RAS: Add a Corrected Errors Collector
Introduce a simple data structure for collecting correctable errors along with accessors. More detailed description in the code itself. The error decoding is done with the decoding chain now and mce_first_notifier() gets to see the error first and the CEC decides whether to log it and then the rest of the chain doesn't hear about it - basically the main reason for the CE collector - or to continue running the notifiers. When the CEC hits the action threshold, it will try to soft-offine the page containing the ECC and then the whole decoding chain gets to see the error. Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/20170327093304.10683-5-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
Этот коммит содержится в:
Borislav Petkov
коммит произвёл
Ingo Molnar
Ingo Molnar
родитель
e64edfcce9
Коммит
011d826111
@@ -35,6 +35,7 @@
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#include <linux/poll.h>
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#include <linux/nmi.h>
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#include <linux/cpu.h>
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#include <linux/ras.h>
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#include <linux/smp.h>
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#include <linux/fs.h>
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#include <linux/mm.h>
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@@ -160,47 +161,8 @@ static struct mce_log_buffer mcelog_buf = {
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void mce_log(struct mce *m)
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{
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unsigned next, entry;
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/* Emit the trace record: */
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trace_mce_record(m);
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if (!mce_gen_pool_add(m))
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irq_work_queue(&mce_irq_work);
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wmb();
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for (;;) {
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entry = mce_log_get_idx_check(mcelog_buf.next);
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for (;;) {
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/*
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* When the buffer fills up discard new entries.
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* Assume that the earlier errors are the more
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* interesting ones:
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*/
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if (entry >= MCE_LOG_LEN) {
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set_bit(MCE_OVERFLOW,
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(unsigned long *)&mcelog_buf.flags);
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return;
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}
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/* Old left over entry. Skip: */
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if (mcelog_buf.entry[entry].finished) {
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entry++;
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continue;
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}
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break;
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}
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smp_rmb();
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next = entry + 1;
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if (cmpxchg(&mcelog_buf.next, entry, next) == entry)
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break;
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}
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memcpy(mcelog_buf.entry + entry, m, sizeof(struct mce));
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wmb();
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mcelog_buf.entry[entry].finished = 1;
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wmb();
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set_bit(0, &mce_need_notify);
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}
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void mce_inject_log(struct mce *m)
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@@ -213,6 +175,12 @@ EXPORT_SYMBOL_GPL(mce_inject_log);
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static struct notifier_block mce_srao_nb;
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/*
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* We run the default notifier if we have only the SRAO, the first and the
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* default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
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* notifiers registered on the chain.
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*/
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#define NUM_DEFAULT_NOTIFIERS 3
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static atomic_t num_notifiers;
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void mce_register_decode_chain(struct notifier_block *nb)
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@@ -522,7 +490,6 @@ static void mce_schedule_work(void)
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static void mce_irq_work_cb(struct irq_work *entry)
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{
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mce_notify_irq();
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mce_schedule_work();
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}
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@@ -565,6 +532,111 @@ static int mce_usable_address(struct mce *m)
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return 1;
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}
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static bool memory_error(struct mce *m)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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if (c->x86_vendor == X86_VENDOR_AMD) {
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/* ErrCodeExt[20:16] */
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u8 xec = (m->status >> 16) & 0x1f;
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return (xec == 0x0 || xec == 0x8);
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} else if (c->x86_vendor == X86_VENDOR_INTEL) {
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/*
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* Intel SDM Volume 3B - 15.9.2 Compound Error Codes
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*
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* Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
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* indicating a memory error. Bit 8 is used for indicating a
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* cache hierarchy error. The combination of bit 2 and bit 3
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* is used for indicating a `generic' cache hierarchy error
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* But we can't just blindly check the above bits, because if
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* bit 11 is set, then it is a bus/interconnect error - and
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* either way the above bits just gives more detail on what
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* bus/interconnect error happened. Note that bit 12 can be
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* ignored, as it's the "filter" bit.
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*/
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return (m->status & 0xef80) == BIT(7) ||
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(m->status & 0xef00) == BIT(8) ||
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(m->status & 0xeffc) == 0xc;
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}
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return false;
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}
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static bool cec_add_mce(struct mce *m)
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{
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if (!m)
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return false;
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/* We eat only correctable DRAM errors with usable addresses. */
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if (memory_error(m) &&
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!(m->status & MCI_STATUS_UC) &&
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mce_usable_address(m))
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if (!cec_add_elem(m->addr >> PAGE_SHIFT))
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return true;
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return false;
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}
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static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
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void *data)
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{
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struct mce *m = (struct mce *)data;
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unsigned int next, entry;
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if (!m)
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return NOTIFY_DONE;
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if (cec_add_mce(m))
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return NOTIFY_STOP;
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/* Emit the trace record: */
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trace_mce_record(m);
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wmb();
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for (;;) {
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entry = mce_log_get_idx_check(mcelog_buf.next);
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for (;;) {
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/*
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* When the buffer fills up discard new entries.
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* Assume that the earlier errors are the more
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* interesting ones:
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*/
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if (entry >= MCE_LOG_LEN) {
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set_bit(MCE_OVERFLOW,
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(unsigned long *)&mcelog_buf.flags);
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return NOTIFY_DONE;
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}
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/* Old left over entry. Skip: */
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if (mcelog_buf.entry[entry].finished) {
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entry++;
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continue;
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}
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break;
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}
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smp_rmb();
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next = entry + 1;
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if (cmpxchg(&mcelog_buf.next, entry, next) == entry)
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break;
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}
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memcpy(mcelog_buf.entry + entry, m, sizeof(struct mce));
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wmb();
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mcelog_buf.entry[entry].finished = 1;
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wmb();
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set_bit(0, &mce_need_notify);
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mce_notify_irq();
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return NOTIFY_DONE;
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}
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static struct notifier_block first_nb = {
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.notifier_call = mce_first_notifier,
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.priority = MCE_PRIO_FIRST,
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};
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static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
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void *data)
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{
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@@ -594,11 +666,7 @@ static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
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if (!m)
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return NOTIFY_DONE;
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/*
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* Run the default notifier if we have only the SRAO
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* notifier and us registered.
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*/
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if (atomic_read(&num_notifiers) > 2)
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if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
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return NOTIFY_DONE;
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/* Don't print when mcelog is running */
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@@ -655,37 +723,6 @@ static void mce_read_aux(struct mce *m, int i)
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}
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}
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static bool memory_error(struct mce *m)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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if (c->x86_vendor == X86_VENDOR_AMD) {
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/* ErrCodeExt[20:16] */
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u8 xec = (m->status >> 16) & 0x1f;
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return (xec == 0x0 || xec == 0x8);
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} else if (c->x86_vendor == X86_VENDOR_INTEL) {
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/*
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* Intel SDM Volume 3B - 15.9.2 Compound Error Codes
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*
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* Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
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* indicating a memory error. Bit 8 is used for indicating a
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* cache hierarchy error. The combination of bit 2 and bit 3
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* is used for indicating a `generic' cache hierarchy error
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* But we can't just blindly check the above bits, because if
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* bit 11 is set, then it is a bus/interconnect error - and
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* either way the above bits just gives more detail on what
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* bus/interconnect error happened. Note that bit 12 can be
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* ignored, as it's the "filter" bit.
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*/
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return (m->status & 0xef80) == BIT(7) ||
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(m->status & 0xef00) == BIT(8) ||
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(m->status & 0xeffc) == 0xc;
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}
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return false;
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}
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DEFINE_PER_CPU(unsigned, mce_poll_count);
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/*
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@@ -2167,6 +2204,7 @@ __setup("mce", mcheck_enable);
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int __init mcheck_init(void)
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{
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mcheck_intel_therm_init();
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mce_register_decode_chain(&first_nb);
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mce_register_decode_chain(&mce_srao_nb);
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mce_register_decode_chain(&mce_default_nb);
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mcheck_vendor_init_severity();
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@@ -2716,6 +2754,7 @@ static int __init mcheck_late_init(void)
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static_branch_inc(&mcsafe_key);
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mcheck_debugfs_init();
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cec_init();
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/*
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* Flush out everything that has been logged during early boot, now that
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