Merge tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux into drm-misc-next
Main pull request for drm for 4.10 kernel - resync drm-misc with full 4.10 state (2 new drivers) so that we can start pulling in all the refactorings for 4.11! Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
This commit is contained in:
Daniel Vetter
112
Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
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112
Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
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Amlogic Meson Display Controller
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================================
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The Amlogic Meson Display controller is composed of several components
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that are going to be documented below:
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DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
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| vd1 _______ _____________ _________________ | |
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D |-------| |----| | | | | HDMI PLL |
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D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
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R |-------| |----| Processing | | | | |
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| osd2 | | | |---| Enci ----------|----|-----VDAC------|
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R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
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A | osd1 | | | Blenders | | Encl ----------|----|---------------|
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M |-------|______|----|____________| |________________| | |
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___|__________________________________________________________|_______________|
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VIU: Video Input Unit
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---------------------
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The Video Input Unit is in charge of the pixel scanout from the DDR memory.
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It fetches the frames addresses, stride and parameters from the "Canvas" memory.
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This part is also in charge of the CSC (Colorspace Conversion).
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It can handle 2 OSD Planes and 2 Video Planes.
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VPP: Video Post Processing
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--------------------------
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The Video Post Processing is in charge of the scaling and blending of the
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various planes into a single pixel stream.
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There is a special "pre-blending" used by the video planes with a dedicated
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scaler and a "post-blending" to merge with the OSD Planes.
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The OSD planes also have a dedicated scaler for one of the OSD.
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VENC: Video Encoders
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--------------------
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The VENC is composed of the multiple pixel encoders :
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- ENCI : Interlace Video encoder for CVBS and Interlace HDMI
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- ENCP : Progressive Video Encoder for HDMI
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- ENCL : LCD LVDS Encoder
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The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
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tree and provides the scanout clock to the VPP and VIU.
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The ENCI is connected to a single VDAC for Composite Output.
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The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
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Device Tree Bindings:
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---------------------
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VPU: Video Processing Unit
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--------------------------
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Required properties:
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- compatible: value should be different for each SoC family as :
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- GXBB (S905) : "amlogic,meson-gxbb-vpu"
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- GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
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- GXM (S912) : "amlogic,meson-gxm-vpu"
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followed by the common "amlogic,meson-gx-vpu"
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- reg: base address and size of he following memory-mapped regions :
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- vpu
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- hhi
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- dmc
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- reg-names: should contain the names of the previous memory regions
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- interrupts: should contain the VENC Vsync interrupt number
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Required nodes:
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The connections to the VPU output video ports are modeled using the OF graph
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bindings specified in Documentation/devicetree/bindings/graph.txt.
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The following table lists for each supported model the port number
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corresponding to each VPU output.
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Port 0 Port 1
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-----------------------------------------
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S905 (GXBB) CVBS VDAC HDMI-TX
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S905X (GXL) CVBS VDAC HDMI-TX
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S905D (GXL) CVBS VDAC HDMI-TX
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S912 (GXM) CVBS VDAC HDMI-TX
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Example:
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tv-connector {
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compatible = "composite-video-connector";
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port {
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tv_connector_in: endpoint {
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remote-endpoint = <&cvbs_vdac_out>;
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};
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};
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};
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vpu: vpu@d0100000 {
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compatible = "amlogic,meson-gxbb-vpu";
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reg = <0x0 0xd0100000 0x0 0x100000>,
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<0x0 0xc883c000 0x0 0x1000>,
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<0x0 0xc8838000 0x0 0x1000>;
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reg-names = "vpu", "hhi", "dmc";
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* CVBS VDAC output port */
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port@0 {
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reg = <0>;
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cvbs_vdac_out: endpoint {
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remote-endpoint = <&tv_connector_in>;
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};
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};
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};
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@@ -43,6 +43,13 @@ Required properties for DPI:
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- port: Port node with a single endpoint connecting to the panel
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device, as defined in [1]
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Required properties for VEC:
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- compatible: Should be "brcm,bcm2835-vec"
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- reg: Physical base address and length of the registers
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- clocks: The core clock the unit runs on
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- interrupts: The interrupt number
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See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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Required properties for V3D:
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- compatible: Should be "brcm,bcm2835-v3d"
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- reg: Physical base address and length of the V3D's registers
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@@ -92,6 +99,13 @@ dpi: dpi@7e208000 {
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};
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};
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vec: vec@7e806000 {
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compatible = "brcm,bcm2835-vec";
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reg = <0x7e806000 0x1000>;
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clocks = <&clocks BCM2835_CLOCK_VEC>;
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interrupts = <2 27>;
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};
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v3d: v3d@7ec00000 {
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compatible = "brcm,bcm2835-v3d";
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reg = <0x7ec00000 0x1000>;
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@@ -1,20 +1,57 @@
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* Freescale MXS LCD Interface (LCDIF)
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New bindings:
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=============
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Required properties:
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- compatible: Should be "fsl,<chip>-lcdif". Supported chips include
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imx23 and imx28.
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- reg: Address and length of the register set for lcdif
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- interrupts: Should contain lcdif interrupts
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- display : phandle to display node (see below for details)
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- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
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Should be "fsl,imx28-lcdif" for i.MX28.
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Should be "fsl,imx6sx-lcdif" for i.MX6SX.
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- reg: Address and length of the register set for LCDIF
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- interrupts: Should contain LCDIF interrupt
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- clocks: A list of phandle + clock-specifier pairs, one for each
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entry in 'clock-names'.
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- clock-names: A list of clock names. For MXSFB it should contain:
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- "pix" for the LCDIF block clock
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- (MX6SX-only) "axi", "disp_axi" for the bus interface clock
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Required sub-nodes:
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- port: The connection to an encoder chip.
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Example:
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lcdif1: display-controller@2220000 {
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compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
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reg = <0x02220000 0x4000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
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<&clks IMX6SX_CLK_LCDIF_APB>,
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<&clks IMX6SX_CLK_DISPLAY_AXI>;
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clock-names = "pix", "axi", "disp_axi";
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port {
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parallel_out: endpoint {
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remote-endpoint = <&panel_in_parallel>;
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};
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};
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};
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Deprecated bindings:
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====================
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Required properties:
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- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
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Should be "fsl,imx28-lcdif" for i.MX28.
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- reg: Address and length of the register set for LCDIF
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- interrupts: Should contain LCDIF interrupts
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- display: phandle to display node (see below for details)
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* display node
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Required properties:
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- bits-per-pixel : <16> for RGB565, <32> for RGB888/666.
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- bus-width : number of data lines. Could be <8>, <16>, <18> or <24>.
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- bits-per-pixel: <16> for RGB565, <32> for RGB888/666.
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- bus-width: number of data lines. Could be <8>, <16>, <18> or <24>.
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Required sub-node:
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- display-timings : Refer to binding doc display-timing.txt for details.
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- display-timings: Refer to binding doc display-timing.txt for details.
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Examples:
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@@ -0,0 +1,7 @@
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AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel
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Required properties:
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- compatible: should be "auo,g133han01"
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@@ -0,0 +1,7 @@
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AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel
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Required properties:
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- compatible: should be "auo,g185han01"
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@@ -0,0 +1,7 @@
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AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel
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Required properties:
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- compatible: should be "auo,t215hvn01"
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@@ -0,0 +1,7 @@
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Chunghwa Picture Tubes Ltd. 7" WXGA TFT LCD panel
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Required properties:
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- compatible: should be "chunghwa,claa070wp03xg"
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@@ -0,0 +1,7 @@
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New Vision Display 7.0" 800 RGB x 480 TFT LCD panel
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Required properties:
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- compatible: should be "nvd,9128"
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@@ -0,0 +1,36 @@
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Sharp 15" LQ150X1LG11 XGA TFT LCD panel
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Required properties:
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- compatible: should be "sharp,lq150x1lg11"
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- power-supply: regulator to provide the VCC supply voltage (3.3 volts)
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Optional properties:
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- backlight: phandle of the backlight device
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- rlud-gpios: a single GPIO for the RL/UD (rotate 180 degrees) pin.
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- sellvds-gpios: a single GPIO for the SELLVDS pin.
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If rlud-gpios and/or sellvds-gpios are not specified, the RL/UD and/or SELLVDS
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pins are assumed to be handled appropriately by the hardware.
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Example:
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm 0 100000>; /* VBR */
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brightness-levels = <0 20 40 60 80 100>;
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default-brightness-level = <2>;
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power-supply = <&vdd_12v_reg>; /* VDD */
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enable-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; /* XSTABY */
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};
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panel {
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compatible = "sharp,lq150x1lg11";
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power-supply = <&vcc_3v3_reg>; /* VCC */
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backlight = <&backlight>;
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rlud-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* RL/UD */
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sellvds-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; /* SELLVDS */
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};
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@@ -187,6 +187,7 @@ netgear NETGEAR
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netlogic Broadcom Corporation (formerly NetLogic Microsystems)
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netxeon Shenzhen Netxeon Technology CO., LTD
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newhaven Newhaven Display International
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nvd New Vision Display
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nintendo Nintendo
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nokia Nokia
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nuvoton Nuvoton Technology Corporation
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