usb: dwc3: add dis_del_phy_power_chg_quirk
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu <william.wu@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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@@ -448,6 +448,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
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if (dwc->dis_u3_susphy_quirk)
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reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
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if (dwc->dis_del_phy_power_chg_quirk)
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reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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@@ -947,6 +950,8 @@ static int dwc3_probe(struct platform_device *pdev)
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"snps,dis_rxdet_inp3_quirk");
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dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
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"snps,dis-u2-freeclk-exists-quirk");
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dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
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"snps,dis-del-phy-power-chg-quirk");
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dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
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"snps,tx_de_emphasis_quirk");
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@@ -818,6 +818,8 @@ struct dwc3_scratchpad_array {
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* @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
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* in GUSB2PHYCFG, specify that USB2 PHY doesn't
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* provide a free-running PHY clock.
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* @dis_del_phy_power_chg_quirk: set if we disable delay phy power
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* change quirk.
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* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
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* @tx_de_emphasis: Tx de-emphasis value
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* 0 - -6dB de-emphasis
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@@ -963,6 +965,7 @@ struct dwc3 {
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unsigned dis_enblslpm_quirk:1;
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unsigned dis_rxdet_inp3_quirk:1;
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unsigned dis_u2_freeclk_exists_quirk:1;
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unsigned dis_del_phy_power_chg_quirk:1;
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unsigned tx_de_emphasis_quirk:1;
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unsigned tx_de_emphasis:2;
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