ARM: shmobile: sh73a0: Common clock framework DT description
Declares all sh73a0 clocks supported by the legacy clock framework. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Ulrich Hecht
committed by
Simon Horman
Simon Horman
parent
4452164e7b
commit
00df611376
@@ -10,6 +10,7 @@
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/sh73a0-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@@ -322,4 +323,332 @@
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interrupts = <0 146 0x4>;
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status = "disabled";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* External root clocks */
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extalr_clk: extalr_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "extalr";
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};
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extal1_clk: extal1_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "extal1";
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};
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extal2_clk: extal2_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "extal2";
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};
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extcki_clk: extcki_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "extcki";
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};
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fsiack_clk: fsiack_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsiack";
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};
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fsibck_clk: fsibck_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsibck";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,sh73a0-cpg-clocks";
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reg = <0xe6150000 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll2",
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"pll3", "dsi0phy", "dsi1phy",
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"zg", "m3", "b", "m1", "m2",
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"z", "zx", "hp";
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};
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/* Variable factor clocks (DIV6) */
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vclk1_clk: vclk1_clk@e6150008 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150008 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "vclk1";
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};
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vclk2_clk: vclk2_clk@e615000c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615000c 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "vclk2";
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};
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vclk3_clk: vclk3_clk@e615001c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615001c 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "vclk3";
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};
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zb_clk: zb_clk@e6150010 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150010 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "zb";
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};
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flctl_clk: flctl_clk@e6150014 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150014 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "flctlck";
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};
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sdhi0_clk: sdhi0_clk@e6150074 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150074 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi0ck";
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};
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sdhi1_clk: sdhi1_clk@e6150078 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150078 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi1ck";
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};
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sdhi2_clk: sdhi2_clk@e615007c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615007c 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi2ck";
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};
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fsia_clk: fsia_clk@e6150018 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150018 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "fsia";
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};
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fsib_clk: fsib_clk@e6150090 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150090 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "fsib";
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};
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sub_clk: sub_clk@e6150080 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150080 4>;
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clocks = <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sub";
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};
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spua_clk: spua_clk@e6150084 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150084 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "spua";
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};
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spuv_clk: spuv_clk@e6150094 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150094 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "spuv";
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};
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msu_clk: msu_clk@e6150088 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150088 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "msu";
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};
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hsi_clk: hsi_clk@e615008c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615008c 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "hsi";
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};
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mfg1_clk: mfg1_clk@e6150098 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150098 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mfg1";
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};
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mfg2_clk: mfg2_clk@e615009c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615009c 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mfg2";
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};
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dsit_clk: dsit_clk@e6150060 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150060 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "dsit";
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};
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dsi0p_clk: dsi0p_clk@e6150064 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150064 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "dsi0pck";
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};
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/* Fixed factor clocks */
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main_div2_clk: main_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "main_div2";
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};
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pll1_div2_clk: pll1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "pll1_div2";
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};
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pll1_div7_clk: pll1_div7_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <7>;
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clock-mult = <1>;
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clock-output-names = "pll1_div7";
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};
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pll1_div13_clk: pll1_div13_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <13>;
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clock-mult = <1>;
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clock-output-names = "pll1_div13";
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};
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twd_clk: twd_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks SH73A0_CLK_Z>;
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clock-output-names = "twd";
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};
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/* Gate clocks */
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mstp0_clks: mstp0_clks@e6150130 {
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compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150130 4>, <0xe6150030 4>;
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clocks = <&cpg_clocks SH73A0_CLK_HP>;
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#clock-cells = <1>;
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clock-indices = <
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SH73A0_CLK_IIC2
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>;
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clock-output-names =
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"iic2";
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};
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mstp1_clks: mstp1_clks@e6150134 {
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compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150134 4>, <0xe6150038 4>;
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clocks = <&cpg_clocks SH73A0_CLK_B>,
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<&cpg_clocks SH73A0_CLK_B>,
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<&cpg_clocks SH73A0_CLK_B>,
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<&cpg_clocks SH73A0_CLK_B>,
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<&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
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<&cpg_clocks SH73A0_CLK_HP>,
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<&cpg_clocks SH73A0_CLK_ZG>,
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<&cpg_clocks SH73A0_CLK_B>;
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#clock-cells = <1>;
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clock-indices = <
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SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
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SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
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SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
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SH73A0_CLK_IIC0 SH73A0_CLK_SGX
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SH73A0_CLK_LCDC0
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>;
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clock-output-names =
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"ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
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"tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
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};
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150138 4>, <0xe6150040 4>;
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clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
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<&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
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<&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
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<&sub_clk>, <&sub_clk>;
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#clock-cells = <1>;
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clock-indices = <
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SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
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SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
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SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
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SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
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SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
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>;
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clock-output-names =
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"scifa7", "sy_dmac", "mp_dmac", "scifa5",
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"scifb", "scifa0", "scifa1", "scifa2",
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"scifa3", "scifa4";
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};
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mstp3_clks: mstp3_clks@e615013c {
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compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe615013c 4>, <0xe6150048 4>;
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clocks = <&sub_clk>, <&extalr_clk>,
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<&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
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<&cpg_clocks SH73A0_CLK_HP>,
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<&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
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<&sdhi0_clk>, <&sdhi1_clk>,
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<&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
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<&main_div2_clk>, <&main_div2_clk>,
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<&main_div2_clk>, <&main_div2_clk>,
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<&main_div2_clk>;
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#clock-cells = <1>;
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clock-indices = <
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SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
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SH73A0_CLK_FSI SH73A0_CLK_IRDA
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SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
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SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
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SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
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SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
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SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
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SH73A0_CLK_TPU4
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>;
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clock-output-names =
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"scifa6", "cmt1", "fsi", "irda", "iic1",
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"usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
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"tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
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};
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mstp4_clks: mstp4_clks@e6150140 {
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compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150140 4>, <0xe615004c 4>;
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clocks = <&cpg_clocks SH73A0_CLK_HP>,
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<&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
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#clock-cells = <1>;
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clock-indices = <
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SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
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SH73A0_CLK_KEYSC
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>;
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clock-output-names =
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"iic3", "iic4", "keysc";
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};
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};
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};
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