Merge tag 'mmc-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC updates from Ulf Hansson: "This time, this pull request contains changes crossing subsystems and archs/platforms, which is mainly because of a bigger modernization of moving from legacy GPIO to GPIO descriptors for MMC (by Linus Walleij). Additionally, once again, I am funneling changes to drivers/misc/cardreader/* and drivers/memstick/* through my MMC tree, mostly due to that we lack a maintainer for these. Summary: MMC core: - Cleanup BKOPS support - Introduce MMC_CAP_SYNC_RUNTIME_PM - slot-gpio: Delete legacy slot GPIO handling MMC host: - alcor: Add new mmc host driver for Alcor Micro PCI based cardreader - bcm2835: Several improvements to better recover from errors - jz4740: Rework and fixup pre|post_req support - mediatek: Add support for SDIO IRQs - meson-gx: Improve clock phase management - meson-gx: Stop descriptor on errors - mmci: Complete the sbc error path by sending a stop command - renesas_sdhi/tmio: Fixup reset/resume operations - renesas_sdhi: Add support for r8a774c0 and R7S9210 - renesas_sdhi: Whitelist R8A77990 SDHI - renesas_sdhi: Fixup eMMC HS400 compatibility issues for H3 and M3-W - rtsx_usb_sdmmc: Re-work card detection/removal support - rtsx_usb_sdmmc: Re-work runtime PM support - sdhci: Fix timeout loops for some variant drivers - sdhci: Improve support for error handling due to failing commands - sdhci-acpi/pci: Disable LED control for Intel BYT-based controllers - sdhci_am654: Add new SDHCI variant driver to support TI's AM654 SOCs - sdhci-of-esdhc: Add support for eMMC HS400 mode - sdhci-omap: Fixup reset support - sdhci-omap: Workaround errata regarding SDR104/HS200 tuning failures - sdhci-msm: Fixup sporadic write transfers issues for SDR104/HS200 - sdhci-msm: Fixup dynamical clock gating issues - various: Complete converting all hosts into using slot GPIO descriptors Other: - Move GPIO mmc platform data for mips/sh/arm to GPIO descriptors - Add new Alcor Micro cardreader PCI driver - Support runtime power management for memstick rtsx_usb_ms driver - Use USB remote wakeups for card detection for rtsx_usb misc driver" * tag 'mmc-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (99 commits) mmc: mediatek: Add MMC_CAP_SDIO_IRQ support mmc: renesas_sdhi_internal_dmac: Whitelist r8a774c0 dt-bindings: mmc: renesas_sdhi: Add r8a774c0 support mmc: core: Cleanup BKOPS support mmc: core: Drop redundant check in mmc_send_hpi_cmd() mmc: sdhci-omap: Workaround errata regarding SDR104/HS200 tuning failures (i929) dt-bindings: sdhci-omap: Add note for cpu_thermal mmc: sdhci-acpi: Disable LED control for Intel BYT-based controllers mmc: sdhci-pci: Disable LED control for Intel BYT-based controllers mmc: sdhci: Add quirk to disable LED control mmc: mmci: add variant property to set command stop bit misc: alcor_pci: fix spelling mistake "invailid" -> "invalid" mmc: meson-gx: add signal resampling mmc: meson-gx: align default phase on soc vendor tree mmc: meson-gx: remove useless lock mmc: meson-gx: make sure the descriptor is stopped on errors mmc: sdhci_am654: Add Initial Support for AM654 SDHCI driver dt-bindings: mmc: sdhci-of-arasan: Add deprecated message for AM65 dt-bindings: mmc: sdhci-am654: Document bindings for the host controllers on TI's AM654 SOCs mmc: sdhci-msm: avoid unused function warning ...
This commit is contained in:
Linus Torvalds
286
include/linux/alcor_pci.h
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286
include/linux/alcor_pci.h
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@@ -0,0 +1,286 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de>
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*
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* Driver for Alcor Micro AU6601 and AU6621 controllers
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*/
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#ifndef __ALCOR_PCI_H
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#define __ALCOR_PCI_H
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#define ALCOR_SD_CARD 0
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#define ALCOR_MS_CARD 1
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#define DRV_NAME_ALCOR_PCI_SDMMC "alcor_sdmmc"
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#define DRV_NAME_ALCOR_PCI_MS "alcor_ms"
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#define PCI_ID_ALCOR_MICRO 0x1AEA
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#define PCI_ID_AU6601 0x6601
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#define PCI_ID_AU6621 0x6621
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#define MHZ_TO_HZ(freq) ((freq) * 1000 * 1000)
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#define AU6601_BASE_CLOCK 31000000
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#define AU6601_MIN_CLOCK 150000
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#define AU6601_MAX_CLOCK 208000000
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#define AU6601_MAX_DMA_SEGMENTS 1
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#define AU6601_MAX_PIO_SEGMENTS 1
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#define AU6601_MAX_DMA_BLOCK_SIZE 0x1000
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#define AU6601_MAX_PIO_BLOCK_SIZE 0x200
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#define AU6601_MAX_DMA_BLOCKS 1
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#define AU6601_DMA_LOCAL_SEGMENTS 1
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/* registers spotter by reverse engineering but still
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* with unknown functionality:
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* 0x10 - ADMA phy address. AU6621 only?
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* 0x51 - LED ctrl?
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* 0x52 - unknown
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* 0x61 - LED related? Always toggled BIT0
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* 0x63 - Same as 0x61?
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* 0x77 - unknown
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*/
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/* SDMA phy address. Higher then 0x0800.0000?
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* The au6601 and au6621 have different DMA engines with different issues. One
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* For example au6621 engine is triggered by addr change. No other interaction
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* is needed. This means, if we get two buffers with same address, then engine
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* will stall.
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*/
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#define AU6601_REG_SDMA_ADDR 0x00
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#define AU6601_SDMA_MASK 0xffffffff
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#define AU6601_DMA_BOUNDARY 0x05
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#define AU6621_DMA_PAGE_CNT 0x05
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/* PIO */
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#define AU6601_REG_BUFFER 0x08
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/* ADMA ctrl? AU6621 only. */
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#define AU6621_DMA_CTRL 0x0c
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#define AU6621_DMA_ENABLE BIT(0)
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/* CMD index */
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#define AU6601_REG_CMD_OPCODE 0x23
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/* CMD parametr */
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#define AU6601_REG_CMD_ARG 0x24
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/* CMD response 4x4 Bytes */
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#define AU6601_REG_CMD_RSP0 0x30
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#define AU6601_REG_CMD_RSP1 0x34
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#define AU6601_REG_CMD_RSP2 0x38
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#define AU6601_REG_CMD_RSP3 0x3C
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/* default timeout set to 125: 125 * 40ms = 5 sec
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* how exactly it is calculated?
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*/
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#define AU6601_TIME_OUT_CTRL 0x69
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/* Block size for SDMA or PIO */
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#define AU6601_REG_BLOCK_SIZE 0x6c
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/* Some power related reg, used together with AU6601_OUTPUT_ENABLE */
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#define AU6601_POWER_CONTROL 0x70
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/* PLL ctrl */
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#define AU6601_CLK_SELECT 0x72
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#define AU6601_CLK_OVER_CLK 0x80
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#define AU6601_CLK_384_MHZ 0x30
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#define AU6601_CLK_125_MHZ 0x20
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#define AU6601_CLK_48_MHZ 0x10
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#define AU6601_CLK_EXT_PLL 0x04
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#define AU6601_CLK_X2_MODE 0x02
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#define AU6601_CLK_ENABLE 0x01
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#define AU6601_CLK_31_25_MHZ 0x00
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#define AU6601_CLK_DIVIDER 0x73
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#define AU6601_INTERFACE_MODE_CTRL 0x74
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#define AU6601_DLINK_MODE 0x80
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#define AU6601_INTERRUPT_DELAY_TIME 0x40
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#define AU6601_SIGNAL_REQ_CTRL 0x30
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#define AU6601_MS_CARD_WP BIT(3)
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#define AU6601_SD_CARD_WP BIT(0)
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/* same register values are used for:
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* - AU6601_OUTPUT_ENABLE
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* - AU6601_POWER_CONTROL
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*/
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#define AU6601_ACTIVE_CTRL 0x75
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#define AU6601_XD_CARD BIT(4)
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/* AU6601_MS_CARD_ACTIVE - will cativate MS card section? */
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#define AU6601_MS_CARD BIT(3)
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#define AU6601_SD_CARD BIT(0)
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/* card slot state. It should automatically detect type of
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* the card
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*/
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#define AU6601_DETECT_STATUS 0x76
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#define AU6601_DETECT_EN BIT(7)
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#define AU6601_MS_DETECTED BIT(3)
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#define AU6601_SD_DETECTED BIT(0)
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#define AU6601_DETECT_STATUS_M 0xf
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#define AU6601_REG_SW_RESET 0x79
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#define AU6601_BUF_CTRL_RESET BIT(7)
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#define AU6601_RESET_DATA BIT(3)
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#define AU6601_RESET_CMD BIT(0)
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#define AU6601_OUTPUT_ENABLE 0x7a
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#define AU6601_PAD_DRIVE0 0x7b
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#define AU6601_PAD_DRIVE1 0x7c
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#define AU6601_PAD_DRIVE2 0x7d
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/* read EEPROM? */
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#define AU6601_FUNCTION 0x7f
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#define AU6601_CMD_XFER_CTRL 0x81
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#define AU6601_CMD_17_BYTE_CRC 0xc0
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#define AU6601_CMD_6_BYTE_WO_CRC 0x80
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#define AU6601_CMD_6_BYTE_CRC 0x40
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#define AU6601_CMD_START_XFER 0x20
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#define AU6601_CMD_STOP_WAIT_RDY 0x10
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#define AU6601_CMD_NO_RESP 0x00
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#define AU6601_REG_BUS_CTRL 0x82
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#define AU6601_BUS_WIDTH_4BIT 0x20
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#define AU6601_BUS_WIDTH_8BIT 0x10
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#define AU6601_BUS_WIDTH_1BIT 0x00
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#define AU6601_DATA_XFER_CTRL 0x83
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#define AU6601_DATA_WRITE BIT(7)
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#define AU6601_DATA_DMA_MODE BIT(6)
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#define AU6601_DATA_START_XFER BIT(0)
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#define AU6601_DATA_PIN_STATE 0x84
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#define AU6601_BUS_STAT_CMD BIT(15)
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/* BIT(4) - BIT(7) are permanently 1.
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* May be reserved or not attached DAT4-DAT7
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*/
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#define AU6601_BUS_STAT_DAT3 BIT(3)
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#define AU6601_BUS_STAT_DAT2 BIT(2)
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#define AU6601_BUS_STAT_DAT1 BIT(1)
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#define AU6601_BUS_STAT_DAT0 BIT(0)
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#define AU6601_BUS_STAT_DAT_MASK 0xf
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#define AU6601_OPT 0x85
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#define AU6601_OPT_CMD_LINE_LEVEL 0x80
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#define AU6601_OPT_NCRC_16_CLK BIT(4)
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#define AU6601_OPT_CMD_NWT BIT(3)
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#define AU6601_OPT_STOP_CLK BIT(2)
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#define AU6601_OPT_DDR_MODE BIT(1)
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#define AU6601_OPT_SD_18V BIT(0)
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#define AU6601_CLK_DELAY 0x86
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#define AU6601_CLK_DATA_POSITIVE_EDGE 0x80
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#define AU6601_CLK_CMD_POSITIVE_EDGE 0x40
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#define AU6601_CLK_POSITIVE_EDGE_ALL (AU6601_CLK_CMD_POSITIVE_EDGE \
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| AU6601_CLK_DATA_POSITIVE_EDGE)
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#define AU6601_REG_INT_STATUS 0x90
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#define AU6601_REG_INT_ENABLE 0x94
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#define AU6601_INT_DATA_END_BIT_ERR BIT(22)
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#define AU6601_INT_DATA_CRC_ERR BIT(21)
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#define AU6601_INT_DATA_TIMEOUT_ERR BIT(20)
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#define AU6601_INT_CMD_INDEX_ERR BIT(19)
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#define AU6601_INT_CMD_END_BIT_ERR BIT(18)
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#define AU6601_INT_CMD_CRC_ERR BIT(17)
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#define AU6601_INT_CMD_TIMEOUT_ERR BIT(16)
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#define AU6601_INT_ERROR BIT(15)
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#define AU6601_INT_OVER_CURRENT_ERR BIT(8)
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#define AU6601_INT_CARD_INSERT BIT(7)
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#define AU6601_INT_CARD_REMOVE BIT(6)
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#define AU6601_INT_READ_BUF_RDY BIT(5)
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#define AU6601_INT_WRITE_BUF_RDY BIT(4)
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#define AU6601_INT_DMA_END BIT(3)
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#define AU6601_INT_DATA_END BIT(1)
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#define AU6601_INT_CMD_END BIT(0)
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#define AU6601_INT_NORMAL_MASK 0x00007FFF
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#define AU6601_INT_ERROR_MASK 0xFFFF8000
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#define AU6601_INT_CMD_MASK (AU6601_INT_CMD_END | \
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AU6601_INT_CMD_TIMEOUT_ERR | AU6601_INT_CMD_CRC_ERR | \
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AU6601_INT_CMD_END_BIT_ERR | AU6601_INT_CMD_INDEX_ERR)
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#define AU6601_INT_DATA_MASK (AU6601_INT_DATA_END | AU6601_INT_DMA_END | \
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AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY | \
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AU6601_INT_DATA_TIMEOUT_ERR | AU6601_INT_DATA_CRC_ERR | \
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AU6601_INT_DATA_END_BIT_ERR)
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#define AU6601_INT_ALL_MASK ((u32)-1)
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/* MS_CARD mode registers */
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#define AU6601_MS_STATUS 0xa0
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#define AU6601_MS_BUS_MODE_CTRL 0xa1
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#define AU6601_MS_BUS_8BIT_MODE 0x03
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#define AU6601_MS_BUS_4BIT_MODE 0x01
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#define AU6601_MS_BUS_1BIT_MODE 0x00
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#define AU6601_MS_TPC_CMD 0xa2
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#define AU6601_MS_TPC_READ_PAGE_DATA 0x02
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#define AU6601_MS_TPC_READ_REG 0x04
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#define AU6601_MS_TPC_GET_INT 0x07
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#define AU6601_MS_TPC_WRITE_PAGE_DATA 0x0D
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#define AU6601_MS_TPC_WRITE_REG 0x0B
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#define AU6601_MS_TPC_SET_RW_REG_ADRS 0x08
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#define AU6601_MS_TPC_SET_CMD 0x0E
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#define AU6601_MS_TPC_EX_SET_CMD 0x09
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#define AU6601_MS_TPC_READ_SHORT_DATA 0x03
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#define AU6601_MS_TPC_WRITE_SHORT_DATA 0x0C
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#define AU6601_MS_TRANSFER_MODE 0xa3
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#define AU6601_MS_XFER_INT_TIMEOUT_CHK BIT(2)
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#define AU6601_MS_XFER_DMA_ENABLE BIT(1)
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#define AU6601_MS_XFER_START BIT(0)
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#define AU6601_MS_DATA_PIN_STATE 0xa4
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#define AU6601_MS_INT_STATUS 0xb0
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#define AU6601_MS_INT_ENABLE 0xb4
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#define AU6601_MS_INT_OVER_CURRENT_ERROR BIT(23)
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#define AU6601_MS_INT_DATA_CRC_ERROR BIT(21)
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#define AU6601_MS_INT_INT_TIMEOUT BIT(20)
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#define AU6601_MS_INT_INT_RESP_ERROR BIT(19)
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#define AU6601_MS_INT_CED_ERROR BIT(18)
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#define AU6601_MS_INT_TPC_TIMEOUT BIT(16)
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#define AU6601_MS_INT_ERROR BIT(15)
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#define AU6601_MS_INT_CARD_INSERT BIT(7)
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#define AU6601_MS_INT_CARD_REMOVE BIT(6)
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#define AU6601_MS_INT_BUF_READ_RDY BIT(5)
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#define AU6601_MS_INT_BUF_WRITE_RDY BIT(4)
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#define AU6601_MS_INT_DMA_END BIT(3)
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#define AU6601_MS_INT_TPC_END BIT(1)
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#define AU6601_MS_INT_DATA_MASK 0x00000038
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#define AU6601_MS_INT_TPC_MASK 0x003d8002
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#define AU6601_MS_INT_TPC_ERROR 0x003d0000
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#define ALCOR_PCIE_LINK_CTRL_OFFSET 0x10
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#define ALCOR_PCIE_LINK_CAP_OFFSET 0x0c
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#define ALCOR_CAP_START_OFFSET 0x34
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struct alcor_dev_cfg {
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u8 dma;
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};
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struct alcor_pci_priv {
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struct pci_dev *pdev;
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struct pci_dev *parent_pdev;
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struct device *dev;
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void __iomem *iobase;
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unsigned int irq;
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unsigned long id; /* idr id */
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struct alcor_dev_cfg *cfg;
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/* PCI ASPM related vars */
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int pdev_cap_off;
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u8 pdev_aspm_cap;
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int parent_cap_off;
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u8 parent_aspm_cap;
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u8 ext_config_dev_aspm;
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};
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void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr);
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void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr);
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void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr);
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void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr);
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u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr);
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u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr);
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u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr);
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#endif
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@@ -54,12 +54,8 @@
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* idle before writing to some registers.
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*/
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#define TMIO_MMC_HAS_IDLE_WAIT BIT(4)
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/*
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* A GPIO is used for card hotplug detection. We need an extra flag for this,
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* because 0 is a valid GPIO number too, and requiring users to specify
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* cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
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*/
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#define TMIO_MMC_USE_GPIO_CD BIT(5)
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/* BIT(5) is unused */
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/*
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* Some controllers have CMD12 automatically
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@@ -104,7 +100,6 @@ struct tmio_mmc_data {
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unsigned long capabilities2;
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unsigned long flags;
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u32 ocr_mask; /* available voltages */
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unsigned int cd_gpio;
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int alignment_shift;
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dma_addr_t dma_rx_offset;
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unsigned int max_blk_count;
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@@ -147,6 +147,9 @@ struct mmc_host_ops {
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/* Prepare HS400 target operating frequency depending host driver */
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int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios);
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/* Prepare switch to DDR during the HS400 init sequence */
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int (*hs400_prepare_ddr)(struct mmc_host *host);
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/* Prepare for switching from HS400 to HS200 */
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void (*hs400_downgrade)(struct mmc_host *host);
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@@ -331,7 +334,7 @@ struct mmc_host {
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#define MMC_CAP_UHS (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | \
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MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | \
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MMC_CAP_UHS_DDR50)
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/* (1 << 21) is free for reuse */
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#define MMC_CAP_SYNC_RUNTIME_PM (1 << 21) /* Synced runtime PM suspends. */
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#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
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#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
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#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
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||||
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||||
@@ -17,12 +17,7 @@
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struct mmc_host;
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||||
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int mmc_gpio_get_ro(struct mmc_host *host);
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int mmc_gpio_request_ro(struct mmc_host *host, unsigned int gpio);
|
||||
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int mmc_gpio_get_cd(struct mmc_host *host);
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int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio,
|
||||
unsigned int debounce);
|
||||
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||||
int mmc_gpiod_request_cd(struct mmc_host *host, const char *con_id,
|
||||
unsigned int idx, bool override_active_level,
|
||||
unsigned int debounce, bool *gpio_invert);
|
||||
|
||||
@@ -30,15 +30,11 @@ enum cd_types {
|
||||
*
|
||||
* ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
|
||||
*
|
||||
* @wp_gpio: gpio for write_protect
|
||||
* @cd_gpio: gpio for card_detect interrupt
|
||||
* @wp_type: type of write_protect method (see wp_types enum above)
|
||||
* @cd_type: type of card_detect method (see cd_types enum above)
|
||||
*/
|
||||
|
||||
struct esdhc_platform_data {
|
||||
unsigned int wp_gpio;
|
||||
unsigned int cd_gpio;
|
||||
enum wp_types wp_type;
|
||||
enum cd_types cd_type;
|
||||
int max_bus_width;
|
||||
|
||||
@@ -15,11 +15,7 @@ struct pxamci_platform_data {
|
||||
int (*get_ro)(struct device *);
|
||||
int (*setpower)(struct device *, unsigned int);
|
||||
void (*exit)(struct device *, void *);
|
||||
int gpio_card_detect; /* gpio detecting card insertion */
|
||||
int gpio_card_ro; /* gpio detecting read only toggle */
|
||||
bool gpio_card_ro_invert; /* gpio ro is inverted */
|
||||
int gpio_power; /* gpio powering up MMC bus */
|
||||
bool gpio_power_invert; /* gpio power is inverted */
|
||||
};
|
||||
|
||||
extern void pxa_set_mci_info(struct pxamci_platform_data *info);
|
||||
|
||||
@@ -7,7 +7,6 @@
|
||||
* @no_wprotect: Set this to indicate there is no write-protect switch.
|
||||
* @no_detect: Set this if there is no detect switch.
|
||||
* @wprotect_invert: Invert the default sense of the write protect switch.
|
||||
* @detect_invert: Invert the default sense of the write protect switch.
|
||||
* @use_dma: Set to allow the use of DMA.
|
||||
* @gpio_detect: GPIO number for the card detect line.
|
||||
* @gpio_wprotect: GPIO number for the write protect line.
|
||||
@@ -31,11 +30,8 @@ struct s3c24xx_mci_pdata {
|
||||
unsigned int no_wprotect:1;
|
||||
unsigned int no_detect:1;
|
||||
unsigned int wprotect_invert:1;
|
||||
unsigned int detect_invert:1; /* set => detect active high */
|
||||
unsigned int use_dma:1;
|
||||
|
||||
unsigned int gpio_detect;
|
||||
unsigned int gpio_wprotect;
|
||||
unsigned long ocr_avail;
|
||||
void (*set_power)(unsigned char power_mode,
|
||||
unsigned short vdd);
|
||||
|
||||
@@ -8,11 +8,6 @@
|
||||
struct device;
|
||||
struct mmc_host;
|
||||
|
||||
#define MMC_SPI_USE_CD_GPIO (1 << 0)
|
||||
#define MMC_SPI_USE_RO_GPIO (1 << 1)
|
||||
#define MMC_SPI_CD_GPIO_ACTIVE_LOW (1 << 2)
|
||||
#define MMC_SPI_RO_GPIO_ACTIVE_LOW (1 << 3)
|
||||
|
||||
/* Put this in platform_data of a device being used to manage an MMC/SD
|
||||
* card slot. (Modeled after PXA mmc glue; see that for usage examples.)
|
||||
*
|
||||
@@ -27,16 +22,6 @@ struct mmc_spi_platform_data {
|
||||
void *);
|
||||
void (*exit)(struct device *, void *);
|
||||
|
||||
/*
|
||||
* Card Detect and Read Only GPIOs. To enable debouncing on the card
|
||||
* detect GPIO, set the cd_debounce to the debounce time in
|
||||
* microseconds.
|
||||
*/
|
||||
unsigned int flags;
|
||||
unsigned int cd_gpio;
|
||||
unsigned int cd_debounce;
|
||||
unsigned int ro_gpio;
|
||||
|
||||
/* Capabilities to pass into mmc core (e.g. MMC_CAP_NEEDS_POLL). */
|
||||
unsigned long caps;
|
||||
unsigned long caps2;
|
||||
|
||||
Reference in New Issue
Block a user