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clk: meson: mpll: add rw operation

Selaa lähdekoodia 
This patch adds new callbacks to the meson-mpll driver to control
and set the pll rate. For this, we also need to add the enable bit and
sdm enable bit. The corresponding parameters are added to mpll data
structure.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20170309104154.28295-6-jbrunet@baylibre.com
This commit is contained in:
Jerome Brunet
2017-03-09 11:41:50 +01:00
committed by Michael Turquette
vanhempi b92332eea8
commit 007e6e5c5f
3 muutettua tiedostoa jossa 180 lisäystä ja 6 poistoa
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4
drivers/clk/meson/clkc.h
Näytä tiedosto

@@ -92,8 +92,9 @@ struct meson_clk_mpll {
struct clk_hw hw;
void __iomem *base;
struct parm sdm;
struct parm sdm_en;
struct parm n2;
/* FIXME ssen gate control? */
struct parm en;
spinlock_t *lock;
};
@@ -116,5 +117,6 @@ extern const struct clk_ops meson_clk_pll_ro_ops;
extern const struct clk_ops meson_clk_pll_ops;
extern const struct clk_ops meson_clk_cpu_ops;
extern const struct clk_ops meson_clk_mpll_ro_ops;
extern const struct clk_ops meson_clk_mpll_ops;
#endif /* __CLKC_H */