meson_gxbb_wdt.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2. /*
  3. * Copyright (c) 2016 BayLibre, SAS.
  4. * Author: Neil Armstrong <[email protected]>
  5. *
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/types.h>
  15. #include <linux/watchdog.h>
  16. #define DEFAULT_TIMEOUT 30 /* seconds */
  17. #define GXBB_WDT_CTRL_REG 0x0
  18. #define GXBB_WDT_TCNT_REG 0x8
  19. #define GXBB_WDT_RSET_REG 0xc
  20. #define GXBB_WDT_CTRL_CLKDIV_EN BIT(25)
  21. #define GXBB_WDT_CTRL_CLK_EN BIT(24)
  22. #define GXBB_WDT_CTRL_EE_RESET BIT(21)
  23. #define GXBB_WDT_CTRL_EN BIT(18)
  24. #define GXBB_WDT_CTRL_DIV_MASK (BIT(18) - 1)
  25. #define GXBB_WDT_TCNT_SETUP_MASK (BIT(16) - 1)
  26. #define GXBB_WDT_TCNT_CNT_SHIFT 16
  27. static bool nowayout = WATCHDOG_NOWAYOUT;
  28. module_param(nowayout, bool, 0);
  29. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started default="
  30. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  31. static unsigned int timeout;
  32. module_param(timeout, uint, 0);
  33. MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds="
  34. __MODULE_STRING(DEFAULT_TIMEOUT) ")");
  35. struct meson_gxbb_wdt {
  36. void __iomem *reg_base;
  37. struct watchdog_device wdt_dev;
  38. struct clk *clk;
  39. };
  40. static int meson_gxbb_wdt_start(struct watchdog_device *wdt_dev)
  41. {
  42. struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
  43. writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN,
  44. data->reg_base + GXBB_WDT_CTRL_REG);
  45. return 0;
  46. }
  47. static int meson_gxbb_wdt_stop(struct watchdog_device *wdt_dev)
  48. {
  49. struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
  50. writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN,
  51. data->reg_base + GXBB_WDT_CTRL_REG);
  52. return 0;
  53. }
  54. static int meson_gxbb_wdt_ping(struct watchdog_device *wdt_dev)
  55. {
  56. struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
  57. writel(0, data->reg_base + GXBB_WDT_RSET_REG);
  58. return 0;
  59. }
  60. static int meson_gxbb_wdt_set_timeout(struct watchdog_device *wdt_dev,
  61. unsigned int timeout)
  62. {
  63. struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
  64. unsigned long tcnt = timeout * 1000;
  65. if (tcnt > GXBB_WDT_TCNT_SETUP_MASK)
  66. tcnt = GXBB_WDT_TCNT_SETUP_MASK;
  67. wdt_dev->timeout = timeout;
  68. meson_gxbb_wdt_ping(wdt_dev);
  69. writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG);
  70. return 0;
  71. }
  72. static unsigned int meson_gxbb_wdt_get_timeleft(struct watchdog_device *wdt_dev)
  73. {
  74. struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
  75. unsigned long reg;
  76. reg = readl(data->reg_base + GXBB_WDT_TCNT_REG);
  77. return ((reg & GXBB_WDT_TCNT_SETUP_MASK) -
  78. (reg >> GXBB_WDT_TCNT_CNT_SHIFT)) / 1000;
  79. }
  80. static const struct watchdog_ops meson_gxbb_wdt_ops = {
  81. .start = meson_gxbb_wdt_start,
  82. .stop = meson_gxbb_wdt_stop,
  83. .ping = meson_gxbb_wdt_ping,
  84. .set_timeout = meson_gxbb_wdt_set_timeout,
  85. .get_timeleft = meson_gxbb_wdt_get_timeleft,
  86. };
  87. static const struct watchdog_info meson_gxbb_wdt_info = {
  88. .identity = "Meson GXBB Watchdog",
  89. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
  90. };
  91. static int __maybe_unused meson_gxbb_wdt_resume(struct device *dev)
  92. {
  93. struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
  94. if (watchdog_active(&data->wdt_dev))
  95. meson_gxbb_wdt_start(&data->wdt_dev);
  96. return 0;
  97. }
  98. static int __maybe_unused meson_gxbb_wdt_suspend(struct device *dev)
  99. {
  100. struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
  101. if (watchdog_active(&data->wdt_dev))
  102. meson_gxbb_wdt_stop(&data->wdt_dev);
  103. return 0;
  104. }
  105. static const struct dev_pm_ops meson_gxbb_wdt_pm_ops = {
  106. SET_SYSTEM_SLEEP_PM_OPS(meson_gxbb_wdt_suspend, meson_gxbb_wdt_resume)
  107. };
  108. static const struct of_device_id meson_gxbb_wdt_dt_ids[] = {
  109. { .compatible = "amlogic,meson-gxbb-wdt", },
  110. { /* sentinel */ },
  111. };
  112. MODULE_DEVICE_TABLE(of, meson_gxbb_wdt_dt_ids);
  113. static void meson_clk_disable_unprepare(void *data)
  114. {
  115. clk_disable_unprepare(data);
  116. }
  117. static int meson_gxbb_wdt_probe(struct platform_device *pdev)
  118. {
  119. struct device *dev = &pdev->dev;
  120. struct meson_gxbb_wdt *data;
  121. int ret;
  122. u32 ctrl_reg;
  123. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  124. if (!data)
  125. return -ENOMEM;
  126. data->reg_base = devm_platform_ioremap_resource(pdev, 0);
  127. if (IS_ERR(data->reg_base))
  128. return PTR_ERR(data->reg_base);
  129. data->clk = devm_clk_get(dev, NULL);
  130. if (IS_ERR(data->clk))
  131. return PTR_ERR(data->clk);
  132. ret = clk_prepare_enable(data->clk);
  133. if (ret)
  134. return ret;
  135. ret = devm_add_action_or_reset(dev, meson_clk_disable_unprepare,
  136. data->clk);
  137. if (ret)
  138. return ret;
  139. platform_set_drvdata(pdev, data);
  140. data->wdt_dev.parent = dev;
  141. data->wdt_dev.info = &meson_gxbb_wdt_info;
  142. data->wdt_dev.ops = &meson_gxbb_wdt_ops;
  143. data->wdt_dev.max_hw_heartbeat_ms = GXBB_WDT_TCNT_SETUP_MASK;
  144. data->wdt_dev.min_timeout = 1;
  145. data->wdt_dev.timeout = DEFAULT_TIMEOUT;
  146. watchdog_init_timeout(&data->wdt_dev, timeout, dev);
  147. watchdog_set_nowayout(&data->wdt_dev, nowayout);
  148. watchdog_set_drvdata(&data->wdt_dev, data);
  149. ctrl_reg = readl(data->reg_base + GXBB_WDT_CTRL_REG) &
  150. GXBB_WDT_CTRL_EN;
  151. if (ctrl_reg) {
  152. /* Watchdog is running - keep it running but extend timeout
  153. * to the maximum while setting the timebase
  154. */
  155. set_bit(WDOG_HW_RUNNING, &data->wdt_dev.status);
  156. meson_gxbb_wdt_set_timeout(&data->wdt_dev,
  157. GXBB_WDT_TCNT_SETUP_MASK / 1000);
  158. }
  159. /* Setup with 1ms timebase */
  160. ctrl_reg |= ((clk_get_rate(data->clk) / 1000) &
  161. GXBB_WDT_CTRL_DIV_MASK) |
  162. GXBB_WDT_CTRL_EE_RESET |
  163. GXBB_WDT_CTRL_CLK_EN |
  164. GXBB_WDT_CTRL_CLKDIV_EN;
  165. writel(ctrl_reg, data->reg_base + GXBB_WDT_CTRL_REG);
  166. meson_gxbb_wdt_set_timeout(&data->wdt_dev, data->wdt_dev.timeout);
  167. return devm_watchdog_register_device(dev, &data->wdt_dev);
  168. }
  169. static struct platform_driver meson_gxbb_wdt_driver = {
  170. .probe = meson_gxbb_wdt_probe,
  171. .driver = {
  172. .name = "meson-gxbb-wdt",
  173. .pm = &meson_gxbb_wdt_pm_ops,
  174. .of_match_table = meson_gxbb_wdt_dt_ids,
  175. },
  176. };
  177. module_platform_driver(meson_gxbb_wdt_driver);
  178. MODULE_AUTHOR("Neil Armstrong <[email protected]>");
  179. MODULE_DESCRIPTION("Amlogic Meson GXBB Watchdog timer driver");
  180. MODULE_LICENSE("Dual BSD/GPL");