lmh.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2021, Linaro Limited. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/irqdomain.h>
  8. #include <linux/err.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/of_platform.h>
  11. #include <linux/slab.h>
  12. #include <linux/qcom_scm.h>
  13. #define LMH_NODE_DCVS 0x44435653
  14. #define LMH_CLUSTER0_NODE_ID 0x6370302D
  15. #define LMH_CLUSTER1_NODE_ID 0x6370312D
  16. #define LMH_SUB_FN_THERMAL 0x54484D4C
  17. #define LMH_SUB_FN_CRNT 0x43524E54
  18. #define LMH_SUB_FN_REL 0x52454C00
  19. #define LMH_SUB_FN_BCL 0x42434C00
  20. #define LMH_ALGO_MODE_ENABLE 0x454E424C
  21. #define LMH_TH_HI_THRESHOLD 0x48494748
  22. #define LMH_TH_LOW_THRESHOLD 0x4C4F5700
  23. #define LMH_TH_ARM_THRESHOLD 0x41524D00
  24. #define LMH_REG_DCVS_INTR_CLR 0x8
  25. #define LMH_ENABLE_ALGOS 1
  26. struct lmh_hw_data {
  27. void __iomem *base;
  28. struct irq_domain *domain;
  29. int irq;
  30. };
  31. static irqreturn_t lmh_handle_irq(int hw_irq, void *data)
  32. {
  33. struct lmh_hw_data *lmh_data = data;
  34. int irq = irq_find_mapping(lmh_data->domain, 0);
  35. /* Call the cpufreq driver to handle the interrupt */
  36. if (irq)
  37. generic_handle_irq(irq);
  38. return IRQ_HANDLED;
  39. }
  40. static void lmh_enable_interrupt(struct irq_data *d)
  41. {
  42. struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d);
  43. /* Clear the existing interrupt */
  44. writel(0xff, lmh_data->base + LMH_REG_DCVS_INTR_CLR);
  45. enable_irq(lmh_data->irq);
  46. }
  47. static void lmh_disable_interrupt(struct irq_data *d)
  48. {
  49. struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d);
  50. disable_irq_nosync(lmh_data->irq);
  51. }
  52. static struct irq_chip lmh_irq_chip = {
  53. .name = "lmh",
  54. .irq_enable = lmh_enable_interrupt,
  55. .irq_disable = lmh_disable_interrupt
  56. };
  57. static int lmh_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  58. {
  59. struct lmh_hw_data *lmh_data = d->host_data;
  60. irq_set_chip_and_handler(irq, &lmh_irq_chip, handle_simple_irq);
  61. irq_set_chip_data(irq, lmh_data);
  62. return 0;
  63. }
  64. static const struct irq_domain_ops lmh_irq_ops = {
  65. .map = lmh_irq_map,
  66. .xlate = irq_domain_xlate_onecell,
  67. };
  68. static int lmh_probe(struct platform_device *pdev)
  69. {
  70. struct device *dev = &pdev->dev;
  71. struct device_node *np = dev->of_node;
  72. struct device_node *cpu_node;
  73. struct lmh_hw_data *lmh_data;
  74. int temp_low, temp_high, temp_arm, cpu_id, ret;
  75. unsigned int enable_alg;
  76. u32 node_id;
  77. lmh_data = devm_kzalloc(dev, sizeof(*lmh_data), GFP_KERNEL);
  78. if (!lmh_data)
  79. return -ENOMEM;
  80. lmh_data->base = devm_platform_ioremap_resource(pdev, 0);
  81. if (IS_ERR(lmh_data->base))
  82. return PTR_ERR(lmh_data->base);
  83. cpu_node = of_parse_phandle(np, "cpus", 0);
  84. if (!cpu_node)
  85. return -EINVAL;
  86. cpu_id = of_cpu_node_to_id(cpu_node);
  87. of_node_put(cpu_node);
  88. ret = of_property_read_u32(np, "qcom,lmh-temp-high-millicelsius", &temp_high);
  89. if (ret) {
  90. dev_err(dev, "missing qcom,lmh-temp-high-millicelsius property\n");
  91. return ret;
  92. }
  93. ret = of_property_read_u32(np, "qcom,lmh-temp-low-millicelsius", &temp_low);
  94. if (ret) {
  95. dev_err(dev, "missing qcom,lmh-temp-low-millicelsius property\n");
  96. return ret;
  97. }
  98. ret = of_property_read_u32(np, "qcom,lmh-temp-arm-millicelsius", &temp_arm);
  99. if (ret) {
  100. dev_err(dev, "missing qcom,lmh-temp-arm-millicelsius property\n");
  101. return ret;
  102. }
  103. /*
  104. * Only sdm845 has lmh hardware currently enabled from hlos. If this is needed
  105. * for other platforms, revisit this to check if the <cpu-id, node-id> should be part
  106. * of a dt match table.
  107. */
  108. if (cpu_id == 0) {
  109. node_id = LMH_CLUSTER0_NODE_ID;
  110. } else if (cpu_id == 4) {
  111. node_id = LMH_CLUSTER1_NODE_ID;
  112. } else {
  113. dev_err(dev, "Wrong CPU id associated with LMh node\n");
  114. return -EINVAL;
  115. }
  116. if (!qcom_scm_lmh_dcvsh_available())
  117. return -EINVAL;
  118. enable_alg = (uintptr_t)of_device_get_match_data(dev);
  119. if (enable_alg) {
  120. ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
  121. LMH_NODE_DCVS, node_id, 0);
  122. if (ret)
  123. dev_err(dev, "Error %d enabling current subfunction\n", ret);
  124. ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1,
  125. LMH_NODE_DCVS, node_id, 0);
  126. if (ret)
  127. dev_err(dev, "Error %d enabling reliability subfunction\n", ret);
  128. ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1,
  129. LMH_NODE_DCVS, node_id, 0);
  130. if (ret)
  131. dev_err(dev, "Error %d enabling BCL subfunction\n", ret);
  132. ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1,
  133. LMH_NODE_DCVS, node_id, 0);
  134. if (ret) {
  135. dev_err(dev, "Error %d enabling thermal subfunction\n", ret);
  136. return ret;
  137. }
  138. ret = qcom_scm_lmh_profile_change(0x1);
  139. if (ret) {
  140. dev_err(dev, "Error %d changing profile\n", ret);
  141. return ret;
  142. }
  143. }
  144. /* Set default thermal trips */
  145. ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_ARM_THRESHOLD, temp_arm,
  146. LMH_NODE_DCVS, node_id, 0);
  147. if (ret) {
  148. dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
  149. return ret;
  150. }
  151. ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_HI_THRESHOLD, temp_high,
  152. LMH_NODE_DCVS, node_id, 0);
  153. if (ret) {
  154. dev_err(dev, "Error setting thermal HI threshold%d\n", ret);
  155. return ret;
  156. }
  157. ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_LOW_THRESHOLD, temp_low,
  158. LMH_NODE_DCVS, node_id, 0);
  159. if (ret) {
  160. dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
  161. return ret;
  162. }
  163. lmh_data->irq = platform_get_irq(pdev, 0);
  164. lmh_data->domain = irq_domain_add_linear(np, 1, &lmh_irq_ops, lmh_data);
  165. if (!lmh_data->domain) {
  166. dev_err(dev, "Error adding irq_domain\n");
  167. return -EINVAL;
  168. }
  169. /* Disable the irq and let cpufreq enable it when ready to handle the interrupt */
  170. irq_set_status_flags(lmh_data->irq, IRQ_NOAUTOEN);
  171. ret = devm_request_irq(dev, lmh_data->irq, lmh_handle_irq,
  172. IRQF_ONESHOT | IRQF_NO_SUSPEND,
  173. "lmh-irq", lmh_data);
  174. if (ret) {
  175. dev_err(dev, "Error %d registering irq %x\n", ret, lmh_data->irq);
  176. irq_domain_remove(lmh_data->domain);
  177. return ret;
  178. }
  179. return 0;
  180. }
  181. static const struct of_device_id lmh_table[] = {
  182. { .compatible = "qcom,sc8180x-lmh", },
  183. { .compatible = "qcom,sdm845-lmh", .data = (void *)LMH_ENABLE_ALGOS},
  184. { .compatible = "qcom,sm8150-lmh", },
  185. {}
  186. };
  187. MODULE_DEVICE_TABLE(of, lmh_table);
  188. static struct platform_driver lmh_driver = {
  189. .probe = lmh_probe,
  190. .driver = {
  191. .name = "qcom-lmh",
  192. .of_match_table = lmh_table,
  193. .suppress_bind_attrs = true,
  194. },
  195. };
  196. module_platform_driver(lmh_driver);
  197. MODULE_LICENSE("GPL v2");
  198. MODULE_DESCRIPTION("QCOM LMh driver");