cxgbit_main.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016 Chelsio Communications, Inc.
  4. */
  5. #define DRV_NAME "cxgbit"
  6. #define DRV_VERSION "1.0.0-ko"
  7. #define pr_fmt(fmt) DRV_NAME ": " fmt
  8. #include "cxgbit.h"
  9. #ifdef CONFIG_CHELSIO_T4_DCB
  10. #include <net/dcbevent.h>
  11. #include "cxgb4_dcb.h"
  12. #endif
  13. LIST_HEAD(cdev_list_head);
  14. /* cdev list lock */
  15. DEFINE_MUTEX(cdev_list_lock);
  16. void _cxgbit_free_cdev(struct kref *kref)
  17. {
  18. struct cxgbit_device *cdev;
  19. cdev = container_of(kref, struct cxgbit_device, kref);
  20. cxgbi_ppm_release(cdev2ppm(cdev));
  21. kfree(cdev);
  22. }
  23. static void cxgbit_set_mdsl(struct cxgbit_device *cdev)
  24. {
  25. struct cxgb4_lld_info *lldi = &cdev->lldi;
  26. u32 mdsl;
  27. #define CXGBIT_T5_MAX_PDU_LEN 16224
  28. #define CXGBIT_PDU_NONPAYLOAD_LEN 312 /* 48(BHS) + 256(AHS) + 8(Digest) */
  29. if (is_t5(lldi->adapter_type)) {
  30. mdsl = min_t(u32, lldi->iscsi_iolen - CXGBIT_PDU_NONPAYLOAD_LEN,
  31. CXGBIT_T5_MAX_PDU_LEN - CXGBIT_PDU_NONPAYLOAD_LEN);
  32. } else {
  33. mdsl = lldi->iscsi_iolen - CXGBIT_PDU_NONPAYLOAD_LEN;
  34. mdsl = min(mdsl, 16384U);
  35. }
  36. mdsl = round_down(mdsl, 4);
  37. mdsl = min_t(u32, mdsl, 4 * PAGE_SIZE);
  38. mdsl = min_t(u32, mdsl, (MAX_SKB_FRAGS - 1) * PAGE_SIZE);
  39. cdev->mdsl = mdsl;
  40. }
  41. static void *cxgbit_uld_add(const struct cxgb4_lld_info *lldi)
  42. {
  43. struct cxgbit_device *cdev;
  44. if (is_t4(lldi->adapter_type))
  45. return ERR_PTR(-ENODEV);
  46. cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
  47. if (!cdev)
  48. return ERR_PTR(-ENOMEM);
  49. kref_init(&cdev->kref);
  50. spin_lock_init(&cdev->np_lock);
  51. cdev->lldi = *lldi;
  52. cxgbit_set_mdsl(cdev);
  53. if (cxgbit_ddp_init(cdev) < 0) {
  54. kfree(cdev);
  55. return ERR_PTR(-EINVAL);
  56. }
  57. if (!test_bit(CDEV_DDP_ENABLE, &cdev->flags))
  58. pr_info("cdev %s ddp init failed\n",
  59. pci_name(lldi->pdev));
  60. if (lldi->fw_vers >= 0x10d2b00)
  61. set_bit(CDEV_ISO_ENABLE, &cdev->flags);
  62. spin_lock_init(&cdev->cskq.lock);
  63. INIT_LIST_HEAD(&cdev->cskq.list);
  64. mutex_lock(&cdev_list_lock);
  65. list_add_tail(&cdev->list, &cdev_list_head);
  66. mutex_unlock(&cdev_list_lock);
  67. pr_info("cdev %s added for iSCSI target transport\n",
  68. pci_name(lldi->pdev));
  69. return cdev;
  70. }
  71. static void cxgbit_close_conn(struct cxgbit_device *cdev)
  72. {
  73. struct cxgbit_sock *csk;
  74. struct sk_buff *skb;
  75. bool wakeup_thread = false;
  76. spin_lock_bh(&cdev->cskq.lock);
  77. list_for_each_entry(csk, &cdev->cskq.list, list) {
  78. skb = alloc_skb(0, GFP_ATOMIC);
  79. if (!skb)
  80. continue;
  81. spin_lock_bh(&csk->rxq.lock);
  82. __skb_queue_tail(&csk->rxq, skb);
  83. if (skb_queue_len(&csk->rxq) == 1)
  84. wakeup_thread = true;
  85. spin_unlock_bh(&csk->rxq.lock);
  86. if (wakeup_thread) {
  87. wake_up(&csk->waitq);
  88. wakeup_thread = false;
  89. }
  90. }
  91. spin_unlock_bh(&cdev->cskq.lock);
  92. }
  93. static void cxgbit_detach_cdev(struct cxgbit_device *cdev)
  94. {
  95. bool free_cdev = false;
  96. spin_lock_bh(&cdev->cskq.lock);
  97. if (list_empty(&cdev->cskq.list))
  98. free_cdev = true;
  99. spin_unlock_bh(&cdev->cskq.lock);
  100. if (free_cdev) {
  101. mutex_lock(&cdev_list_lock);
  102. list_del(&cdev->list);
  103. mutex_unlock(&cdev_list_lock);
  104. cxgbit_put_cdev(cdev);
  105. } else {
  106. cxgbit_close_conn(cdev);
  107. }
  108. }
  109. static int cxgbit_uld_state_change(void *handle, enum cxgb4_state state)
  110. {
  111. struct cxgbit_device *cdev = handle;
  112. switch (state) {
  113. case CXGB4_STATE_UP:
  114. set_bit(CDEV_STATE_UP, &cdev->flags);
  115. pr_info("cdev %s state UP.\n", pci_name(cdev->lldi.pdev));
  116. break;
  117. case CXGB4_STATE_START_RECOVERY:
  118. clear_bit(CDEV_STATE_UP, &cdev->flags);
  119. cxgbit_close_conn(cdev);
  120. pr_info("cdev %s state RECOVERY.\n", pci_name(cdev->lldi.pdev));
  121. break;
  122. case CXGB4_STATE_DOWN:
  123. pr_info("cdev %s state DOWN.\n", pci_name(cdev->lldi.pdev));
  124. break;
  125. case CXGB4_STATE_DETACH:
  126. clear_bit(CDEV_STATE_UP, &cdev->flags);
  127. pr_info("cdev %s state DETACH.\n", pci_name(cdev->lldi.pdev));
  128. cxgbit_detach_cdev(cdev);
  129. break;
  130. default:
  131. pr_info("cdev %s unknown state %d.\n",
  132. pci_name(cdev->lldi.pdev), state);
  133. break;
  134. }
  135. return 0;
  136. }
  137. static void
  138. cxgbit_process_ddpvld(struct cxgbit_sock *csk, struct cxgbit_lro_pdu_cb *pdu_cb,
  139. u32 ddpvld)
  140. {
  141. if (ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_HCRC_SHIFT)) {
  142. pr_info("tid 0x%x, status 0x%x, hcrc bad.\n", csk->tid, ddpvld);
  143. pdu_cb->flags |= PDUCBF_RX_HCRC_ERR;
  144. }
  145. if (ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_DCRC_SHIFT)) {
  146. pr_info("tid 0x%x, status 0x%x, dcrc bad.\n", csk->tid, ddpvld);
  147. pdu_cb->flags |= PDUCBF_RX_DCRC_ERR;
  148. }
  149. if (ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_PAD_SHIFT))
  150. pr_info("tid 0x%x, status 0x%x, pad bad.\n", csk->tid, ddpvld);
  151. if ((ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_DDP_SHIFT)) &&
  152. (!(pdu_cb->flags & PDUCBF_RX_DATA))) {
  153. pdu_cb->flags |= PDUCBF_RX_DATA_DDPD;
  154. }
  155. }
  156. static void
  157. cxgbit_lro_add_packet_rsp(struct sk_buff *skb, u8 op, const __be64 *rsp)
  158. {
  159. struct cxgbit_lro_cb *lro_cb = cxgbit_skb_lro_cb(skb);
  160. struct cxgbit_lro_pdu_cb *pdu_cb = cxgbit_skb_lro_pdu_cb(skb,
  161. lro_cb->pdu_idx);
  162. struct cpl_rx_iscsi_ddp *cpl = (struct cpl_rx_iscsi_ddp *)(rsp + 1);
  163. cxgbit_process_ddpvld(lro_cb->csk, pdu_cb, be32_to_cpu(cpl->ddpvld));
  164. pdu_cb->flags |= PDUCBF_RX_STATUS;
  165. pdu_cb->ddigest = ntohl(cpl->ulp_crc);
  166. pdu_cb->pdulen = ntohs(cpl->len);
  167. if (pdu_cb->flags & PDUCBF_RX_HDR)
  168. pdu_cb->complete = true;
  169. lro_cb->pdu_totallen += pdu_cb->pdulen;
  170. lro_cb->complete = true;
  171. lro_cb->pdu_idx++;
  172. }
  173. static void
  174. cxgbit_copy_frags(struct sk_buff *skb, const struct pkt_gl *gl,
  175. unsigned int offset)
  176. {
  177. u8 skb_frag_idx = skb_shinfo(skb)->nr_frags;
  178. u8 i;
  179. /* usually there's just one frag */
  180. __skb_fill_page_desc(skb, skb_frag_idx, gl->frags[0].page,
  181. gl->frags[0].offset + offset,
  182. gl->frags[0].size - offset);
  183. for (i = 1; i < gl->nfrags; i++)
  184. __skb_fill_page_desc(skb, skb_frag_idx + i,
  185. gl->frags[i].page,
  186. gl->frags[i].offset,
  187. gl->frags[i].size);
  188. skb_shinfo(skb)->nr_frags += gl->nfrags;
  189. /* get a reference to the last page, we don't own it */
  190. get_page(gl->frags[gl->nfrags - 1].page);
  191. }
  192. static void
  193. cxgbit_lro_add_packet_gl(struct sk_buff *skb, u8 op, const struct pkt_gl *gl)
  194. {
  195. struct cxgbit_lro_cb *lro_cb = cxgbit_skb_lro_cb(skb);
  196. struct cxgbit_lro_pdu_cb *pdu_cb = cxgbit_skb_lro_pdu_cb(skb,
  197. lro_cb->pdu_idx);
  198. u32 len, offset;
  199. if (op == CPL_ISCSI_HDR) {
  200. struct cpl_iscsi_hdr *cpl = (struct cpl_iscsi_hdr *)gl->va;
  201. offset = sizeof(struct cpl_iscsi_hdr);
  202. pdu_cb->flags |= PDUCBF_RX_HDR;
  203. pdu_cb->seq = ntohl(cpl->seq);
  204. len = ntohs(cpl->len);
  205. pdu_cb->hdr = gl->va + offset;
  206. pdu_cb->hlen = len;
  207. pdu_cb->hfrag_idx = skb_shinfo(skb)->nr_frags;
  208. if (unlikely(gl->nfrags > 1))
  209. cxgbit_skcb_flags(skb) = 0;
  210. lro_cb->complete = false;
  211. } else if (op == CPL_ISCSI_DATA) {
  212. struct cpl_iscsi_data *cpl = (struct cpl_iscsi_data *)gl->va;
  213. offset = sizeof(struct cpl_iscsi_data);
  214. pdu_cb->flags |= PDUCBF_RX_DATA;
  215. len = ntohs(cpl->len);
  216. pdu_cb->dlen = len;
  217. pdu_cb->doffset = lro_cb->offset;
  218. pdu_cb->nr_dfrags = gl->nfrags;
  219. pdu_cb->dfrag_idx = skb_shinfo(skb)->nr_frags;
  220. lro_cb->complete = false;
  221. } else {
  222. struct cpl_rx_iscsi_cmp *cpl;
  223. cpl = (struct cpl_rx_iscsi_cmp *)gl->va;
  224. offset = sizeof(struct cpl_rx_iscsi_cmp);
  225. pdu_cb->flags |= (PDUCBF_RX_HDR | PDUCBF_RX_STATUS);
  226. len = be16_to_cpu(cpl->len);
  227. pdu_cb->hdr = gl->va + offset;
  228. pdu_cb->hlen = len;
  229. pdu_cb->hfrag_idx = skb_shinfo(skb)->nr_frags;
  230. pdu_cb->ddigest = be32_to_cpu(cpl->ulp_crc);
  231. pdu_cb->pdulen = ntohs(cpl->len);
  232. if (unlikely(gl->nfrags > 1))
  233. cxgbit_skcb_flags(skb) = 0;
  234. cxgbit_process_ddpvld(lro_cb->csk, pdu_cb,
  235. be32_to_cpu(cpl->ddpvld));
  236. if (pdu_cb->flags & PDUCBF_RX_DATA_DDPD) {
  237. pdu_cb->flags |= PDUCBF_RX_DDP_CMP;
  238. pdu_cb->complete = true;
  239. } else if (pdu_cb->flags & PDUCBF_RX_DATA) {
  240. pdu_cb->complete = true;
  241. }
  242. lro_cb->pdu_totallen += pdu_cb->hlen + pdu_cb->dlen;
  243. lro_cb->complete = true;
  244. lro_cb->pdu_idx++;
  245. }
  246. cxgbit_copy_frags(skb, gl, offset);
  247. pdu_cb->frags += gl->nfrags;
  248. lro_cb->offset += len;
  249. skb->len += len;
  250. skb->data_len += len;
  251. skb->truesize += len;
  252. }
  253. static struct sk_buff *
  254. cxgbit_lro_init_skb(struct cxgbit_sock *csk, u8 op, const struct pkt_gl *gl,
  255. const __be64 *rsp, struct napi_struct *napi)
  256. {
  257. struct sk_buff *skb;
  258. struct cxgbit_lro_cb *lro_cb;
  259. skb = napi_alloc_skb(napi, LRO_SKB_MAX_HEADROOM);
  260. if (unlikely(!skb))
  261. return NULL;
  262. memset(skb->data, 0, LRO_SKB_MAX_HEADROOM);
  263. cxgbit_skcb_flags(skb) |= SKCBF_RX_LRO;
  264. lro_cb = cxgbit_skb_lro_cb(skb);
  265. cxgbit_get_csk(csk);
  266. lro_cb->csk = csk;
  267. return skb;
  268. }
  269. static void cxgbit_queue_lro_skb(struct cxgbit_sock *csk, struct sk_buff *skb)
  270. {
  271. bool wakeup_thread = false;
  272. spin_lock(&csk->rxq.lock);
  273. __skb_queue_tail(&csk->rxq, skb);
  274. if (skb_queue_len(&csk->rxq) == 1)
  275. wakeup_thread = true;
  276. spin_unlock(&csk->rxq.lock);
  277. if (wakeup_thread)
  278. wake_up(&csk->waitq);
  279. }
  280. static void cxgbit_lro_flush(struct t4_lro_mgr *lro_mgr, struct sk_buff *skb)
  281. {
  282. struct cxgbit_lro_cb *lro_cb = cxgbit_skb_lro_cb(skb);
  283. struct cxgbit_sock *csk = lro_cb->csk;
  284. csk->lro_skb = NULL;
  285. __skb_unlink(skb, &lro_mgr->lroq);
  286. cxgbit_queue_lro_skb(csk, skb);
  287. cxgbit_put_csk(csk);
  288. lro_mgr->lro_pkts++;
  289. lro_mgr->lro_session_cnt--;
  290. }
  291. static void cxgbit_uld_lro_flush(struct t4_lro_mgr *lro_mgr)
  292. {
  293. struct sk_buff *skb;
  294. while ((skb = skb_peek(&lro_mgr->lroq)))
  295. cxgbit_lro_flush(lro_mgr, skb);
  296. }
  297. static int
  298. cxgbit_lro_receive(struct cxgbit_sock *csk, u8 op, const __be64 *rsp,
  299. const struct pkt_gl *gl, struct t4_lro_mgr *lro_mgr,
  300. struct napi_struct *napi)
  301. {
  302. struct sk_buff *skb;
  303. struct cxgbit_lro_cb *lro_cb;
  304. if (!csk) {
  305. pr_err("%s: csk NULL, op 0x%x.\n", __func__, op);
  306. goto out;
  307. }
  308. if (csk->lro_skb)
  309. goto add_packet;
  310. start_lro:
  311. if (lro_mgr->lro_session_cnt >= MAX_LRO_SESSIONS) {
  312. cxgbit_uld_lro_flush(lro_mgr);
  313. goto start_lro;
  314. }
  315. skb = cxgbit_lro_init_skb(csk, op, gl, rsp, napi);
  316. if (unlikely(!skb))
  317. goto out;
  318. csk->lro_skb = skb;
  319. __skb_queue_tail(&lro_mgr->lroq, skb);
  320. lro_mgr->lro_session_cnt++;
  321. add_packet:
  322. skb = csk->lro_skb;
  323. lro_cb = cxgbit_skb_lro_cb(skb);
  324. if ((gl && (((skb_shinfo(skb)->nr_frags + gl->nfrags) >
  325. MAX_SKB_FRAGS) || (lro_cb->pdu_totallen >= LRO_FLUSH_LEN_MAX))) ||
  326. (lro_cb->pdu_idx >= MAX_SKB_FRAGS)) {
  327. cxgbit_lro_flush(lro_mgr, skb);
  328. goto start_lro;
  329. }
  330. if (gl)
  331. cxgbit_lro_add_packet_gl(skb, op, gl);
  332. else
  333. cxgbit_lro_add_packet_rsp(skb, op, rsp);
  334. lro_mgr->lro_merged++;
  335. return 0;
  336. out:
  337. return -1;
  338. }
  339. static int
  340. cxgbit_uld_lro_rx_handler(void *hndl, const __be64 *rsp,
  341. const struct pkt_gl *gl, struct t4_lro_mgr *lro_mgr,
  342. struct napi_struct *napi)
  343. {
  344. struct cxgbit_device *cdev = hndl;
  345. struct cxgb4_lld_info *lldi = &cdev->lldi;
  346. struct cpl_tx_data *rpl = NULL;
  347. struct cxgbit_sock *csk = NULL;
  348. unsigned int tid = 0;
  349. struct sk_buff *skb;
  350. unsigned int op = *(u8 *)rsp;
  351. bool lro_flush = true;
  352. switch (op) {
  353. case CPL_ISCSI_HDR:
  354. case CPL_ISCSI_DATA:
  355. case CPL_RX_ISCSI_CMP:
  356. case CPL_RX_ISCSI_DDP:
  357. case CPL_FW4_ACK:
  358. lro_flush = false;
  359. fallthrough;
  360. case CPL_ABORT_RPL_RSS:
  361. case CPL_PASS_ESTABLISH:
  362. case CPL_PEER_CLOSE:
  363. case CPL_CLOSE_CON_RPL:
  364. case CPL_ABORT_REQ_RSS:
  365. case CPL_SET_TCB_RPL:
  366. case CPL_RX_DATA:
  367. rpl = gl ? (struct cpl_tx_data *)gl->va :
  368. (struct cpl_tx_data *)(rsp + 1);
  369. tid = GET_TID(rpl);
  370. csk = lookup_tid(lldi->tids, tid);
  371. break;
  372. default:
  373. break;
  374. }
  375. if (csk && csk->lro_skb && lro_flush)
  376. cxgbit_lro_flush(lro_mgr, csk->lro_skb);
  377. if (!gl) {
  378. unsigned int len;
  379. if (op == CPL_RX_ISCSI_DDP) {
  380. if (!cxgbit_lro_receive(csk, op, rsp, NULL, lro_mgr,
  381. napi))
  382. return 0;
  383. }
  384. len = 64 - sizeof(struct rsp_ctrl) - 8;
  385. skb = napi_alloc_skb(napi, len);
  386. if (!skb)
  387. goto nomem;
  388. __skb_put(skb, len);
  389. skb_copy_to_linear_data(skb, &rsp[1], len);
  390. } else {
  391. if (unlikely(op != *(u8 *)gl->va)) {
  392. pr_info("? FL 0x%p,RSS%#llx,FL %#llx,len %u.\n",
  393. gl->va, be64_to_cpu(*rsp),
  394. get_unaligned_be64(gl->va),
  395. gl->tot_len);
  396. return 0;
  397. }
  398. if ((op == CPL_ISCSI_HDR) || (op == CPL_ISCSI_DATA) ||
  399. (op == CPL_RX_ISCSI_CMP)) {
  400. if (!cxgbit_lro_receive(csk, op, rsp, gl, lro_mgr,
  401. napi))
  402. return 0;
  403. }
  404. #define RX_PULL_LEN 128
  405. skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN);
  406. if (unlikely(!skb))
  407. goto nomem;
  408. }
  409. rpl = (struct cpl_tx_data *)skb->data;
  410. op = rpl->ot.opcode;
  411. cxgbit_skcb_rx_opcode(skb) = op;
  412. pr_debug("cdev %p, opcode 0x%x(0x%x,0x%x), skb %p.\n",
  413. cdev, op, rpl->ot.opcode_tid,
  414. ntohl(rpl->ot.opcode_tid), skb);
  415. if (op < NUM_CPL_CMDS && cxgbit_cplhandlers[op]) {
  416. cxgbit_cplhandlers[op](cdev, skb);
  417. } else {
  418. pr_err("No handler for opcode 0x%x.\n", op);
  419. __kfree_skb(skb);
  420. }
  421. return 0;
  422. nomem:
  423. pr_err("%s OOM bailing out.\n", __func__);
  424. return 1;
  425. }
  426. #ifdef CONFIG_CHELSIO_T4_DCB
  427. struct cxgbit_dcb_work {
  428. struct dcb_app_type dcb_app;
  429. struct work_struct work;
  430. };
  431. static void
  432. cxgbit_update_dcb_priority(struct cxgbit_device *cdev, u8 port_id,
  433. u8 dcb_priority, u16 port_num)
  434. {
  435. struct cxgbit_sock *csk;
  436. struct sk_buff *skb;
  437. u16 local_port;
  438. bool wakeup_thread = false;
  439. spin_lock_bh(&cdev->cskq.lock);
  440. list_for_each_entry(csk, &cdev->cskq.list, list) {
  441. if (csk->port_id != port_id)
  442. continue;
  443. if (csk->com.local_addr.ss_family == AF_INET6) {
  444. struct sockaddr_in6 *sock_in6;
  445. sock_in6 = (struct sockaddr_in6 *)&csk->com.local_addr;
  446. local_port = ntohs(sock_in6->sin6_port);
  447. } else {
  448. struct sockaddr_in *sock_in;
  449. sock_in = (struct sockaddr_in *)&csk->com.local_addr;
  450. local_port = ntohs(sock_in->sin_port);
  451. }
  452. if (local_port != port_num)
  453. continue;
  454. if (csk->dcb_priority == dcb_priority)
  455. continue;
  456. skb = alloc_skb(0, GFP_ATOMIC);
  457. if (!skb)
  458. continue;
  459. spin_lock(&csk->rxq.lock);
  460. __skb_queue_tail(&csk->rxq, skb);
  461. if (skb_queue_len(&csk->rxq) == 1)
  462. wakeup_thread = true;
  463. spin_unlock(&csk->rxq.lock);
  464. if (wakeup_thread) {
  465. wake_up(&csk->waitq);
  466. wakeup_thread = false;
  467. }
  468. }
  469. spin_unlock_bh(&cdev->cskq.lock);
  470. }
  471. static void cxgbit_dcb_workfn(struct work_struct *work)
  472. {
  473. struct cxgbit_dcb_work *dcb_work;
  474. struct net_device *ndev;
  475. struct cxgbit_device *cdev = NULL;
  476. struct dcb_app_type *iscsi_app;
  477. u8 priority, port_id = 0xff;
  478. dcb_work = container_of(work, struct cxgbit_dcb_work, work);
  479. iscsi_app = &dcb_work->dcb_app;
  480. if (iscsi_app->dcbx & DCB_CAP_DCBX_VER_IEEE) {
  481. if ((iscsi_app->app.selector != IEEE_8021QAZ_APP_SEL_STREAM) &&
  482. (iscsi_app->app.selector != IEEE_8021QAZ_APP_SEL_ANY))
  483. goto out;
  484. priority = iscsi_app->app.priority;
  485. } else if (iscsi_app->dcbx & DCB_CAP_DCBX_VER_CEE) {
  486. if (iscsi_app->app.selector != DCB_APP_IDTYPE_PORTNUM)
  487. goto out;
  488. if (!iscsi_app->app.priority)
  489. goto out;
  490. priority = ffs(iscsi_app->app.priority) - 1;
  491. } else {
  492. goto out;
  493. }
  494. pr_debug("priority for ifid %d is %u\n",
  495. iscsi_app->ifindex, priority);
  496. ndev = dev_get_by_index(&init_net, iscsi_app->ifindex);
  497. if (!ndev)
  498. goto out;
  499. mutex_lock(&cdev_list_lock);
  500. cdev = cxgbit_find_device(ndev, &port_id);
  501. dev_put(ndev);
  502. if (!cdev) {
  503. mutex_unlock(&cdev_list_lock);
  504. goto out;
  505. }
  506. cxgbit_update_dcb_priority(cdev, port_id, priority,
  507. iscsi_app->app.protocol);
  508. mutex_unlock(&cdev_list_lock);
  509. out:
  510. kfree(dcb_work);
  511. }
  512. static int
  513. cxgbit_dcbevent_notify(struct notifier_block *nb, unsigned long action,
  514. void *data)
  515. {
  516. struct cxgbit_dcb_work *dcb_work;
  517. struct dcb_app_type *dcb_app = data;
  518. dcb_work = kzalloc(sizeof(*dcb_work), GFP_ATOMIC);
  519. if (!dcb_work)
  520. return NOTIFY_DONE;
  521. dcb_work->dcb_app = *dcb_app;
  522. INIT_WORK(&dcb_work->work, cxgbit_dcb_workfn);
  523. schedule_work(&dcb_work->work);
  524. return NOTIFY_OK;
  525. }
  526. #endif
  527. static enum target_prot_op cxgbit_get_sup_prot_ops(struct iscsit_conn *conn)
  528. {
  529. return TARGET_PROT_NORMAL;
  530. }
  531. static struct iscsit_transport cxgbit_transport = {
  532. .name = DRV_NAME,
  533. .transport_type = ISCSI_CXGBIT,
  534. .rdma_shutdown = false,
  535. .priv_size = sizeof(struct cxgbit_cmd),
  536. .owner = THIS_MODULE,
  537. .iscsit_setup_np = cxgbit_setup_np,
  538. .iscsit_accept_np = cxgbit_accept_np,
  539. .iscsit_free_np = cxgbit_free_np,
  540. .iscsit_free_conn = cxgbit_free_conn,
  541. .iscsit_get_login_rx = cxgbit_get_login_rx,
  542. .iscsit_put_login_tx = cxgbit_put_login_tx,
  543. .iscsit_immediate_queue = iscsit_immediate_queue,
  544. .iscsit_response_queue = iscsit_response_queue,
  545. .iscsit_get_dataout = iscsit_build_r2ts_for_cmd,
  546. .iscsit_queue_data_in = iscsit_queue_rsp,
  547. .iscsit_queue_status = iscsit_queue_rsp,
  548. .iscsit_xmit_pdu = cxgbit_xmit_pdu,
  549. .iscsit_get_r2t_ttt = cxgbit_get_r2t_ttt,
  550. .iscsit_get_rx_pdu = cxgbit_get_rx_pdu,
  551. .iscsit_validate_params = cxgbit_validate_params,
  552. .iscsit_unmap_cmd = cxgbit_unmap_cmd,
  553. .iscsit_aborted_task = iscsit_aborted_task,
  554. .iscsit_get_sup_prot_ops = cxgbit_get_sup_prot_ops,
  555. };
  556. static struct cxgb4_uld_info cxgbit_uld_info = {
  557. .name = DRV_NAME,
  558. .nrxq = MAX_ULD_QSETS,
  559. .ntxq = MAX_ULD_QSETS,
  560. .rxq_size = 1024,
  561. .lro = true,
  562. .add = cxgbit_uld_add,
  563. .state_change = cxgbit_uld_state_change,
  564. .lro_rx_handler = cxgbit_uld_lro_rx_handler,
  565. .lro_flush = cxgbit_uld_lro_flush,
  566. };
  567. #ifdef CONFIG_CHELSIO_T4_DCB
  568. static struct notifier_block cxgbit_dcbevent_nb = {
  569. .notifier_call = cxgbit_dcbevent_notify,
  570. };
  571. #endif
  572. static int __init cxgbit_init(void)
  573. {
  574. cxgb4_register_uld(CXGB4_ULD_ISCSIT, &cxgbit_uld_info);
  575. iscsit_register_transport(&cxgbit_transport);
  576. #ifdef CONFIG_CHELSIO_T4_DCB
  577. pr_info("%s dcb enabled.\n", DRV_NAME);
  578. register_dcbevent_notifier(&cxgbit_dcbevent_nb);
  579. #endif
  580. BUILD_BUG_ON(sizeof_field(struct sk_buff, cb) <
  581. sizeof(union cxgbit_skb_cb));
  582. return 0;
  583. }
  584. static void __exit cxgbit_exit(void)
  585. {
  586. struct cxgbit_device *cdev, *tmp;
  587. #ifdef CONFIG_CHELSIO_T4_DCB
  588. unregister_dcbevent_notifier(&cxgbit_dcbevent_nb);
  589. #endif
  590. mutex_lock(&cdev_list_lock);
  591. list_for_each_entry_safe(cdev, tmp, &cdev_list_head, list) {
  592. list_del(&cdev->list);
  593. cxgbit_put_cdev(cdev);
  594. }
  595. mutex_unlock(&cdev_list_lock);
  596. iscsit_unregister_transport(&cxgbit_transport);
  597. cxgb4_unregister_uld(CXGB4_ULD_ISCSIT);
  598. }
  599. module_init(cxgbit_init);
  600. module_exit(cxgbit_exit);
  601. MODULE_DESCRIPTION("Chelsio iSCSI target offload driver");
  602. MODULE_AUTHOR("Chelsio Communications");
  603. MODULE_VERSION(DRV_VERSION);
  604. MODULE_LICENSE("GPL");