cxgbit_ddp.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016 Chelsio Communications, Inc.
  4. */
  5. #include "cxgbit.h"
  6. static void
  7. cxgbit_set_one_ppod(struct cxgbi_pagepod *ppod,
  8. struct cxgbi_task_tag_info *ttinfo,
  9. struct scatterlist **sg_pp, unsigned int *sg_off)
  10. {
  11. struct scatterlist *sg = sg_pp ? *sg_pp : NULL;
  12. unsigned int offset = sg_off ? *sg_off : 0;
  13. dma_addr_t addr = 0UL;
  14. unsigned int len = 0;
  15. int i;
  16. memcpy(ppod, &ttinfo->hdr, sizeof(struct cxgbi_pagepod_hdr));
  17. if (sg) {
  18. addr = sg_dma_address(sg);
  19. len = sg_dma_len(sg);
  20. }
  21. for (i = 0; i < PPOD_PAGES_MAX; i++) {
  22. if (sg) {
  23. ppod->addr[i] = cpu_to_be64(addr + offset);
  24. offset += PAGE_SIZE;
  25. if (offset == (len + sg->offset)) {
  26. offset = 0;
  27. sg = sg_next(sg);
  28. if (sg) {
  29. addr = sg_dma_address(sg);
  30. len = sg_dma_len(sg);
  31. }
  32. }
  33. } else {
  34. ppod->addr[i] = 0ULL;
  35. }
  36. }
  37. /*
  38. * the fifth address needs to be repeated in the next ppod, so do
  39. * not move sg
  40. */
  41. if (sg_pp) {
  42. *sg_pp = sg;
  43. *sg_off = offset;
  44. }
  45. if (offset == len) {
  46. offset = 0;
  47. if (sg) {
  48. sg = sg_next(sg);
  49. if (sg)
  50. addr = sg_dma_address(sg);
  51. }
  52. }
  53. ppod->addr[i] = sg ? cpu_to_be64(addr + offset) : 0ULL;
  54. }
  55. static struct sk_buff *
  56. cxgbit_ppod_init_idata(struct cxgbit_device *cdev, struct cxgbi_ppm *ppm,
  57. unsigned int idx, unsigned int npods, unsigned int tid)
  58. {
  59. struct ulp_mem_io *req;
  60. struct ulptx_idata *idata;
  61. unsigned int pm_addr = (idx << PPOD_SIZE_SHIFT) + ppm->llimit;
  62. unsigned int dlen = npods << PPOD_SIZE_SHIFT;
  63. unsigned int wr_len = roundup(sizeof(struct ulp_mem_io) +
  64. sizeof(struct ulptx_idata) + dlen, 16);
  65. struct sk_buff *skb;
  66. skb = alloc_skb(wr_len, GFP_KERNEL);
  67. if (!skb)
  68. return NULL;
  69. req = __skb_put(skb, wr_len);
  70. INIT_ULPTX_WR(req, wr_len, 0, tid);
  71. req->wr.wr_hi = htonl(FW_WR_OP_V(FW_ULPTX_WR) |
  72. FW_WR_ATOMIC_V(0));
  73. req->cmd = htonl(ULPTX_CMD_V(ULP_TX_MEM_WRITE) |
  74. ULP_MEMIO_ORDER_V(0) |
  75. T5_ULP_MEMIO_IMM_V(1));
  76. req->dlen = htonl(ULP_MEMIO_DATA_LEN_V(dlen >> 5));
  77. req->lock_addr = htonl(ULP_MEMIO_ADDR_V(pm_addr >> 5));
  78. req->len16 = htonl(DIV_ROUND_UP(wr_len - sizeof(req->wr), 16));
  79. idata = (struct ulptx_idata *)(req + 1);
  80. idata->cmd_more = htonl(ULPTX_CMD_V(ULP_TX_SC_IMM));
  81. idata->len = htonl(dlen);
  82. return skb;
  83. }
  84. static int
  85. cxgbit_ppod_write_idata(struct cxgbi_ppm *ppm, struct cxgbit_sock *csk,
  86. struct cxgbi_task_tag_info *ttinfo, unsigned int idx,
  87. unsigned int npods, struct scatterlist **sg_pp,
  88. unsigned int *sg_off)
  89. {
  90. struct cxgbit_device *cdev = csk->com.cdev;
  91. struct sk_buff *skb;
  92. struct ulp_mem_io *req;
  93. struct ulptx_idata *idata;
  94. struct cxgbi_pagepod *ppod;
  95. unsigned int i;
  96. skb = cxgbit_ppod_init_idata(cdev, ppm, idx, npods, csk->tid);
  97. if (!skb)
  98. return -ENOMEM;
  99. req = (struct ulp_mem_io *)skb->data;
  100. idata = (struct ulptx_idata *)(req + 1);
  101. ppod = (struct cxgbi_pagepod *)(idata + 1);
  102. for (i = 0; i < npods; i++, ppod++)
  103. cxgbit_set_one_ppod(ppod, ttinfo, sg_pp, sg_off);
  104. __skb_queue_tail(&csk->ppodq, skb);
  105. return 0;
  106. }
  107. static int
  108. cxgbit_ddp_set_map(struct cxgbi_ppm *ppm, struct cxgbit_sock *csk,
  109. struct cxgbi_task_tag_info *ttinfo)
  110. {
  111. unsigned int pidx = ttinfo->idx;
  112. unsigned int npods = ttinfo->npods;
  113. unsigned int i, cnt;
  114. struct scatterlist *sg = ttinfo->sgl;
  115. unsigned int offset = 0;
  116. int ret = 0;
  117. for (i = 0; i < npods; i += cnt, pidx += cnt) {
  118. cnt = npods - i;
  119. if (cnt > ULPMEM_IDATA_MAX_NPPODS)
  120. cnt = ULPMEM_IDATA_MAX_NPPODS;
  121. ret = cxgbit_ppod_write_idata(ppm, csk, ttinfo, pidx, cnt,
  122. &sg, &offset);
  123. if (ret < 0)
  124. break;
  125. }
  126. return ret;
  127. }
  128. static int cxgbit_ddp_sgl_check(struct scatterlist *sg,
  129. unsigned int nents)
  130. {
  131. unsigned int last_sgidx = nents - 1;
  132. unsigned int i;
  133. for (i = 0; i < nents; i++, sg = sg_next(sg)) {
  134. unsigned int len = sg->length + sg->offset;
  135. if ((sg->offset & 0x3) || (i && sg->offset) ||
  136. ((i != last_sgidx) && (len != PAGE_SIZE))) {
  137. return -EINVAL;
  138. }
  139. }
  140. return 0;
  141. }
  142. static int
  143. cxgbit_ddp_reserve(struct cxgbit_sock *csk, struct cxgbi_task_tag_info *ttinfo,
  144. unsigned int xferlen)
  145. {
  146. struct cxgbit_device *cdev = csk->com.cdev;
  147. struct cxgbi_ppm *ppm = cdev2ppm(cdev);
  148. struct scatterlist *sgl = ttinfo->sgl;
  149. unsigned int sgcnt = ttinfo->nents;
  150. unsigned int sg_offset = sgl->offset;
  151. int ret;
  152. if ((xferlen < DDP_THRESHOLD) || (!sgcnt)) {
  153. pr_debug("ppm 0x%p, pgidx %u, xfer %u, sgcnt %u, NO ddp.\n",
  154. ppm, ppm->tformat.pgsz_idx_dflt,
  155. xferlen, ttinfo->nents);
  156. return -EINVAL;
  157. }
  158. if (cxgbit_ddp_sgl_check(sgl, sgcnt) < 0)
  159. return -EINVAL;
  160. ttinfo->nr_pages = (xferlen + sgl->offset +
  161. (1 << PAGE_SHIFT) - 1) >> PAGE_SHIFT;
  162. /*
  163. * the ddp tag will be used for the ttt in the outgoing r2t pdu
  164. */
  165. ret = cxgbi_ppm_ppods_reserve(ppm, ttinfo->nr_pages, 0, &ttinfo->idx,
  166. &ttinfo->tag, 0);
  167. if (ret < 0)
  168. return ret;
  169. ttinfo->npods = ret;
  170. sgl->offset = 0;
  171. ret = dma_map_sg(&ppm->pdev->dev, sgl, sgcnt, DMA_FROM_DEVICE);
  172. sgl->offset = sg_offset;
  173. if (!ret) {
  174. pr_debug("%s: 0x%x, xfer %u, sgl %u dma mapping err.\n",
  175. __func__, 0, xferlen, sgcnt);
  176. goto rel_ppods;
  177. }
  178. cxgbi_ppm_make_ppod_hdr(ppm, ttinfo->tag, csk->tid, sgl->offset,
  179. xferlen, &ttinfo->hdr);
  180. ret = cxgbit_ddp_set_map(ppm, csk, ttinfo);
  181. if (ret < 0) {
  182. __skb_queue_purge(&csk->ppodq);
  183. dma_unmap_sg(&ppm->pdev->dev, sgl, sgcnt, DMA_FROM_DEVICE);
  184. goto rel_ppods;
  185. }
  186. return 0;
  187. rel_ppods:
  188. cxgbi_ppm_ppod_release(ppm, ttinfo->idx);
  189. return -EINVAL;
  190. }
  191. void
  192. cxgbit_get_r2t_ttt(struct iscsit_conn *conn, struct iscsit_cmd *cmd,
  193. struct iscsi_r2t *r2t)
  194. {
  195. struct cxgbit_sock *csk = conn->context;
  196. struct cxgbit_device *cdev = csk->com.cdev;
  197. struct cxgbit_cmd *ccmd = iscsit_priv_cmd(cmd);
  198. struct cxgbi_task_tag_info *ttinfo = &ccmd->ttinfo;
  199. int ret;
  200. if ((!ccmd->setup_ddp) ||
  201. (!test_bit(CSK_DDP_ENABLE, &csk->com.flags)))
  202. goto out;
  203. ccmd->setup_ddp = false;
  204. ttinfo->sgl = cmd->se_cmd.t_data_sg;
  205. ttinfo->nents = cmd->se_cmd.t_data_nents;
  206. ret = cxgbit_ddp_reserve(csk, ttinfo, cmd->se_cmd.data_length);
  207. if (ret < 0) {
  208. pr_debug("csk 0x%p, cmd 0x%p, xfer len %u, sgcnt %u no ddp.\n",
  209. csk, cmd, cmd->se_cmd.data_length, ttinfo->nents);
  210. ttinfo->sgl = NULL;
  211. ttinfo->nents = 0;
  212. } else {
  213. ccmd->release = true;
  214. }
  215. out:
  216. pr_debug("cdev 0x%p, cmd 0x%p, tag 0x%x\n", cdev, cmd, ttinfo->tag);
  217. r2t->targ_xfer_tag = ttinfo->tag;
  218. }
  219. void cxgbit_unmap_cmd(struct iscsit_conn *conn, struct iscsit_cmd *cmd)
  220. {
  221. struct cxgbit_cmd *ccmd = iscsit_priv_cmd(cmd);
  222. if (ccmd->release) {
  223. if (cmd->se_cmd.se_cmd_flags & SCF_PASSTHROUGH_SG_TO_MEM_NOALLOC) {
  224. put_page(sg_page(&ccmd->sg));
  225. } else {
  226. struct cxgbit_sock *csk = conn->context;
  227. struct cxgbit_device *cdev = csk->com.cdev;
  228. struct cxgbi_ppm *ppm = cdev2ppm(cdev);
  229. struct cxgbi_task_tag_info *ttinfo = &ccmd->ttinfo;
  230. /* Abort the TCP conn if DDP is not complete to
  231. * avoid any possibility of DDP after freeing
  232. * the cmd.
  233. */
  234. if (unlikely(cmd->write_data_done !=
  235. cmd->se_cmd.data_length))
  236. cxgbit_abort_conn(csk);
  237. if (unlikely(ttinfo->sgl)) {
  238. dma_unmap_sg(&ppm->pdev->dev, ttinfo->sgl,
  239. ttinfo->nents, DMA_FROM_DEVICE);
  240. ttinfo->nents = 0;
  241. ttinfo->sgl = NULL;
  242. }
  243. cxgbi_ppm_ppod_release(ppm, ttinfo->idx);
  244. }
  245. ccmd->release = false;
  246. }
  247. }
  248. int cxgbit_ddp_init(struct cxgbit_device *cdev)
  249. {
  250. struct cxgb4_lld_info *lldi = &cdev->lldi;
  251. struct net_device *ndev = cdev->lldi.ports[0];
  252. struct cxgbi_tag_format tformat;
  253. int ret, i;
  254. if (!lldi->vr->iscsi.size) {
  255. pr_warn("%s, iscsi NOT enabled, check config!\n", ndev->name);
  256. return -EACCES;
  257. }
  258. memset(&tformat, 0, sizeof(struct cxgbi_tag_format));
  259. for (i = 0; i < 4; i++)
  260. tformat.pgsz_order[i] = (lldi->iscsi_pgsz_order >> (i << 3))
  261. & 0xF;
  262. cxgbi_tagmask_check(lldi->iscsi_tagmask, &tformat);
  263. ret = cxgbi_ppm_init(lldi->iscsi_ppm, cdev->lldi.ports[0],
  264. cdev->lldi.pdev, &cdev->lldi, &tformat,
  265. lldi->vr->iscsi.size, lldi->iscsi_llimit,
  266. lldi->vr->iscsi.start, 2,
  267. lldi->vr->ppod_edram.start,
  268. lldi->vr->ppod_edram.size);
  269. if (ret >= 0) {
  270. struct cxgbi_ppm *ppm = (struct cxgbi_ppm *)(*lldi->iscsi_ppm);
  271. if ((ppm->tformat.pgsz_idx_dflt < DDP_PGIDX_MAX) &&
  272. (ppm->ppmax >= 1024))
  273. set_bit(CDEV_DDP_ENABLE, &cdev->flags);
  274. ret = 0;
  275. }
  276. return ret;
  277. }