qcom-ngd-ctrl.c 61 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2011-2017, 2020-2021, The Linux Foundation. All rights reserved.
  3. // Copyright (c) 2018, Linaro Limited
  4. // Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. #include <linux/irq.h>
  6. #include <linux/kernel.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/slimbus.h>
  14. #include <linux/delay.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/mutex.h>
  17. #include <linux/notifier.h>
  18. #include <linux/remoteproc/qcom_rproc.h>
  19. #include <linux/of.h>
  20. #include <linux/io.h>
  21. #include <linux/soc/qcom/qmi.h>
  22. #include <linux/soc/qcom/pdr.h>
  23. #include <net/sock.h>
  24. #include "slimbus.h"
  25. #include <trace/events/rproc_qcom.h>
  26. /* NGD (Non-ported Generic Device) registers */
  27. #define NGD_CFG 0x0
  28. #define NGD_CFG_ENABLE BIT(0)
  29. #define NGD_CFG_RX_MSGQ_EN BIT(1)
  30. #define NGD_CFG_TX_MSGQ_EN BIT(2)
  31. #define NGD_STATUS 0x4
  32. #define NGD_LADDR BIT(1)
  33. #define NGD_RX_MSGQ_CFG 0x8
  34. #define NGD_INT_EN 0x10
  35. #define NGD_INT_RECFG_DONE BIT(24)
  36. #define NGD_INT_TX_NACKED_2 BIT(25)
  37. #define NGD_INT_MSG_BUF_CONTE BIT(26)
  38. #define NGD_INT_MSG_TX_INVAL BIT(27)
  39. #define NGD_INT_IE_VE_CHG BIT(28)
  40. #define NGD_INT_DEV_ERR BIT(29)
  41. #define NGD_INT_RX_MSG_RCVD BIT(30)
  42. #define NGD_INT_TX_MSG_SENT BIT(31)
  43. #define NGD_INT_STAT 0x14
  44. #define NGD_INT_CLR 0x18
  45. #define DEF_NGD_INT_MASK (NGD_INT_TX_NACKED_2 | NGD_INT_MSG_BUF_CONTE | \
  46. NGD_INT_MSG_TX_INVAL | NGD_INT_IE_VE_CHG | \
  47. NGD_INT_DEV_ERR | NGD_INT_TX_MSG_SENT | \
  48. NGD_INT_RX_MSG_RCVD)
  49. /* Slimbus QMI service */
  50. #define SLIMBUS_QMI_SVC_ID 0x0301
  51. #define SLIMBUS_QMI_SVC_V1 1
  52. #define SLIMBUS_QMI_INS_ID 0
  53. #define SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01 0x0020
  54. #define SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01 0x0020
  55. #define SLIMBUS_QMI_POWER_REQ_V01 0x0021
  56. #define SLIMBUS_QMI_POWER_RESP_V01 0x0021
  57. #define SLIMBUS_QMI_CHECK_FRAMER_STATUS_REQ 0x0022
  58. #define SLIMBUS_QMI_CHECK_FRAMER_STATUS_RESP 0x0022
  59. #define SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN 14
  60. #define SLIMBUS_QMI_POWER_RESP_MAX_MSG_LEN 7
  61. #define SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN 14
  62. #define SLIMBUS_QMI_SELECT_INSTANCE_RESP_MAX_MSG_LEN 7
  63. #define SLIMBUS_QMI_CHECK_FRAMER_STAT_RESP_MAX_MSG_LEN 7
  64. /* QMI response timeout of 500ms */
  65. #define SLIMBUS_QMI_RESP_TOUT 1000
  66. /* User defined commands */
  67. #define SLIM_USR_MC_GENERIC_ACK 0x25
  68. #define SLIM_USR_MC_MASTER_CAPABILITY 0x0
  69. #define SLIM_USR_MC_REPORT_SATELLITE 0x1
  70. #define SLIM_USR_MC_ADDR_QUERY 0xD
  71. #define SLIM_USR_MC_ADDR_REPLY 0xE
  72. #define SLIM_USR_MC_DEFINE_CHAN 0x20
  73. #define SLIM_USR_MC_DEF_ACT_CHAN 0x21
  74. #define SLIM_USR_MC_CHAN_CTRL 0x23
  75. #define SLIM_USR_MC_RECONFIG_NOW 0x24
  76. #define SLIM_USR_MC_REQ_BW 0x28
  77. #define SLIM_USR_MC_CONNECT_SRC 0x2C
  78. #define SLIM_USR_MC_CONNECT_SINK 0x2D
  79. #define SLIM_USR_MC_DISCONNECT_PORT 0x2E
  80. #define SLIM_USR_MC_REPEAT_CHANGE_VALUE 0x0
  81. #define QCOM_SLIM_NGD_AUTOSUSPEND (MSEC_PER_SEC / 10)
  82. #define SLIM_RX_MSGQ_TIMEOUT_VAL 0x10000
  83. #define SLIM_QMI_TIMEOUT_MS 1000
  84. #define SLIM_LA_MGR 0xFF
  85. #define SLIM_ROOT_FREQ 24576000
  86. #define LADDR_RETRY 5
  87. /* Per spec.max 40 bytes per received message */
  88. #define SLIM_MSGQ_BUF_LEN 40
  89. #define QCOM_SLIM_NGD_DESC_NUM 30
  90. #define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
  91. ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
  92. #define INIT_MX_RETRIES 10
  93. #define DEF_RETRY_MS 10
  94. #define SAT_MAGIC_LSB 0xD9
  95. #define SAT_MAGIC_MSB 0xC5
  96. #define SAT_MSG_VER 0x1
  97. #define SAT_MSG_PROT 0x1
  98. #define to_ngd(d) container_of(d, struct qcom_slim_ngd, dev)
  99. #define CREATE_TRACE_POINTS
  100. #include "trace.h"
  101. void __slimbus_dbg(const char *func, const char *fmt, ...)
  102. {
  103. struct va_format vaf = {
  104. .fmt = fmt,
  105. };
  106. va_list args;
  107. va_start(args, fmt);
  108. vaf.va = &args;
  109. trace_slimbus_dbg(func, &vaf);
  110. va_end(args);
  111. }
  112. struct ngd_reg_offset_data {
  113. u32 offset, size;
  114. };
  115. static const struct ngd_reg_offset_data ngd_v1_5_offset_info = {
  116. .offset = 0x1000,
  117. .size = 0x1000,
  118. };
  119. enum qcom_slim_ngd_state {
  120. QCOM_SLIM_NGD_CTRL_AWAKE,
  121. QCOM_SLIM_NGD_CTRL_IDLE,
  122. QCOM_SLIM_NGD_CTRL_ASLEEP,
  123. QCOM_SLIM_NGD_CTRL_DOWN,
  124. QCOM_SLIM_NGD_CTRL_SSR_GOING_DOWN,
  125. };
  126. struct qcom_slim_ngd_qmi {
  127. struct qmi_handle qmi;
  128. struct sockaddr_qrtr svc_info;
  129. struct qmi_handle svc_event_hdl;
  130. struct qmi_response_type_v01 resp;
  131. struct qmi_handle *handle;
  132. struct completion qmi_comp;
  133. };
  134. struct qcom_slim_ngd_ctrl;
  135. struct qcom_slim_ngd;
  136. struct qcom_slim_ngd_dma_desc {
  137. struct dma_async_tx_descriptor *desc;
  138. struct qcom_slim_ngd_ctrl *ctrl;
  139. struct completion *comp;
  140. dma_cookie_t cookie;
  141. dma_addr_t phys;
  142. void *base;
  143. };
  144. struct qcom_slim_ngd {
  145. struct platform_device *pdev;
  146. void __iomem *base;
  147. int id;
  148. };
  149. /*
  150. * structure to store remote memory information
  151. * @r_res: stores remote memory resource structre parsed from devicetree
  152. * @r_vbase: stores latest virtual base address of remote memory region
  153. * @r_vsbase: stores virtual base address of remote memory region
  154. * parsed from devicetree
  155. * @r_pbase: stores physical base address of remote memory region
  156. * @is_r_mem: boolean to indicate if remote memory is used or not
  157. */
  158. struct remote_mem {
  159. struct resource *r_res;
  160. void __iomem *r_vbase;
  161. void __iomem *r_vsbase;
  162. u32 r_pbase;
  163. bool is_r_mem;
  164. };
  165. struct qcom_slim_ngd_ctrl {
  166. struct slim_framer framer;
  167. struct slim_controller ctrl;
  168. struct qcom_slim_ngd_qmi qmi;
  169. struct qcom_slim_ngd *ngd;
  170. struct device *dev;
  171. void __iomem *base;
  172. struct dma_chan *dma_rx_channel;
  173. struct dma_chan *dma_tx_channel;
  174. struct qcom_slim_ngd_dma_desc rx_desc[QCOM_SLIM_NGD_DESC_NUM];
  175. struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM];
  176. struct completion reconf;
  177. struct completion ctrl_up;
  178. struct work_struct m_work;
  179. struct work_struct ngd_up_work;
  180. struct workqueue_struct *mwq;
  181. struct completion qmi_up;
  182. struct completion xfer_done;
  183. struct completion sync_done;
  184. spinlock_t tx_buf_lock;
  185. struct mutex tx_lock;
  186. struct mutex suspend_resume_lock;
  187. struct mutex ssr_lock;
  188. struct mutex qmi_handle_lock;
  189. struct notifier_block nb;
  190. void *notifier;
  191. struct pdr_handle *pdr;
  192. enum qcom_slim_ngd_state state;
  193. dma_addr_t rx_phys_base;
  194. dma_addr_t tx_phys_base;
  195. void *rx_base;
  196. void *tx_base;
  197. int tx_tail;
  198. int tx_head;
  199. u32 ver;
  200. struct remote_mem r_mem;
  201. int default_ipc_log_mask;
  202. int ipc_log_mask;
  203. bool sysfs_created;
  204. bool wait_for_adsp_up;
  205. void *ipc_slimbus_log;
  206. void *ipc_slimbus_log_err;
  207. unsigned int irq;
  208. bool irq_disabled;
  209. bool capability_timeout;
  210. };
  211. enum slimbus_mode_enum_type_v01 {
  212. /* To force a 32 bit signed enum. Do not change or use*/
  213. SLIMBUS_MODE_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
  214. SLIMBUS_MODE_SATELLITE_V01 = 1,
  215. SLIMBUS_MODE_MASTER_V01 = 2,
  216. SLIMBUS_MODE_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
  217. };
  218. enum slimbus_pm_enum_type_v01 {
  219. /* To force a 32 bit signed enum. Do not change or use*/
  220. SLIMBUS_PM_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
  221. SLIMBUS_PM_INACTIVE_V01 = 1,
  222. SLIMBUS_PM_ACTIVE_V01 = 2,
  223. SLIMBUS_PM_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
  224. };
  225. enum slimbus_resp_enum_type_v01 {
  226. SLIMBUS_RESP_ENUM_TYPE_MIN_VAL_V01 = INT_MIN,
  227. SLIMBUS_RESP_SYNCHRONOUS_V01 = 1,
  228. SLIMBUS_RESP_ENUM_TYPE_MAX_VAL_V01 = INT_MAX,
  229. };
  230. struct slimbus_select_inst_req_msg_v01 {
  231. uint32_t instance;
  232. uint8_t mode_valid;
  233. enum slimbus_mode_enum_type_v01 mode;
  234. };
  235. struct slimbus_select_inst_resp_msg_v01 {
  236. struct qmi_response_type_v01 resp;
  237. };
  238. struct slimbus_power_req_msg_v01 {
  239. enum slimbus_pm_enum_type_v01 pm_req;
  240. uint8_t resp_type_valid;
  241. enum slimbus_resp_enum_type_v01 resp_type;
  242. };
  243. struct slimbus_power_resp_msg_v01 {
  244. struct qmi_response_type_v01 resp;
  245. };
  246. static int qcom_slim_ngd_runtime_suspend(struct device *device);
  247. static struct qmi_elem_info slimbus_select_inst_req_msg_v01_ei[] = {
  248. {
  249. .data_type = QMI_UNSIGNED_4_BYTE,
  250. .elem_len = 1,
  251. .elem_size = sizeof(uint32_t),
  252. .array_type = NO_ARRAY,
  253. .tlv_type = 0x01,
  254. .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
  255. instance),
  256. .ei_array = NULL,
  257. },
  258. {
  259. .data_type = QMI_OPT_FLAG,
  260. .elem_len = 1,
  261. .elem_size = sizeof(uint8_t),
  262. .array_type = NO_ARRAY,
  263. .tlv_type = 0x10,
  264. .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
  265. mode_valid),
  266. .ei_array = NULL,
  267. },
  268. {
  269. .data_type = QMI_UNSIGNED_4_BYTE,
  270. .elem_len = 1,
  271. .elem_size = sizeof(enum slimbus_mode_enum_type_v01),
  272. .array_type = NO_ARRAY,
  273. .tlv_type = 0x10,
  274. .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
  275. mode),
  276. .ei_array = NULL,
  277. },
  278. {
  279. .data_type = QMI_EOTI,
  280. .elem_len = 0,
  281. .elem_size = 0,
  282. .array_type = NO_ARRAY,
  283. .tlv_type = 0x00,
  284. .offset = 0,
  285. .ei_array = NULL,
  286. },
  287. };
  288. static struct qmi_elem_info slimbus_select_inst_resp_msg_v01_ei[] = {
  289. {
  290. .data_type = QMI_STRUCT,
  291. .elem_len = 1,
  292. .elem_size = sizeof(struct qmi_response_type_v01),
  293. .array_type = NO_ARRAY,
  294. .tlv_type = 0x02,
  295. .offset = offsetof(struct slimbus_select_inst_resp_msg_v01,
  296. resp),
  297. .ei_array = qmi_response_type_v01_ei,
  298. },
  299. {
  300. .data_type = QMI_EOTI,
  301. .elem_len = 0,
  302. .elem_size = 0,
  303. .array_type = NO_ARRAY,
  304. .tlv_type = 0x00,
  305. .offset = 0,
  306. .ei_array = NULL,
  307. },
  308. };
  309. static struct qmi_elem_info slimbus_power_req_msg_v01_ei[] = {
  310. {
  311. .data_type = QMI_UNSIGNED_4_BYTE,
  312. .elem_len = 1,
  313. .elem_size = sizeof(enum slimbus_pm_enum_type_v01),
  314. .array_type = NO_ARRAY,
  315. .tlv_type = 0x01,
  316. .offset = offsetof(struct slimbus_power_req_msg_v01,
  317. pm_req),
  318. .ei_array = NULL,
  319. },
  320. {
  321. .data_type = QMI_OPT_FLAG,
  322. .elem_len = 1,
  323. .elem_size = sizeof(uint8_t),
  324. .array_type = NO_ARRAY,
  325. .tlv_type = 0x10,
  326. .offset = offsetof(struct slimbus_power_req_msg_v01,
  327. resp_type_valid),
  328. },
  329. {
  330. .data_type = QMI_SIGNED_4_BYTE_ENUM,
  331. .elem_len = 1,
  332. .elem_size = sizeof(enum slimbus_resp_enum_type_v01),
  333. .array_type = NO_ARRAY,
  334. .tlv_type = 0x10,
  335. .offset = offsetof(struct slimbus_power_req_msg_v01,
  336. resp_type),
  337. },
  338. {
  339. .data_type = QMI_EOTI,
  340. .elem_len = 0,
  341. .elem_size = 0,
  342. .array_type = NO_ARRAY,
  343. .tlv_type = 0x00,
  344. .offset = 0,
  345. .ei_array = NULL,
  346. },
  347. };
  348. static struct qmi_elem_info slimbus_power_resp_msg_v01_ei[] = {
  349. {
  350. .data_type = QMI_STRUCT,
  351. .elem_len = 1,
  352. .elem_size = sizeof(struct qmi_response_type_v01),
  353. .array_type = NO_ARRAY,
  354. .tlv_type = 0x02,
  355. .offset = offsetof(struct slimbus_power_resp_msg_v01, resp),
  356. .ei_array = qmi_response_type_v01_ei,
  357. },
  358. {
  359. .data_type = QMI_EOTI,
  360. .elem_len = 0,
  361. .elem_size = 0,
  362. .array_type = NO_ARRAY,
  363. .tlv_type = 0x00,
  364. .offset = 0,
  365. .ei_array = NULL,
  366. },
  367. };
  368. static int qcom_slim_qmi_send_select_inst_req(struct qcom_slim_ngd_ctrl *ctrl,
  369. struct slimbus_select_inst_req_msg_v01 *req)
  370. {
  371. struct slimbus_select_inst_resp_msg_v01 resp = { { 0, 0 } };
  372. struct qmi_txn txn;
  373. int rc;
  374. rc = qmi_txn_init(ctrl->qmi.handle, &txn,
  375. slimbus_select_inst_resp_msg_v01_ei, &resp);
  376. if (rc < 0) {
  377. SLIM_ERR(ctrl, "QMI TXN init fail: %d\n", rc);
  378. return rc;
  379. }
  380. rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
  381. SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01,
  382. SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN,
  383. slimbus_select_inst_req_msg_v01_ei, req);
  384. if (rc < 0) {
  385. SLIM_ERR(ctrl, "QMI send req fail %d\n", rc);
  386. qmi_txn_cancel(&txn);
  387. return rc;
  388. }
  389. rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
  390. if (rc < 0) {
  391. SLIM_ERR(ctrl, "QMI TXN wait fail: %d\n", rc);
  392. return rc;
  393. }
  394. /* Check the response */
  395. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  396. SLIM_ERR(ctrl, "QMI request failed 0x%x\n",
  397. resp.resp.result);
  398. return -EREMOTEIO;
  399. }
  400. SLIM_INFO(ctrl, "%s end RC=%d\n", __func__, rc);
  401. return 0;
  402. }
  403. static void qcom_slim_qmi_power_resp_cb(struct qmi_handle *handle,
  404. struct sockaddr_qrtr *sq,
  405. struct qmi_txn *txn, const void *data)
  406. {
  407. struct slimbus_power_resp_msg_v01 *resp;
  408. resp = (struct slimbus_power_resp_msg_v01 *)data;
  409. if (resp->resp.result != QMI_RESULT_SUCCESS_V01)
  410. pr_err("QMI power request failed 0x%x\n",
  411. resp->resp.result);
  412. complete(&txn->completion);
  413. }
  414. static int qcom_slim_qmi_send_power_request(struct qcom_slim_ngd_ctrl *ctrl,
  415. struct slimbus_power_req_msg_v01 *req)
  416. {
  417. struct slimbus_power_resp_msg_v01 resp = { { 0, 0 } };
  418. struct qmi_txn txn;
  419. int rc;
  420. mutex_lock(&ctrl->qmi_handle_lock);
  421. if (ctrl->qmi.handle == NULL) {
  422. mutex_unlock(&ctrl->qmi_handle_lock);
  423. return -EINVAL;
  424. }
  425. rc = qmi_txn_init(ctrl->qmi.handle, &txn,
  426. slimbus_power_resp_msg_v01_ei, &resp);
  427. rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
  428. SLIMBUS_QMI_POWER_REQ_V01,
  429. SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
  430. slimbus_power_req_msg_v01_ei, req);
  431. if (rc < 0) {
  432. SLIM_ERR(ctrl, "QMI send req fail %d\n", rc);
  433. mutex_unlock(&ctrl->qmi_handle_lock);
  434. qmi_txn_cancel(&txn);
  435. return rc;
  436. }
  437. mutex_unlock(&ctrl->qmi_handle_lock);
  438. rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
  439. if (rc < 0) {
  440. SLIM_ERR(ctrl, "QMI TXN wait fail: %d\n", rc);
  441. return rc;
  442. }
  443. /* Check the response */
  444. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  445. SLIM_ERR(ctrl, "QMI request failed 0x%x\n",
  446. resp.resp.result);
  447. return -EREMOTEIO;
  448. }
  449. SLIM_INFO(ctrl, "%s end %d\n", __func__, req->pm_req);
  450. return 0;
  451. }
  452. static const struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = {
  453. {
  454. .type = QMI_RESPONSE,
  455. .msg_id = SLIMBUS_QMI_POWER_RESP_V01,
  456. .ei = slimbus_power_resp_msg_v01_ei,
  457. .decoded_size = sizeof(struct slimbus_power_resp_msg_v01),
  458. .fn = qcom_slim_qmi_power_resp_cb,
  459. },
  460. {}
  461. };
  462. static int qcom_slim_qmi_init(struct qcom_slim_ngd_ctrl *ctrl,
  463. bool apps_is_master)
  464. {
  465. struct slimbus_select_inst_req_msg_v01 req;
  466. struct qmi_handle *handle;
  467. int rc;
  468. if (ctrl->qmi.handle) {
  469. SLIM_INFO(ctrl, "qmi handle already allocated\n");
  470. return 0;
  471. }
  472. handle = devm_kzalloc(ctrl->dev, sizeof(*handle), GFP_KERNEL);
  473. if (!handle)
  474. return -ENOMEM;
  475. rc = qmi_handle_init(handle, SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
  476. NULL, qcom_slim_qmi_msg_handlers);
  477. if (rc < 0) {
  478. dev_err(ctrl->dev, "QMI client init failed: %d\n", rc);
  479. goto qmi_handle_init_failed;
  480. }
  481. rc = kernel_connect(handle->sock,
  482. (struct sockaddr *)&ctrl->qmi.svc_info,
  483. sizeof(ctrl->qmi.svc_info), 0);
  484. if (rc < 0) {
  485. SLIM_ERR(ctrl, "Remote Service connect failed: %d\n", rc);
  486. goto qmi_connect_to_service_failed;
  487. }
  488. /* Instance is 0 based */
  489. req.instance = (ctrl->ngd->id >> 1);
  490. req.mode_valid = 1;
  491. /* Mode indicates the role of the ADSP */
  492. if (apps_is_master)
  493. req.mode = SLIMBUS_MODE_SATELLITE_V01;
  494. else
  495. req.mode = SLIMBUS_MODE_MASTER_V01;
  496. ctrl->qmi.handle = handle;
  497. rc = qcom_slim_qmi_send_select_inst_req(ctrl, &req);
  498. if (rc) {
  499. dev_err(ctrl->dev, "failed to select h/w instance\n");
  500. goto qmi_select_instance_failed;
  501. }
  502. return 0;
  503. qmi_select_instance_failed:
  504. ctrl->qmi.handle = NULL;
  505. qmi_connect_to_service_failed:
  506. qmi_handle_release(handle);
  507. qmi_handle_init_failed:
  508. devm_kfree(ctrl->dev, handle);
  509. return rc;
  510. }
  511. static void qcom_slim_qmi_exit(struct qcom_slim_ngd_ctrl *ctrl)
  512. {
  513. mutex_lock(&ctrl->qmi_handle_lock);
  514. if (!ctrl->qmi.handle) {
  515. mutex_unlock(&ctrl->qmi_handle_lock);
  516. return;
  517. }
  518. qmi_handle_release(ctrl->qmi.handle);
  519. devm_kfree(ctrl->dev, ctrl->qmi.handle);
  520. ctrl->qmi.handle = NULL;
  521. mutex_unlock(&ctrl->qmi_handle_lock);
  522. }
  523. static int qcom_slim_qmi_power_request(struct qcom_slim_ngd_ctrl *ctrl,
  524. bool active)
  525. {
  526. struct slimbus_power_req_msg_v01 req;
  527. if (active)
  528. req.pm_req = SLIMBUS_PM_ACTIVE_V01;
  529. else
  530. req.pm_req = SLIMBUS_PM_INACTIVE_V01;
  531. req.resp_type_valid = 0;
  532. return qcom_slim_qmi_send_power_request(ctrl, &req);
  533. }
  534. static u32 *qcom_slim_ngd_tx_msg_get(struct qcom_slim_ngd_ctrl *ctrl, int len,
  535. struct completion *comp)
  536. {
  537. struct qcom_slim_ngd_dma_desc *desc;
  538. unsigned long flags;
  539. spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
  540. if (((ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM == ctrl->tx_head)
  541. || !ctrl->tx_base) {
  542. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  543. return NULL;
  544. }
  545. desc = &ctrl->txdesc[ctrl->tx_tail];
  546. desc->base = ctrl->tx_base + ctrl->tx_tail * SLIM_MSGQ_BUF_LEN;
  547. desc->comp = comp;
  548. ctrl->tx_tail = (ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM;
  549. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  550. return desc->base;
  551. }
  552. static void qcom_slim_ngd_tx_msg_dma_cb(void *args)
  553. {
  554. struct qcom_slim_ngd_dma_desc *desc = args;
  555. struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
  556. unsigned long flags;
  557. /* Return if capability exchange is not successful due to timeout */
  558. if (ctrl->capability_timeout) {
  559. ctrl->capability_timeout = false;
  560. SLIM_WARN(ctrl, "Timedout due to delayed interrupt\n");
  561. desc->comp = NULL;
  562. return;
  563. }
  564. spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
  565. if (desc->comp) {
  566. complete(desc->comp);
  567. desc->comp = NULL;
  568. }
  569. ctrl->tx_head = (ctrl->tx_head + 1) % QCOM_SLIM_NGD_DESC_NUM;
  570. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  571. }
  572. static int qcom_slim_ngd_tx_msg_post(struct qcom_slim_ngd_ctrl *ctrl,
  573. void *buf, int len)
  574. {
  575. struct qcom_slim_ngd_dma_desc *desc;
  576. unsigned long flags;
  577. int ret, index, offset;
  578. spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
  579. offset = buf - ctrl->tx_base;
  580. index = offset/SLIM_MSGQ_BUF_LEN;
  581. desc = &ctrl->txdesc[index];
  582. desc->phys = ctrl->tx_phys_base + offset;
  583. desc->base = ctrl->tx_base + offset;
  584. desc->ctrl = ctrl;
  585. len = (len + 3) & 0xfc;
  586. for (ret = 0; ret < ((len) >> 2); ret++)
  587. SLIM_INFO(ctrl, "BAM TX len = %d buf[%d]:0x%x\n", len, ret, ((u32 *)buf)[ret]);
  588. if (!ctrl->dma_tx_channel)
  589. SLIM_WARN(ctrl, " tx channel not available\n");
  590. desc->desc = dmaengine_prep_slave_single(ctrl->dma_tx_channel,
  591. desc->phys, len,
  592. DMA_MEM_TO_DEV,
  593. DMA_PREP_INTERRUPT);
  594. if (!desc->desc) {
  595. dev_err(ctrl->dev, "unable to prepare channel\n");
  596. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  597. return -EINVAL;
  598. }
  599. desc->desc->callback = qcom_slim_ngd_tx_msg_dma_cb;
  600. desc->desc->callback_param = desc;
  601. desc->desc->cookie = dmaengine_submit(desc->desc);
  602. dma_async_issue_pending(ctrl->dma_tx_channel);
  603. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  604. return 0;
  605. }
  606. static void qcom_slim_ngd_rx(struct qcom_slim_ngd_ctrl *ctrl, u8 *buf)
  607. {
  608. u8 mc, mt, len;
  609. mt = SLIM_HEADER_GET_MT(buf[0]);
  610. len = SLIM_HEADER_GET_RL(buf[0]);
  611. mc = SLIM_HEADER_GET_MC(buf[1]);
  612. SLIM_INFO(ctrl, "BAM RX len = %d buf[0]:0x%x buf[1]:0x%x\n", len, buf[0], buf[1]);
  613. if (mc == SLIM_USR_MC_MASTER_CAPABILITY &&
  614. mt == SLIM_MSG_MT_SRC_REFERRED_USER)
  615. queue_work(ctrl->mwq, &ctrl->m_work);
  616. if (mc == SLIM_MSG_MC_REPLY_INFORMATION ||
  617. mc == SLIM_MSG_MC_REPLY_VALUE || (mc == SLIM_USR_MC_ADDR_REPLY &&
  618. mt == SLIM_MSG_MT_SRC_REFERRED_USER) ||
  619. (mc == SLIM_USR_MC_GENERIC_ACK &&
  620. mt == SLIM_MSG_MT_SRC_REFERRED_USER)) {
  621. slim_msg_response(&ctrl->ctrl, &buf[4], buf[3], len - 4);
  622. pm_runtime_mark_last_busy(ctrl->ctrl.dev);
  623. }
  624. }
  625. static void qcom_slim_ngd_rx_msgq_cb(void *args)
  626. {
  627. struct qcom_slim_ngd_dma_desc *desc = args;
  628. struct qcom_slim_ngd_ctrl *ctrl;
  629. if (!desc)
  630. return;
  631. ctrl = desc->ctrl;
  632. qcom_slim_ngd_rx(ctrl, (u8 *)desc->base);
  633. /* Add descriptor back to the queue */
  634. desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
  635. desc->phys, SLIM_MSGQ_BUF_LEN,
  636. DMA_DEV_TO_MEM,
  637. DMA_PREP_INTERRUPT);
  638. if (!desc->desc) {
  639. dev_err(ctrl->dev, "Unable to prepare rx channel\n");
  640. return;
  641. }
  642. desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
  643. desc->desc->callback_param = desc;
  644. desc->desc->cookie = dmaengine_submit(desc->desc);
  645. dma_async_issue_pending(ctrl->dma_rx_channel);
  646. }
  647. static int qcom_slim_ngd_post_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
  648. {
  649. struct qcom_slim_ngd_dma_desc *desc;
  650. int i;
  651. for (i = 0; i < QCOM_SLIM_NGD_DESC_NUM; i++) {
  652. desc = &ctrl->rx_desc[i];
  653. desc->phys = ctrl->rx_phys_base + i * SLIM_MSGQ_BUF_LEN;
  654. desc->ctrl = ctrl;
  655. desc->base = ctrl->rx_base + i * SLIM_MSGQ_BUF_LEN;
  656. desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
  657. desc->phys, SLIM_MSGQ_BUF_LEN,
  658. DMA_DEV_TO_MEM,
  659. DMA_PREP_INTERRUPT);
  660. if (!desc->desc) {
  661. dev_err(ctrl->dev, "Unable to prepare rx channel\n");
  662. return -EINVAL;
  663. }
  664. desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
  665. desc->desc->callback_param = desc;
  666. desc->desc->cookie = dmaengine_submit(desc->desc);
  667. }
  668. dma_async_issue_pending(ctrl->dma_rx_channel);
  669. return 0;
  670. }
  671. static int qcom_slim_ngd_init_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
  672. {
  673. struct device *dev = ctrl->dev;
  674. int ret, size;
  675. dma_addr_t phys;
  676. ctrl->dma_rx_channel = dma_request_chan(dev, "rx");
  677. if (IS_ERR(ctrl->dma_rx_channel)) {
  678. dev_err(dev, "Failed to request RX dma channel");
  679. ret = PTR_ERR(ctrl->dma_rx_channel);
  680. ctrl->dma_rx_channel = NULL;
  681. return ret;
  682. }
  683. size = QCOM_SLIM_NGD_DESC_NUM * SLIM_MSGQ_BUF_LEN;
  684. ctrl->rx_base = ctrl->r_mem.is_r_mem ? ctrl->r_mem.r_vbase :
  685. dma_alloc_coherent(dev, size, &phys, GFP_KERNEL);
  686. if (!ctrl->rx_base) {
  687. ret = -ENOMEM;
  688. goto rel_rx;
  689. }
  690. ctrl->rx_phys_base = ctrl->r_mem.is_r_mem ?
  691. (unsigned long long)ctrl->r_mem.r_res->start : phys;
  692. if (ctrl->r_mem.is_r_mem) {
  693. memset_io(ctrl->rx_base, 0x00, size);
  694. ctrl->r_mem.r_vbase = ctrl->r_mem.r_vbase + size;
  695. ctrl->r_mem.r_res->start = ctrl->r_mem.r_res->start + size;
  696. }
  697. ret = qcom_slim_ngd_post_rx_msgq(ctrl);
  698. if (ret) {
  699. dev_err(dev, "post_rx_msgq() failed 0x%x\n", ret);
  700. goto rx_post_err;
  701. }
  702. return 0;
  703. rx_post_err:
  704. if (!ctrl->r_mem.is_r_mem)
  705. dma_free_coherent(dev, size, ctrl->rx_base, ctrl->rx_phys_base);
  706. rel_rx:
  707. dma_release_channel(ctrl->dma_rx_channel);
  708. return ret;
  709. }
  710. static int qcom_slim_ngd_init_tx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
  711. {
  712. struct device *dev = ctrl->dev;
  713. unsigned long flags;
  714. int ret = 0;
  715. int size;
  716. dma_addr_t phys;
  717. ctrl->dma_tx_channel = dma_request_chan(dev, "tx");
  718. if (IS_ERR(ctrl->dma_tx_channel)) {
  719. dev_err(dev, "Failed to request TX dma channel");
  720. ret = PTR_ERR(ctrl->dma_tx_channel);
  721. ctrl->dma_tx_channel = NULL;
  722. return ret;
  723. }
  724. size = ((QCOM_SLIM_NGD_DESC_NUM + 1) * SLIM_MSGQ_BUF_LEN);
  725. ctrl->tx_base = ctrl->r_mem.is_r_mem ? ctrl->r_mem.r_vbase :
  726. dma_alloc_coherent(dev, size, &phys, GFP_KERNEL);
  727. if (!ctrl->tx_base) {
  728. ret = -EINVAL;
  729. goto rel_tx;
  730. }
  731. ctrl->tx_phys_base = ctrl->r_mem.is_r_mem ?
  732. (unsigned long long)ctrl->r_mem.r_res->start : phys;
  733. if (ctrl->r_mem.is_r_mem) {
  734. memset_io(ctrl->tx_base, 0x00, size);
  735. ctrl->r_mem.r_vbase = ctrl->r_mem.r_vbase + size;
  736. ctrl->r_mem.r_res->start = ctrl->r_mem.r_res->start + size;
  737. }
  738. spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
  739. ctrl->tx_tail = 0;
  740. ctrl->tx_head = 0;
  741. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  742. return 0;
  743. rel_tx:
  744. dma_release_channel(ctrl->dma_tx_channel);
  745. return ret;
  746. }
  747. static int qcom_slim_ngd_init_dma(struct qcom_slim_ngd_ctrl *ctrl)
  748. {
  749. int ret = 0;
  750. SLIM_INFO(ctrl, "SLIM: NGD init dma\n");
  751. ret = qcom_slim_ngd_init_rx_msgq(ctrl);
  752. if (ret) {
  753. dev_err(ctrl->dev, "rx dma init failed\n");
  754. return ret;
  755. }
  756. ret = qcom_slim_ngd_init_tx_msgq(ctrl);
  757. if (ret)
  758. dev_err(ctrl->dev, "tx dma init failed\n");
  759. return ret;
  760. }
  761. static void qcom_slim_ngd_enable_irq(struct qcom_slim_ngd_ctrl *ctrl)
  762. {
  763. if (ctrl->irq_disabled) {
  764. enable_irq(ctrl->irq);
  765. ctrl->irq_disabled = false;
  766. SLIM_INFO(ctrl, "Slim ngd IRQ enabled\n");
  767. }
  768. }
  769. static void qcom_slim_ngd_disable_irq(struct qcom_slim_ngd_ctrl *ctrl)
  770. {
  771. if (!ctrl->irq_disabled) {
  772. disable_irq(ctrl->irq);
  773. ctrl->irq_disabled = true;
  774. SLIM_INFO(ctrl, "Slim ngd IRQ disabled\n");
  775. }
  776. }
  777. static irqreturn_t qcom_slim_ngd_interrupt(int irq, void *d)
  778. {
  779. struct qcom_slim_ngd_ctrl *ctrl = d;
  780. void __iomem *base = ctrl->ngd->base;
  781. u32 stat;
  782. if (pm_runtime_suspended(ctrl->ctrl.dev)) {
  783. SLIM_INFO(ctrl, "Slimbus is in suspend state %d\n",
  784. ctrl->irq_disabled);
  785. return IRQ_HANDLED;
  786. }
  787. stat = readl(base + NGD_INT_STAT);
  788. if ((stat & NGD_INT_MSG_BUF_CONTE) ||
  789. (stat & NGD_INT_MSG_TX_INVAL) || (stat & NGD_INT_DEV_ERR) ||
  790. (stat & NGD_INT_TX_NACKED_2)) {
  791. SLIM_WARN(ctrl, "Error Interrupt received 0x%x\n", stat);
  792. }
  793. writel(stat, base + NGD_INT_CLR);
  794. return IRQ_HANDLED;
  795. }
  796. static int check_hw_state(struct qcom_slim_ngd_ctrl *ctrl, struct slim_msg_txn *txn)
  797. {
  798. bool report_sat = false;
  799. if (txn->mc == SLIM_USR_MC_REPORT_SATELLITE &&
  800. txn->mt == SLIM_MSG_MT_SRC_REFERRED_USER)
  801. report_sat = true;
  802. /* If txn is tried when controller is down, return or wait for ADSP to boot */
  803. if (!report_sat) {
  804. if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
  805. u8 mc = (u8)txn->mc;
  806. int timeout;
  807. SLIM_INFO(ctrl, "ADSP slimbus not up yet MC:0x%x,mt:0x%x\n",
  808. mc, txn->mt);
  809. if ((txn->mt == SLIM_MSG_MT_DEST_REFERRED_USER) &&
  810. ((mc == SLIM_USR_MC_CHAN_CTRL ||
  811. mc == SLIM_USR_MC_DISCONNECT_PORT ||
  812. mc == SLIM_USR_MC_RECONFIG_NOW)))
  813. return -EREMOTEIO;
  814. if ((txn->mt == SLIM_MSG_MT_CORE) &&
  815. ((mc == SLIM_MSG_MC_DISCONNECT_PORT ||
  816. mc == SLIM_MSG_MC_NEXT_REMOVE_CHANNEL ||
  817. mc == SLIM_USR_MC_RECONFIG_NOW)))
  818. return -EINVAL;
  819. if ((txn->mt == SLIM_MSG_MT_CORE) &&
  820. ((mc >= SLIM_MSG_MC_CONNECT_SOURCE &&
  821. mc <= SLIM_MSG_MC_CHANGE_CONTENT) ||
  822. (mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
  823. mc <= SLIM_MSG_MC_RECONFIGURE_NOW)))
  824. return -EREMOTEIO;
  825. if ((txn->mt == SLIM_MSG_MT_DEST_REFERRED_USER) &&
  826. ((mc >= SLIM_USR_MC_DEFINE_CHAN &&
  827. mc < SLIM_USR_MC_DISCONNECT_PORT)))
  828. return -EREMOTEIO;
  829. if (!ctrl->wait_for_adsp_up) {
  830. SLIM_INFO(ctrl, "Not waiting for ADSP up MC:0x%x,mt:0x%x\n",
  831. mc, txn->mt);
  832. return -EREMOTEIO;
  833. }
  834. reinit_completion(&ctrl->ctrl_up);
  835. timeout = wait_for_completion_timeout(&ctrl->ctrl_up, HZ);
  836. if (!timeout) {
  837. SLIM_WARN(ctrl, "ADSP slimbus not up timeout MC:0x%x,mt:0x%x\n",
  838. mc, txn->mt);
  839. return -EREMOTEIO;
  840. }
  841. }
  842. }
  843. return 0;
  844. }
  845. static int qcom_slim_ngd_xfer_msg(struct slim_controller *sctrl,
  846. struct slim_msg_txn *txn)
  847. {
  848. struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
  849. DECLARE_COMPLETION_ONSTACK(tx_sent);
  850. int ret, timeout, i;
  851. u8 wbuf[SLIM_MSGQ_BUF_LEN];
  852. u8 rbuf[SLIM_MSGQ_BUF_LEN];
  853. u32 *pbuf;
  854. u8 *puc;
  855. u8 la = txn->la;
  856. bool usr_msg = false;
  857. reinit_completion(&ctrl->xfer_done);
  858. if (txn->mt == SLIM_MSG_MT_CORE &&
  859. (txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
  860. txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW))
  861. return 0;
  862. if (txn->dt == SLIM_MSG_DEST_ENUMADDR) {
  863. SLIM_ERR(ctrl, "%s: proto not supported\n", __func__);
  864. return -EPROTONOSUPPORT;
  865. }
  866. if (txn->msg->num_bytes > SLIM_MSGQ_BUF_LEN ||
  867. txn->rl > SLIM_MSGQ_BUF_LEN) {
  868. SLIM_ERR(ctrl, "%s: msg exceeds HW limit\n", __func__);
  869. return -EINVAL;
  870. }
  871. /*
  872. * As part of SSR/PDR notify when ngd is going down tx_lock is
  873. * acquired and is waiting for ctrl_lock. While in parallel for
  874. * slim_get_logical_addr request from codecs ctrl_lock is acquired
  875. * first followed by qcom_slim_ngd_xfer_msg.
  876. * mutex_trylock will not wait to aquire lock if it is already been
  877. * acquired by SSR sequence hence it will unblock SSR to finish
  878. * gracefully
  879. */
  880. if (!mutex_trylock(&ctrl->tx_lock)) {
  881. SLIM_ERR(ctrl, "%s: ngd going down due SSR/PDR. skipping check hw state\n",
  882. __func__);
  883. return -EAGAIN;
  884. }
  885. ret = check_hw_state(ctrl, txn);
  886. if (ret) {
  887. SLIM_ERR(ctrl, "%s: ADSP slimbus not up MC:0x%x,mt:0x%x ret:%d\n",
  888. __func__, txn->mc, txn->mt, ret);
  889. mutex_unlock(&ctrl->tx_lock);
  890. return ret;
  891. }
  892. pbuf = qcom_slim_ngd_tx_msg_get(ctrl, txn->rl, &tx_sent);
  893. if (!pbuf) {
  894. SLIM_ERR(ctrl, "%s: Message buffer unavailable\n", __func__);
  895. mutex_unlock(&ctrl->tx_lock);
  896. return -ENOMEM;
  897. }
  898. mutex_unlock(&ctrl->tx_lock);
  899. if (txn->mt == SLIM_MSG_MT_CORE &&
  900. (txn->mc == SLIM_MSG_MC_CONNECT_SOURCE ||
  901. txn->mc == SLIM_MSG_MC_CONNECT_SINK ||
  902. txn->mc == SLIM_MSG_MC_DISCONNECT_PORT)) {
  903. txn->mt = SLIM_MSG_MT_DEST_REFERRED_USER;
  904. switch (txn->mc) {
  905. case SLIM_MSG_MC_CONNECT_SOURCE:
  906. txn->mc = SLIM_USR_MC_CONNECT_SRC;
  907. break;
  908. case SLIM_MSG_MC_CONNECT_SINK:
  909. txn->mc = SLIM_USR_MC_CONNECT_SINK;
  910. break;
  911. case SLIM_MSG_MC_DISCONNECT_PORT:
  912. txn->mc = SLIM_USR_MC_DISCONNECT_PORT;
  913. break;
  914. default:
  915. return -EINVAL;
  916. }
  917. usr_msg = true;
  918. i = 0;
  919. wbuf[i++] = txn->la;
  920. la = SLIM_LA_MGR;
  921. wbuf[i++] = txn->msg->wbuf[0];
  922. if (txn->mc != SLIM_USR_MC_DISCONNECT_PORT)
  923. wbuf[i++] = txn->msg->wbuf[1];
  924. txn->comp = &ctrl->xfer_done;
  925. ret = slim_alloc_txn_tid(sctrl, txn);
  926. if (ret) {
  927. SLIM_ERR(ctrl, "%s: Unable to allocate TID\n", __func__);
  928. return ret;
  929. }
  930. wbuf[i++] = txn->tid;
  931. txn->msg->num_bytes = i;
  932. txn->msg->wbuf = wbuf;
  933. txn->msg->rbuf = rbuf;
  934. txn->rl = txn->msg->num_bytes + 4;
  935. }
  936. /* HW expects length field to be excluded */
  937. txn->rl--;
  938. puc = (u8 *)pbuf;
  939. *pbuf = 0;
  940. if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
  941. *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 0,
  942. la);
  943. puc += 3;
  944. } else {
  945. *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 1,
  946. la);
  947. puc += 2;
  948. }
  949. if (slim_tid_txn(txn->mt, txn->mc))
  950. *(puc++) = txn->tid;
  951. if (slim_ec_txn(txn->mt, txn->mc)) {
  952. *(puc++) = (txn->ec & 0xFF);
  953. *(puc++) = (txn->ec >> 8) & 0xFF;
  954. }
  955. if (txn->msg && txn->msg->wbuf) {
  956. if (ctrl->r_mem.is_r_mem)
  957. memcpy_toio(puc, txn->msg->wbuf, txn->msg->num_bytes);
  958. else
  959. memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
  960. }
  961. if (!mutex_trylock(&ctrl->tx_lock)) {
  962. SLIM_ERR(ctrl, "%s: ngd going down due SSR/PDR, skipping tx msg post\n",
  963. __func__);
  964. txn->comp = NULL;
  965. return -EAGAIN;
  966. }
  967. ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl);
  968. if (ret) {
  969. mutex_unlock(&ctrl->tx_lock);
  970. txn->comp = NULL;
  971. return ret;
  972. }
  973. timeout = wait_for_completion_timeout(&tx_sent, 2*HZ);
  974. if (!timeout) {
  975. SLIM_ERR(ctrl, "%s: TX timed out:MC:0x%x,mt:0x%x", txn->mc,
  976. __func__, txn->mt);
  977. mutex_unlock(&ctrl->tx_lock);
  978. ctrl->capability_timeout = true;
  979. txn->comp = NULL;
  980. return -ETIMEDOUT;
  981. }
  982. if (usr_msg) {
  983. timeout = wait_for_completion_timeout(&ctrl->xfer_done, HZ);
  984. if (!timeout) {
  985. SLIM_ERR(ctrl, "%s: TX usr_msg timed out:MC:0x%x,mt:0x%x",
  986. __func__, txn->mc, txn->mt);
  987. ctrl->capability_timeout = true;
  988. txn->comp = NULL;
  989. mutex_unlock(&ctrl->tx_lock);
  990. return -ETIMEDOUT;
  991. }
  992. }
  993. mutex_unlock(&ctrl->tx_lock);
  994. return 0;
  995. }
  996. static int qcom_slim_ngd_xfer_msg_sync(struct slim_controller *ctrl,
  997. struct slim_msg_txn *txn)
  998. {
  999. struct qcom_slim_ngd_ctrl *dev =
  1000. container_of(ctrl, struct qcom_slim_ngd_ctrl, ctrl);
  1001. int ret, timeout;
  1002. reinit_completion(&dev->sync_done);
  1003. ret = pm_runtime_get_sync(ctrl->dev);
  1004. if (ret < 0) {
  1005. SLIM_ERR(dev, "SLIM %s: PM get_sync failed ret :%d count:%d TID:%d\n",
  1006. __func__, ret, atomic_read(&ctrl->dev->power.usage_count), txn->tid);
  1007. goto err;
  1008. }
  1009. SLIM_ERR(dev, "SLIM %s: PM get_sync count:%d TID:%d\n",
  1010. __func__, atomic_read(&ctrl->dev->power.usage_count), txn->tid);
  1011. txn->comp = &dev->sync_done;
  1012. ret = qcom_slim_ngd_xfer_msg(ctrl, txn);
  1013. if (ret) {
  1014. SLIM_ERR(dev, "SLIM %s: xfer_msg failed PM put count:%d TID:%d\n",
  1015. __func__, atomic_read(&ctrl->dev->power.usage_count), txn->tid);
  1016. goto err;
  1017. }
  1018. timeout = wait_for_completion_timeout(&dev->sync_done, HZ);
  1019. if (!timeout) {
  1020. SLIM_ERR(dev, "%s: TX sync timed out:MC:0x%x,mt:0x%x", txn->mc,
  1021. __func__, txn->mt);
  1022. ret = -ETIMEDOUT;
  1023. goto err;
  1024. }
  1025. return 0;
  1026. err:
  1027. pm_runtime_put_noidle(ctrl->dev);
  1028. /* Set device in suspended since resume failed */
  1029. pm_runtime_set_suspended(ctrl->dev);
  1030. return ret;
  1031. }
  1032. static int qcom_slim_calc_coef(struct slim_stream_runtime *rt, int *exp)
  1033. {
  1034. struct slim_controller *ctrl = rt->dev->ctrl;
  1035. int coef;
  1036. if (rt->ratem * ctrl->a_framer->superfreq < rt->rate)
  1037. rt->ratem++;
  1038. coef = rt->ratem;
  1039. /*
  1040. * Channel Rate Multiplier = Cx(2^E) is the formula we are using.
  1041. * Here C is the coffecient and E is the exponent.
  1042. * Coefficeint should be either 1 or 3 and exponenet
  1043. * should be an integer between 0 to 9, inclusive.
  1044. */
  1045. while (1) {
  1046. while ((coef & 0x1) != 0x1) {
  1047. coef >>= 1;
  1048. *exp = *exp + 1;
  1049. }
  1050. if (coef <= 3)
  1051. break;
  1052. coef++;
  1053. }
  1054. /*
  1055. * we rely on the coef value (1 or 3) to set a bit
  1056. * in the slimbus message packet. This bit is
  1057. * BIT(5) which is the segment rate coefficient.
  1058. */
  1059. if (coef == 1) {
  1060. if (*exp > 9)
  1061. return -EIO;
  1062. coef = 0;
  1063. } else {
  1064. if (*exp > 8)
  1065. return -EIO;
  1066. coef = 1;
  1067. }
  1068. return coef;
  1069. }
  1070. static int qcom_slim_ngd_enable_stream(struct slim_stream_runtime *rt)
  1071. {
  1072. struct slim_device *sdev = rt->dev;
  1073. struct slim_controller *ctrl = sdev->ctrl;
  1074. struct qcom_slim_ngd_ctrl *dev =
  1075. container_of(ctrl, struct qcom_slim_ngd_ctrl, ctrl);
  1076. struct slim_val_inf msg = {0};
  1077. u8 wbuf[SLIM_MSGQ_BUF_LEN];
  1078. u8 rbuf[SLIM_MSGQ_BUF_LEN];
  1079. struct slim_msg_txn txn = {0,};
  1080. int i, ret;
  1081. SLIM_INFO(dev, "%s start %d\n", __func__, true);
  1082. txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
  1083. txn.dt = SLIM_MSG_DEST_LOGICALADDR;
  1084. txn.la = SLIM_LA_MGR;
  1085. txn.ec = 0;
  1086. txn.msg = &msg;
  1087. txn.msg->num_bytes = 0;
  1088. txn.msg->wbuf = wbuf;
  1089. txn.msg->rbuf = rbuf;
  1090. for (i = 0; i < rt->num_ports; i++) {
  1091. struct slim_port *port = &rt->ports[i];
  1092. if (txn.msg->num_bytes == 0) {
  1093. int exp = 0, coef = 0;
  1094. wbuf[txn.msg->num_bytes++] = sdev->laddr;
  1095. SLIM_DBG(dev, "%s: wbuf[0] = 0x%x\n", __func__, sdev->laddr);
  1096. wbuf[txn.msg->num_bytes] = rt->bps >> 2 |
  1097. (port->ch.aux_fmt << 6);
  1098. /* calculate coef dynamically */
  1099. coef = qcom_slim_calc_coef(rt, &exp);
  1100. if (coef < 0) {
  1101. SLIM_ERR(dev,
  1102. "%s: error calculating coef %d\n", __func__,
  1103. coef);
  1104. return -EIO;
  1105. }
  1106. if (coef)
  1107. wbuf[txn.msg->num_bytes] |= BIT(5);
  1108. txn.msg->num_bytes++;
  1109. wbuf[txn.msg->num_bytes++] = exp << 4 | rt->prot;
  1110. if (rt->prot == SLIM_PROTO_ISO)
  1111. wbuf[txn.msg->num_bytes++] =
  1112. port->ch.prrate |
  1113. SLIM_CHANNEL_CONTENT_FL;
  1114. else
  1115. wbuf[txn.msg->num_bytes++] = port->ch.prrate;
  1116. ret = slim_alloc_txn_tid(ctrl, &txn);
  1117. if (ret) {
  1118. SLIM_ERR(dev, "%s: Fail to allocate TID\n", __func__);
  1119. return -ENXIO;
  1120. }
  1121. wbuf[txn.msg->num_bytes++] = txn.tid;
  1122. }
  1123. wbuf[txn.msg->num_bytes++] = port->ch.id;
  1124. SLIM_INFO(dev, "%s Channel ID %d\n", __func__, port->ch.id);
  1125. }
  1126. txn.mc = SLIM_USR_MC_DEF_ACT_CHAN;
  1127. txn.rl = txn.msg->num_bytes + 4;
  1128. ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
  1129. if (ret) {
  1130. slim_free_txn_tid(ctrl, &txn);
  1131. SLIM_ERR(dev, "%s: TX ACT_CHAN timed out:MC:0x%x,mt:0x%x", __func__, txn.mc,
  1132. txn.mt);
  1133. return ret;
  1134. }
  1135. txn.mc = SLIM_USR_MC_RECONFIG_NOW;
  1136. txn.msg->num_bytes = 2;
  1137. wbuf[1] = sdev->laddr;
  1138. txn.rl = txn.msg->num_bytes + 4;
  1139. ret = slim_alloc_txn_tid(ctrl, &txn);
  1140. if (ret) {
  1141. SLIM_ERR(dev, "%s: Fail to allocate TID\n", __func__);
  1142. return ret;
  1143. }
  1144. wbuf[0] = txn.tid;
  1145. ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
  1146. if (ret) {
  1147. slim_free_txn_tid(ctrl, &txn);
  1148. SLIM_ERR(dev, "%s: TX RECONFIG timed out:MC:0x%x,mt:0x%x", __func__, txn.mc,
  1149. txn.mt);
  1150. }
  1151. SLIM_INFO(dev, "%s End ret : %d\n", __func__, ret);
  1152. return ret;
  1153. }
  1154. static int qcom_slim_ngd_disable_stream(struct slim_stream_runtime *rt)
  1155. {
  1156. struct slim_device *sdev = rt->dev;
  1157. struct slim_controller *ctrl = sdev->ctrl;
  1158. struct qcom_slim_ngd_ctrl *dev =
  1159. container_of(ctrl, struct qcom_slim_ngd_ctrl, ctrl);
  1160. struct slim_val_inf msg = {0};
  1161. u8 wbuf[SLIM_MSGQ_BUF_LEN];
  1162. u8 rbuf[SLIM_MSGQ_BUF_LEN];
  1163. struct slim_msg_txn txn = {0,};
  1164. int i, ret;
  1165. SLIM_INFO(dev, "%s start %d\n", __func__, true);
  1166. txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
  1167. txn.dt = SLIM_MSG_DEST_LOGICALADDR;
  1168. txn.la = SLIM_LA_MGR;
  1169. txn.ec = 0;
  1170. txn.msg = &msg;
  1171. txn.msg->num_bytes = 0;
  1172. txn.msg->wbuf = wbuf;
  1173. txn.msg->rbuf = rbuf;
  1174. for (i = 0; i < rt->num_ports; i++) {
  1175. struct slim_port *port = &rt->ports[i];
  1176. if (txn.msg->num_bytes == 0) {
  1177. wbuf[txn.msg->num_bytes++] = (u8) (SLIM_CH_REMOVE << 6)
  1178. | (sdev->laddr & 0x1f);
  1179. SLIM_DBG(dev, "%s: wbuf[0] = 0x%x\n", __func__, sdev->laddr);
  1180. ret = slim_alloc_txn_tid(ctrl, &txn);
  1181. if (ret) {
  1182. SLIM_ERR(dev, "Fail to allocate TID ret:%d\n", -ENXIO);
  1183. return -ENXIO;
  1184. }
  1185. wbuf[txn.msg->num_bytes++] = txn.tid;
  1186. }
  1187. wbuf[txn.msg->num_bytes++] = port->ch.id;
  1188. SLIM_INFO(dev, "%s Channel ID %d\n", __func__, port->ch.id);
  1189. }
  1190. txn.mc = SLIM_USR_MC_CHAN_CTRL;
  1191. txn.rl = txn.msg->num_bytes + 4;
  1192. ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
  1193. if (ret) {
  1194. slim_free_txn_tid(ctrl, &txn);
  1195. SLIM_ERR(dev, "%s: TX CHAN_CTRL timed out:MC:0x%x,mt:0x%x ret:%d\n",
  1196. __func__, txn.mc, txn.mt, ret);
  1197. return ret;
  1198. }
  1199. txn.mc = SLIM_USR_MC_RECONFIG_NOW;
  1200. txn.msg->num_bytes = 2;
  1201. wbuf[1] = sdev->laddr;
  1202. txn.rl = txn.msg->num_bytes + 4;
  1203. ret = slim_alloc_txn_tid(ctrl, &txn);
  1204. if (ret) {
  1205. SLIM_ERR(dev, "%s: Fail to allocate TID ret:%d\n", __func__, ret);
  1206. return ret;
  1207. }
  1208. wbuf[0] = txn.tid;
  1209. ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
  1210. if (ret) {
  1211. slim_free_txn_tid(ctrl, &txn);
  1212. SLIM_ERR(dev, "%s: TX RECONFIG timed out:MC:0x%x,mt:0x%x ret:%d\n",
  1213. __func__, txn.mc, txn.mt, ret);
  1214. }
  1215. SLIM_INFO(dev, "%s End ret %d\n", __func__, ret);
  1216. return ret;
  1217. }
  1218. static int qcom_ngd_set_suspend(struct slim_controller *ctrl)
  1219. {
  1220. struct qcom_slim_ngd_ctrl *dev =
  1221. container_of(ctrl, struct qcom_slim_ngd_ctrl, ctrl);
  1222. int ret = 0;
  1223. ret = qcom_slim_ngd_runtime_suspend(dev->ctrl.dev);
  1224. if (ret) {
  1225. SLIM_INFO(dev, "%s: Failed to suspend:%d\n", __func__, ret);
  1226. return ret;
  1227. }
  1228. pm_runtime_disable(dev->ctrl.dev);
  1229. pm_runtime_set_suspended(dev->ctrl.dev);
  1230. pm_runtime_enable(dev->ctrl.dev);
  1231. return ret;
  1232. }
  1233. static int qcom_slim_ngd_get_laddr(struct slim_controller *ctrl,
  1234. struct slim_eaddr *ea, u8 *laddr)
  1235. {
  1236. struct slim_val_inf msg = {0};
  1237. u8 failed_ea[6] = {0, 0, 0, 0, 0, 0};
  1238. struct slim_msg_txn txn;
  1239. struct qcom_slim_ngd_ctrl *dev =
  1240. container_of(ctrl, struct qcom_slim_ngd_ctrl, ctrl);
  1241. u8 wbuf[10] = {0};
  1242. u8 rbuf[10] = {0};
  1243. int ret;
  1244. txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
  1245. txn.dt = SLIM_MSG_DEST_LOGICALADDR;
  1246. txn.la = SLIM_LA_MGR;
  1247. txn.ec = 0;
  1248. txn.mc = SLIM_USR_MC_ADDR_QUERY;
  1249. txn.rl = 11;
  1250. txn.msg = &msg;
  1251. txn.msg->num_bytes = 7;
  1252. txn.msg->wbuf = wbuf;
  1253. txn.msg->rbuf = rbuf;
  1254. ret = slim_alloc_txn_tid(ctrl, &txn);
  1255. if (ret < 0)
  1256. return ret;
  1257. wbuf[0] = (u8)txn.tid;
  1258. memcpy(&wbuf[1], ea, sizeof(*ea));
  1259. ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
  1260. if (ret) {
  1261. slim_free_txn_tid(ctrl, &txn);
  1262. return ret;
  1263. }
  1264. if (!memcmp(rbuf, failed_ea, 6))
  1265. return -ENXIO;
  1266. *laddr = rbuf[6];
  1267. SLIM_INFO(dev, "%s end ret : %d\n", __func__, ret);
  1268. return ret;
  1269. }
  1270. static int qcom_slim_ngd_exit_dma(struct qcom_slim_ngd_ctrl *ctrl)
  1271. {
  1272. struct device *dev = ctrl->dev;
  1273. int size;
  1274. SLIM_INFO(ctrl, "SLIM: NGD exit dma\n");
  1275. if (ctrl->dma_rx_channel) {
  1276. dmaengine_terminate_sync(ctrl->dma_rx_channel);
  1277. dma_release_channel(ctrl->dma_rx_channel);
  1278. }
  1279. if (ctrl->dma_tx_channel) {
  1280. dmaengine_terminate_sync(ctrl->dma_tx_channel);
  1281. dma_release_channel(ctrl->dma_tx_channel);
  1282. }
  1283. if (!ctrl->r_mem.is_r_mem) {
  1284. size = QCOM_SLIM_NGD_DESC_NUM * SLIM_MSGQ_BUF_LEN;
  1285. dma_free_coherent(dev, size, ctrl->rx_base, ctrl->rx_phys_base);
  1286. size = ((QCOM_SLIM_NGD_DESC_NUM + 1) * SLIM_MSGQ_BUF_LEN);
  1287. dma_free_coherent(dev, size, ctrl->tx_base, ctrl->tx_phys_base);
  1288. ctrl->tx_base = ctrl->rx_base = NULL;
  1289. } else {
  1290. ctrl->r_mem.r_vbase = ctrl->r_mem.r_vsbase;
  1291. ctrl->r_mem.r_res->start = ctrl->r_mem.r_pbase;
  1292. }
  1293. ctrl->dma_tx_channel = ctrl->dma_rx_channel = NULL;
  1294. return 0;
  1295. }
  1296. static void qcom_slim_ngd_setup(struct qcom_slim_ngd_ctrl *ctrl)
  1297. {
  1298. u32 cfg = readl_relaxed(ctrl->ngd->base);
  1299. SLIM_INFO(ctrl, "SLIM: NGD setup\n");
  1300. if ((ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) ||
  1301. (ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP))
  1302. qcom_slim_ngd_init_dma(ctrl);
  1303. /* By default enable message queues */
  1304. cfg |= NGD_CFG_RX_MSGQ_EN;
  1305. cfg |= NGD_CFG_TX_MSGQ_EN;
  1306. /* Enable NGD if it's not already enabled*/
  1307. if (!(cfg & NGD_CFG_ENABLE))
  1308. cfg |= NGD_CFG_ENABLE;
  1309. writel_relaxed(cfg, ctrl->ngd->base);
  1310. }
  1311. static int qcom_slim_ngd_power_up(struct qcom_slim_ngd_ctrl *ctrl)
  1312. {
  1313. enum qcom_slim_ngd_state cur_state = ctrl->state;
  1314. struct qcom_slim_ngd *ngd = ctrl->ngd;
  1315. u32 cfg, laddr, rx_msgq;
  1316. int timeout, ret = 0;
  1317. SLIM_INFO(ctrl, "SLIM: NGD power up\n");
  1318. if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
  1319. timeout = wait_for_completion_timeout(&ctrl->qmi.qmi_comp, HZ);
  1320. if (!timeout) {
  1321. SLIM_ERR(ctrl, "slimbus QMI init timed out\n");
  1322. return -EREMOTEIO;
  1323. }
  1324. }
  1325. if (ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP ||
  1326. ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
  1327. SLIM_INFO(ctrl, "Sending QMI power on request\n");
  1328. ret = qcom_slim_qmi_power_request(ctrl, true);
  1329. if (ret) {
  1330. SLIM_ERR(ctrl, "SLIM QMI power request failed:%d\n",
  1331. ret);
  1332. return ret;
  1333. }
  1334. }
  1335. ctrl->ver = readl_relaxed(ctrl->base);
  1336. /* Version info in 16 MSbits */
  1337. ctrl->ver >>= 16;
  1338. laddr = readl_relaxed(ngd->base + NGD_STATUS);
  1339. if (laddr & NGD_LADDR) {
  1340. /*
  1341. * external MDM restart case where ADSP itself was active framer
  1342. * For example, modem restarted when playback was active
  1343. */
  1344. if (cur_state == QCOM_SLIM_NGD_CTRL_AWAKE) {
  1345. SLIM_INFO(ctrl, "Subsys restart: ADSP active framer\n");
  1346. return 0;
  1347. }
  1348. qcom_slim_ngd_setup(ctrl);
  1349. return 0;
  1350. }
  1351. /* reinitialize it only when registers are not retained */
  1352. reinit_completion(&ctrl->reconf);
  1353. writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN);
  1354. rx_msgq = readl_relaxed(ngd->base + NGD_RX_MSGQ_CFG);
  1355. writel_relaxed(rx_msgq|SLIM_RX_MSGQ_TIMEOUT_VAL,
  1356. ngd->base + NGD_RX_MSGQ_CFG);
  1357. qcom_slim_ngd_setup(ctrl);
  1358. timeout = wait_for_completion_timeout(&ctrl->reconf, 10*HZ);
  1359. if (!timeout) {
  1360. dev_err(ctrl->dev, "capability exchange timed-out\n");
  1361. cfg = readl_relaxed(ngd->base + NGD_CFG);
  1362. laddr = readl_relaxed(ngd->base + NGD_STATUS);
  1363. SLIM_WARN(ctrl,
  1364. "slim capability time-out stat:0x%x,cfg:0x%x\n",
  1365. laddr, cfg);
  1366. return -ETIMEDOUT;
  1367. }
  1368. /* mutliple transactions waiting on slimbus to power up? */
  1369. if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
  1370. SLIM_INFO(ctrl, "ADSP slimbus power up now\n");
  1371. complete_all(&ctrl->ctrl_up);
  1372. }
  1373. return 0;
  1374. }
  1375. static void qcom_slim_ngd_notify_slaves(struct qcom_slim_ngd_ctrl *ctrl)
  1376. {
  1377. struct slim_device *sbdev;
  1378. struct device_node *node;
  1379. for_each_child_of_node(ctrl->ngd->pdev->dev.of_node, node) {
  1380. sbdev = of_slim_get_device(&ctrl->ctrl, node);
  1381. if (!sbdev)
  1382. continue;
  1383. if (slim_get_logical_addr(sbdev))
  1384. dev_err(ctrl->dev, "Failed to get logical address\n");
  1385. }
  1386. }
  1387. static void qcom_slim_ngd_master_worker(struct work_struct *work)
  1388. {
  1389. struct qcom_slim_ngd_ctrl *ctrl;
  1390. struct slim_msg_txn txn;
  1391. struct slim_val_inf msg = {0};
  1392. int retries = 0;
  1393. u8 wbuf[8];
  1394. int ret = 0;
  1395. ctrl = container_of(work, struct qcom_slim_ngd_ctrl, m_work);
  1396. txn.dt = SLIM_MSG_DEST_LOGICALADDR;
  1397. txn.ec = 0;
  1398. txn.mc = SLIM_USR_MC_REPORT_SATELLITE;
  1399. txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER;
  1400. txn.la = SLIM_LA_MGR;
  1401. wbuf[0] = SAT_MAGIC_LSB;
  1402. wbuf[1] = SAT_MAGIC_MSB;
  1403. wbuf[2] = SAT_MSG_VER;
  1404. wbuf[3] = SAT_MSG_PROT;
  1405. txn.msg = &msg;
  1406. txn.msg->wbuf = wbuf;
  1407. txn.msg->num_bytes = 4;
  1408. txn.rl = 8;
  1409. SLIM_INFO(ctrl, "SLIM SAT: Rcvd master capability\n");
  1410. capability_retry:
  1411. ret = qcom_slim_ngd_xfer_msg(&ctrl->ctrl, &txn);
  1412. if (!ret) {
  1413. SLIM_INFO(ctrl, "SLIM SAT: capability exchange successful\n");
  1414. if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
  1415. complete(&ctrl->reconf);
  1416. else
  1417. SLIM_WARN(ctrl, "capability due to noise, Unexpected state:%d\n",
  1418. ctrl->state);
  1419. if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN)
  1420. qcom_slim_ngd_notify_slaves(ctrl);
  1421. } else if (ret == -EIO) {
  1422. SLIM_WARN(ctrl, "capability message NACKed, retrying\n");
  1423. if (retries < INIT_MX_RETRIES) {
  1424. msleep(DEF_RETRY_MS);
  1425. retries++;
  1426. goto capability_retry;
  1427. }
  1428. } else {
  1429. dev_err(ctrl->dev, "SLIM: capability TX failed:%d\n", ret);
  1430. }
  1431. }
  1432. static int qcom_slim_ngd_update_device_status(struct device *dev, void *null)
  1433. {
  1434. slim_report_absent(to_slim_device(dev));
  1435. return 0;
  1436. }
  1437. static int qcom_slim_ngd_runtime_resume(struct device *dev)
  1438. {
  1439. struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
  1440. int ret = 0;
  1441. SLIM_INFO(ctrl, "Slim runtime resume\n");
  1442. mutex_lock(&ctrl->suspend_resume_lock);
  1443. if (!ctrl->qmi.handle) {
  1444. SLIM_WARN(ctrl, "%s QMI handle is NULL\n", __func__);
  1445. mutex_unlock(&ctrl->suspend_resume_lock);
  1446. return 0;
  1447. }
  1448. qcom_slim_ngd_enable_irq(ctrl);
  1449. if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
  1450. ret = qcom_slim_ngd_power_up(ctrl);
  1451. if (ret) {
  1452. /* Did SSR cause this power up failure */
  1453. if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN)
  1454. ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
  1455. else
  1456. SLIM_WARN(ctrl, "HW wakeup attempt during SSR\n");
  1457. SLIM_WARN(ctrl, "%s Power up request failed, try resume again\n",
  1458. __func__);
  1459. qcom_slim_ngd_disable_irq(ctrl);
  1460. ret = -EAGAIN;
  1461. } else {
  1462. ctrl->state = QCOM_SLIM_NGD_CTRL_AWAKE;
  1463. }
  1464. mutex_unlock(&ctrl->suspend_resume_lock);
  1465. SLIM_INFO(ctrl, "Slim runtime resume: ret %d irq_disabled %d\n",
  1466. ret, ctrl->irq_disabled);
  1467. return ret;
  1468. }
  1469. static int qcom_slim_ngd_enable(struct qcom_slim_ngd_ctrl *ctrl, bool enable)
  1470. {
  1471. if (enable) {
  1472. int ret = qcom_slim_qmi_init(ctrl, false);
  1473. if (ret) {
  1474. SLIM_ERR(ctrl, "qmi init fail, ret:%d, state:%d\n",
  1475. ret, ctrl->state);
  1476. return ret;
  1477. }
  1478. /* controller state should be in sync with framework state */
  1479. complete(&ctrl->qmi.qmi_comp);
  1480. if (!pm_runtime_enabled(ctrl->ctrl.dev) ||
  1481. !pm_runtime_suspended(ctrl->ctrl.dev))
  1482. qcom_slim_ngd_runtime_resume(ctrl->ctrl.dev);
  1483. else
  1484. pm_runtime_resume(ctrl->ctrl.dev);
  1485. pm_runtime_mark_last_busy(ctrl->ctrl.dev);
  1486. pm_runtime_put(ctrl->ctrl.dev);
  1487. SLIM_INFO(ctrl, "SLIM %s: PM put count:%d\n",
  1488. __func__, atomic_read(&ctrl->ctrl.dev->power.usage_count));
  1489. SLIM_INFO(ctrl, "SLIM NGD Enable\n");
  1490. } else {
  1491. qcom_slim_qmi_exit(ctrl);
  1492. SLIM_INFO(ctrl, "SLIM NGD Disable\n");
  1493. }
  1494. return 0;
  1495. }
  1496. static int qcom_slim_ngd_qmi_new_server(struct qmi_handle *hdl,
  1497. struct qmi_service *service)
  1498. {
  1499. struct qcom_slim_ngd_qmi *qmi =
  1500. container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
  1501. struct qcom_slim_ngd_ctrl *ctrl =
  1502. container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
  1503. SLIM_INFO(ctrl, "Slimbus QMI new server event received\n");
  1504. qmi->svc_info.sq_family = AF_QIPCRTR;
  1505. qmi->svc_info.sq_node = service->node;
  1506. qmi->svc_info.sq_port = service->port;
  1507. complete(&ctrl->qmi_up);
  1508. return 0;
  1509. }
  1510. static void qcom_slim_ngd_qmi_del_server(struct qmi_handle *hdl,
  1511. struct qmi_service *service)
  1512. {
  1513. struct qcom_slim_ngd_qmi *qmi =
  1514. container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
  1515. struct qcom_slim_ngd_ctrl *ctrl =
  1516. container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
  1517. SLIM_INFO(ctrl, "Slimbus QMI del server event received\n");
  1518. reinit_completion(&ctrl->qmi_up);
  1519. qmi->svc_info.sq_node = 0;
  1520. qmi->svc_info.sq_port = 0;
  1521. }
  1522. static const struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = {
  1523. .new_server = qcom_slim_ngd_qmi_new_server,
  1524. .del_server = qcom_slim_ngd_qmi_del_server,
  1525. };
  1526. static int qcom_slim_ngd_qmi_svc_event_init(struct qcom_slim_ngd_ctrl *ctrl)
  1527. {
  1528. struct qcom_slim_ngd_qmi *qmi = &ctrl->qmi;
  1529. int ret;
  1530. ret = qmi_handle_init(&qmi->svc_event_hdl, 0,
  1531. &qcom_slim_ngd_qmi_svc_event_ops, NULL);
  1532. if (ret < 0) {
  1533. dev_err(ctrl->dev, "qmi_handle_init failed: %d\n", ret);
  1534. return ret;
  1535. }
  1536. ret = qmi_add_lookup(&qmi->svc_event_hdl, SLIMBUS_QMI_SVC_ID,
  1537. SLIMBUS_QMI_SVC_V1, SLIMBUS_QMI_INS_ID);
  1538. if (ret < 0) {
  1539. dev_err(ctrl->dev, "qmi_add_lookup failed: %d\n", ret);
  1540. qmi_handle_release(&qmi->svc_event_hdl);
  1541. }
  1542. return ret;
  1543. }
  1544. static void qcom_slim_ngd_qmi_svc_event_deinit(struct qcom_slim_ngd_qmi *qmi)
  1545. {
  1546. qmi_handle_release(&qmi->svc_event_hdl);
  1547. }
  1548. static struct platform_driver qcom_slim_ngd_driver;
  1549. #define QCOM_SLIM_NGD_DRV_NAME "qcom,slim-ngd"
  1550. static const struct of_device_id qcom_slim_ngd_dt_match[] = {
  1551. {
  1552. .compatible = "qcom,slim-ngd-v1.5.0",
  1553. .data = &ngd_v1_5_offset_info,
  1554. },{
  1555. .compatible = "qcom,slim-ngd-v2.1.0",
  1556. .data = &ngd_v1_5_offset_info,
  1557. },
  1558. {}
  1559. };
  1560. MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match);
  1561. static void qcom_slim_ngd_down(struct qcom_slim_ngd_ctrl *ctrl)
  1562. {
  1563. mutex_lock(&ctrl->ssr_lock);
  1564. qcom_slim_ngd_enable(ctrl, false);
  1565. mutex_unlock(&ctrl->ssr_lock);
  1566. }
  1567. static void qcom_slim_ngd_up_worker(struct work_struct *work)
  1568. {
  1569. struct qcom_slim_ngd_ctrl *ctrl;
  1570. ctrl = container_of(work, struct qcom_slim_ngd_ctrl, ngd_up_work);
  1571. /* Make sure qmi service is up before continuing */
  1572. if (!wait_for_completion_interruptible_timeout(&ctrl->qmi_up,
  1573. msecs_to_jiffies(SLIM_QMI_TIMEOUT_MS))) {
  1574. SLIM_INFO(ctrl, "QMI wait timeout\n");
  1575. return;
  1576. }
  1577. mutex_lock(&ctrl->ssr_lock);
  1578. qcom_slim_ngd_enable(ctrl, true);
  1579. mutex_unlock(&ctrl->ssr_lock);
  1580. }
  1581. static int qcom_slim_ngd_ssr_pdr_notify(struct qcom_slim_ngd_ctrl *ctrl,
  1582. unsigned long action)
  1583. {
  1584. SLIM_INFO(ctrl, "SLIM DSP SSR/PDR notify cb:0x%lx\n", action);
  1585. switch (action) {
  1586. case QCOM_SSR_BEFORE_SHUTDOWN:
  1587. case SERVREG_SERVICE_STATE_DOWN:
  1588. trace_rproc_qcom_event(dev_name(ctrl->dev),
  1589. "QCOM_SSR_BEFORE_SHUTDOWN", "slim_ngd_ssr_pdr-enter");
  1590. SLIM_INFO(ctrl, "SLIM SSR Before Shutdown\n");
  1591. if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN) {
  1592. /* Make sure the last dma xfer is finished */
  1593. mutex_lock(&ctrl->suspend_resume_lock);
  1594. mutex_lock(&ctrl->tx_lock);
  1595. ctrl->state = QCOM_SLIM_NGD_CTRL_SSR_GOING_DOWN;
  1596. /*
  1597. * Mark capability_timeout to false here to handle
  1598. * BAM IRQ's from clean state.
  1599. */
  1600. ctrl->capability_timeout = false;
  1601. SLIM_INFO(ctrl, "SLIM SSR going down\n");
  1602. pm_runtime_get_noresume(ctrl->ctrl.dev);
  1603. SLIM_INFO(ctrl, "SLIM %s: PM get_no_resume count:%d\n",
  1604. __func__, atomic_read(&ctrl->ctrl.dev->power.usage_count));
  1605. device_for_each_child(ctrl->ctrl.dev, NULL,
  1606. qcom_slim_ngd_update_device_status);
  1607. qcom_slim_ngd_exit_dma(ctrl);
  1608. ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN;
  1609. SLIM_INFO(ctrl, "SLIM SSR down\n");
  1610. mutex_unlock(&ctrl->tx_lock);
  1611. mutex_unlock(&ctrl->suspend_resume_lock);
  1612. }
  1613. /* PDR must clean up everything as part of state down notification */
  1614. if (action == SERVREG_SERVICE_STATE_DOWN)
  1615. qcom_slim_ngd_down(ctrl);
  1616. break;
  1617. case QCOM_SSR_AFTER_POWERUP:
  1618. case SERVREG_SERVICE_STATE_UP:
  1619. trace_rproc_qcom_event(dev_name(ctrl->dev),
  1620. "QCOM_SSR_AFTER_POWERUP", "slim_ngd_ssr_pdr-enter");
  1621. if (ctrl->r_mem.is_r_mem) {
  1622. ctrl->r_mem.r_vbase = ctrl->r_mem.r_vsbase;
  1623. ctrl->r_mem.r_res->start = ctrl->r_mem.r_pbase;
  1624. }
  1625. schedule_work(&ctrl->ngd_up_work);
  1626. SLIM_INFO(ctrl, "SLIM SSR up\n");
  1627. break;
  1628. case QCOM_SSR_AFTER_SHUTDOWN:
  1629. SLIM_INFO(ctrl, "SLIM SSR After Shutdown\n");
  1630. qcom_slim_ngd_down(ctrl);
  1631. break;
  1632. default:
  1633. break;
  1634. }
  1635. trace_rproc_qcom_event(dev_name(ctrl->dev), "slim_ngd_ssr_pdr", "exit");
  1636. return NOTIFY_OK;
  1637. }
  1638. static int qcom_slim_ngd_ssr_notify(struct notifier_block *nb,
  1639. unsigned long action,
  1640. void *data)
  1641. {
  1642. struct qcom_slim_ngd_ctrl *ctrl = container_of(nb,
  1643. struct qcom_slim_ngd_ctrl, nb);
  1644. return qcom_slim_ngd_ssr_pdr_notify(ctrl, action);
  1645. }
  1646. static void slim_pd_status(int state, char *svc_path, void *priv)
  1647. {
  1648. struct qcom_slim_ngd_ctrl *ctrl = (struct qcom_slim_ngd_ctrl *)priv;
  1649. qcom_slim_ngd_ssr_pdr_notify(ctrl, state);
  1650. }
  1651. static int of_qcom_slim_ngd_register(struct device *parent,
  1652. struct qcom_slim_ngd_ctrl *ctrl)
  1653. {
  1654. const struct ngd_reg_offset_data *data;
  1655. struct qcom_slim_ngd *ngd;
  1656. const struct of_device_id *match;
  1657. struct device_node *node;
  1658. u32 id;
  1659. int ret;
  1660. match = of_match_node(qcom_slim_ngd_dt_match, parent->of_node);
  1661. data = match->data;
  1662. for_each_available_child_of_node(parent->of_node, node) {
  1663. if (of_property_read_u32(node, "reg", &id))
  1664. continue;
  1665. ngd = kzalloc(sizeof(*ngd), GFP_KERNEL);
  1666. if (!ngd) {
  1667. of_node_put(node);
  1668. return -ENOMEM;
  1669. }
  1670. ngd->pdev = platform_device_alloc(QCOM_SLIM_NGD_DRV_NAME, id);
  1671. if (!ngd->pdev) {
  1672. kfree(ngd);
  1673. of_node_put(node);
  1674. return -ENOMEM;
  1675. }
  1676. ngd->id = id;
  1677. ngd->pdev->dev.parent = parent;
  1678. ret = driver_set_override(&ngd->pdev->dev,
  1679. &ngd->pdev->driver_override,
  1680. QCOM_SLIM_NGD_DRV_NAME,
  1681. strlen(QCOM_SLIM_NGD_DRV_NAME));
  1682. if (ret) {
  1683. platform_device_put(ngd->pdev);
  1684. kfree(ngd);
  1685. of_node_put(node);
  1686. return ret;
  1687. }
  1688. ngd->pdev->dev.of_node = node;
  1689. ctrl->ngd = ngd;
  1690. ret = platform_device_add(ngd->pdev);
  1691. if (ret) {
  1692. platform_device_put(ngd->pdev);
  1693. kfree(ngd);
  1694. of_node_put(node);
  1695. return ret;
  1696. }
  1697. ngd->base = ctrl->base + ngd->id * data->offset +
  1698. (ngd->id - 1) * data->size;
  1699. return 0;
  1700. }
  1701. return -ENODEV;
  1702. }
  1703. static ssize_t debug_mask_show(struct device *device,
  1704. struct device_attribute *attr,
  1705. char *buf)
  1706. {
  1707. struct platform_device *pdev = to_platform_device(device);
  1708. struct qcom_slim_ngd_ctrl *dev = platform_get_drvdata(pdev);
  1709. return scnprintf(buf, sizeof(int), "%u\n", dev->ipc_log_mask);
  1710. }
  1711. static ssize_t debug_mask_store(struct device *device,
  1712. struct device_attribute *attr,
  1713. const char *buf, size_t count)
  1714. {
  1715. struct platform_device *pdev = to_platform_device(device);
  1716. struct qcom_slim_ngd_ctrl *dev = platform_get_drvdata(pdev);
  1717. dev->ipc_log_mask = buf[0] - '0';
  1718. if (dev->ipc_log_mask > DBG_LEV)
  1719. dev->ipc_log_mask = DBG_LEV;
  1720. return count;
  1721. }
  1722. static DEVICE_ATTR_RW(debug_mask);
  1723. static int qcom_slim_ngd_probe(struct platform_device *pdev)
  1724. {
  1725. struct device *dev = &pdev->dev;
  1726. struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev->parent);
  1727. int ret;
  1728. ctrl->ctrl.dev = dev;
  1729. ret = slim_register_controller(&ctrl->ctrl);
  1730. if (ret) {
  1731. dev_err(dev, "error adding slim controller\n");
  1732. return ret;
  1733. }
  1734. platform_set_drvdata(pdev, ctrl);
  1735. pm_runtime_use_autosuspend(dev);
  1736. pm_runtime_set_autosuspend_delay(dev, QCOM_SLIM_NGD_AUTOSUSPEND);
  1737. pm_runtime_set_suspended(dev);
  1738. pm_runtime_enable(dev);
  1739. pm_runtime_get_noresume(dev);
  1740. SLIM_INFO(ctrl, "SLIM %s:PM get_noresume count:%d\n", __func__,
  1741. atomic_read(&ctrl->ctrl.dev->power.usage_count));
  1742. INIT_WORK(&ctrl->m_work, qcom_slim_ngd_master_worker);
  1743. INIT_WORK(&ctrl->ngd_up_work, qcom_slim_ngd_up_worker);
  1744. ctrl->mwq = create_singlethread_workqueue("ngd_master");
  1745. if (!ctrl->mwq) {
  1746. dev_err(&pdev->dev, "Failed to start master worker\n");
  1747. ret = -ENOMEM;
  1748. goto wq_err;
  1749. }
  1750. ret = qcom_slim_ngd_qmi_svc_event_init(ctrl);
  1751. if (ret) {
  1752. dev_err(&pdev->dev,
  1753. "QMI service registration failed:%d\n", ret);
  1754. goto err;
  1755. }
  1756. return 0;
  1757. wq_err:
  1758. qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
  1759. if (ctrl->mwq)
  1760. destroy_workqueue(ctrl->mwq);
  1761. err:
  1762. slim_unregister_controller(&ctrl->ctrl);
  1763. return ret;
  1764. }
  1765. static int qcom_slim_ngd_ctrl_probe(struct platform_device *pdev)
  1766. {
  1767. struct device *dev = &pdev->dev;
  1768. struct qcom_slim_ngd_ctrl *ctrl;
  1769. struct resource *res, *remote_res;
  1770. char ipc_err_log_name[30];
  1771. int ret;
  1772. struct pdr_service *pds;
  1773. ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
  1774. if (!ctrl)
  1775. return -ENOMEM;
  1776. dev_set_drvdata(dev, ctrl);
  1777. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1778. ctrl->base = devm_ioremap_resource(dev, res);
  1779. if (IS_ERR(ctrl->base))
  1780. return PTR_ERR(ctrl->base);
  1781. ret = platform_get_irq(pdev, 0);
  1782. if (ret < 0)
  1783. return ret;
  1784. ctrl->irq = ret;
  1785. ret = devm_request_irq(dev, ctrl->irq, qcom_slim_ngd_interrupt,
  1786. IRQF_TRIGGER_HIGH, "slim-ngd", ctrl);
  1787. if (ret)
  1788. return dev_err_probe(&pdev->dev, ret, "request IRQ failed\n");
  1789. ctrl->irq_disabled = false;
  1790. ctrl->r_mem.is_r_mem = false;
  1791. remote_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1792. "slimbus_remote_mem");
  1793. ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  1794. if (ret) {
  1795. dev_err(&pdev->dev, "could not set 32 bit mask\n");
  1796. return -ENODEV;
  1797. }
  1798. if (remote_res) {
  1799. ctrl->r_mem.is_r_mem = true;
  1800. ctrl->r_mem.r_pbase = (unsigned long long)remote_res->start;
  1801. ctrl->r_mem.r_vbase = devm_ioremap(&pdev->dev,
  1802. remote_res->start, resource_size(remote_res));
  1803. if (!ctrl->r_mem.r_vbase) {
  1804. dev_err(&pdev->dev, "Remote mem ioremap failed\n");
  1805. return -ENOMEM;
  1806. }
  1807. ctrl->r_mem.r_vsbase = ctrl->r_mem.r_vbase;
  1808. ctrl->r_mem.r_res = remote_res;
  1809. } else {
  1810. dev_err(&pdev->dev, "no Remote mem\n");
  1811. }
  1812. ctrl->wait_for_adsp_up = of_property_read_bool(pdev->dev.of_node,
  1813. "qcom,wait_for_adsp_up");
  1814. /* Create IPC log context */
  1815. ctrl->ipc_slimbus_log = ipc_log_context_create(IPC_SLIMBUS_LOG_PAGES,
  1816. dev_name(&pdev->dev), 0);
  1817. if (!ctrl->ipc_slimbus_log) {
  1818. dev_err(&pdev->dev, "error creating ipc_logging context\n");
  1819. } else {
  1820. /* Initialize the log mask */
  1821. ctrl->ipc_log_mask = INFO_LEV;
  1822. ctrl->default_ipc_log_mask = INFO_LEV;
  1823. SLIM_INFO(ctrl, "start logging for slim dev %s\n",
  1824. dev_name(&pdev->dev));
  1825. }
  1826. /* Create Error IPC log context */
  1827. memset(ipc_err_log_name, 0, sizeof(ipc_err_log_name));
  1828. scnprintf(ipc_err_log_name, sizeof(ipc_err_log_name), "%s%s",
  1829. dev_name(&pdev->dev), "_err");
  1830. ctrl->ipc_slimbus_log_err =
  1831. ipc_log_context_create(IPC_SLIMBUS_LOG_PAGES,
  1832. ipc_err_log_name, 0);
  1833. if (!ctrl->ipc_slimbus_log_err)
  1834. dev_err(&pdev->dev,
  1835. "error creating ipc_error_logging context\n");
  1836. else
  1837. SLIM_INFO(ctrl, "start error logging for slim dev %s\n",
  1838. ipc_err_log_name);
  1839. ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_debug_mask.attr);
  1840. if (ret) {
  1841. dev_err(&pdev->dev, "Failed to create sysfs ret:%d\n", ret);
  1842. ctrl->sysfs_created = false;
  1843. } else {
  1844. ctrl->sysfs_created = true;
  1845. }
  1846. ctrl->nb.notifier_call = qcom_slim_ngd_ssr_notify;
  1847. ctrl->notifier = qcom_register_ssr_notifier("lpass", &ctrl->nb);
  1848. if (IS_ERR(ctrl->notifier)) {
  1849. ret = PTR_ERR(ctrl->notifier);
  1850. dev_err(dev, "Failed to register SSR notification: %d\n", ret);
  1851. goto remove_ipc_sysfs;
  1852. }
  1853. ctrl->dev = dev;
  1854. ctrl->framer.rootfreq = SLIM_ROOT_FREQ >> 3;
  1855. ctrl->framer.superfreq =
  1856. ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
  1857. ctrl->ctrl.a_framer = &ctrl->framer;
  1858. ctrl->ctrl.clkgear = SLIM_MAX_CLK_GEAR;
  1859. ctrl->ctrl.get_laddr = qcom_slim_ngd_get_laddr;
  1860. ctrl->ctrl.suspend_slimbus = qcom_ngd_set_suspend;
  1861. ctrl->ctrl.enable_stream = qcom_slim_ngd_enable_stream;
  1862. ctrl->ctrl.disable_stream = qcom_slim_ngd_disable_stream;
  1863. ctrl->ctrl.xfer_msg = qcom_slim_ngd_xfer_msg;
  1864. ctrl->ctrl.wakeup = NULL;
  1865. ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN;
  1866. mutex_init(&ctrl->tx_lock);
  1867. mutex_init(&ctrl->suspend_resume_lock);
  1868. mutex_init(&ctrl->ssr_lock);
  1869. mutex_init(&ctrl->qmi_handle_lock);
  1870. spin_lock_init(&ctrl->tx_buf_lock);
  1871. init_completion(&ctrl->reconf);
  1872. init_completion(&ctrl->ctrl_up);
  1873. init_completion(&ctrl->qmi.qmi_comp);
  1874. init_completion(&ctrl->qmi_up);
  1875. init_completion(&ctrl->xfer_done);
  1876. init_completion(&ctrl->sync_done);
  1877. ctrl->pdr = pdr_handle_alloc(slim_pd_status, ctrl);
  1878. if (IS_ERR(ctrl->pdr)) {
  1879. ret = dev_err_probe(dev, PTR_ERR(ctrl->pdr),
  1880. "Failed to init PDR handle: %d\n", ret);
  1881. goto err_pdr_alloc;
  1882. }
  1883. pds = pdr_add_lookup(ctrl->pdr, "avs/audio", "msm/adsp/audio_pd");
  1884. if (IS_ERR(pds) && PTR_ERR(pds) != -EALREADY) {
  1885. ret = dev_err_probe(dev, PTR_ERR(pds), "pdr add lookup failed: %d\n", ret);
  1886. goto err_pdr_lookup;
  1887. }
  1888. ret = of_qcom_slim_ngd_register(dev, ctrl);
  1889. if (ret) {
  1890. SLIM_ERR(ctrl, "qcom_slim_ngd_register failed ret:%d\n", ret);
  1891. goto err_pdr_lookup;
  1892. }
  1893. platform_driver_register(&qcom_slim_ngd_driver);
  1894. SLIM_INFO(ctrl, "NGD SB controller is up!\n");
  1895. return 0;
  1896. err_pdr_lookup:
  1897. pdr_handle_release(ctrl->pdr);
  1898. err_pdr_alloc:
  1899. qcom_unregister_ssr_notifier(ctrl->notifier, &ctrl->nb);
  1900. remove_ipc_sysfs:
  1901. if (ctrl->ipc_slimbus_log)
  1902. ipc_log_context_destroy(ctrl->ipc_slimbus_log);
  1903. if (ctrl->sysfs_created)
  1904. sysfs_remove_file(&pdev->dev.kobj,
  1905. &dev_attr_debug_mask.attr);
  1906. return ret;
  1907. }
  1908. static int qcom_slim_ngd_ctrl_remove(struct platform_device *pdev)
  1909. {
  1910. struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev);
  1911. platform_driver_unregister(&qcom_slim_ngd_driver);
  1912. if (ctrl->sysfs_created)
  1913. sysfs_remove_file(&pdev->dev.kobj,
  1914. &dev_attr_debug_mask.attr);
  1915. ipc_log_context_destroy(ctrl->ipc_slimbus_log);
  1916. ctrl->ipc_slimbus_log = NULL;
  1917. return 0;
  1918. }
  1919. static int qcom_slim_ngd_remove(struct platform_device *pdev)
  1920. {
  1921. struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev);
  1922. pm_runtime_disable(&pdev->dev);
  1923. pdr_handle_release(ctrl->pdr);
  1924. qcom_unregister_ssr_notifier(ctrl->notifier, &ctrl->nb);
  1925. slim_unregister_controller(&ctrl->ctrl);
  1926. qcom_slim_ngd_exit_dma(ctrl);
  1927. qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
  1928. if (ctrl->mwq)
  1929. destroy_workqueue(ctrl->mwq);
  1930. kfree(ctrl->ngd);
  1931. ctrl->ngd = NULL;
  1932. return 0;
  1933. }
  1934. static int __maybe_unused qcom_slim_ngd_runtime_idle(struct device *dev)
  1935. {
  1936. struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
  1937. if (ctrl->state == QCOM_SLIM_NGD_CTRL_AWAKE)
  1938. ctrl->state = QCOM_SLIM_NGD_CTRL_IDLE;
  1939. SLIM_DBG(ctrl, "pm_runtime: idle...\n");
  1940. pm_request_autosuspend(dev);
  1941. return -EAGAIN;
  1942. }
  1943. static int __maybe_unused qcom_slim_ngd_runtime_suspend(struct device *dev)
  1944. {
  1945. struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
  1946. struct qcom_slim_ngd *ngd = ctrl->ngd;
  1947. int ret = 0;
  1948. SLIM_INFO(ctrl, "Slim runtime suspend\n");
  1949. /*
  1950. * Need reset dma for every suspend/resume to have a clean
  1951. * HW reset on remote slimbus side.
  1952. */
  1953. mutex_lock(&ctrl->suspend_resume_lock);
  1954. if (!ctrl->qmi.handle) {
  1955. SLIM_WARN(ctrl, "%s QMI handle is NULL\n", __func__);
  1956. mutex_unlock(&ctrl->suspend_resume_lock);
  1957. return 0;
  1958. }
  1959. qcom_slim_ngd_exit_dma(ctrl);
  1960. qcom_slim_ngd_disable_irq(ctrl);
  1961. writel_relaxed(0x0, ngd->base + NGD_INT_EN);
  1962. SLIM_INFO(ctrl, "Sending QMI power off request\n");
  1963. ret = qcom_slim_qmi_power_request(ctrl, false);
  1964. if (ret && ret != -EBUSY)
  1965. SLIM_INFO(ctrl, "slim resource not idle:%d\n", ret);
  1966. if (!ret || ret == -ETIMEDOUT)
  1967. ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
  1968. mutex_unlock(&ctrl->suspend_resume_lock);
  1969. SLIM_INFO(ctrl, "Slim runtime suspend: ret %d irq_disabled %d\n",
  1970. ret, ctrl->irq_disabled);
  1971. return ret;
  1972. }
  1973. static const struct dev_pm_ops qcom_slim_ngd_dev_pm_ops = {
  1974. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1975. pm_runtime_force_resume)
  1976. SET_RUNTIME_PM_OPS(
  1977. qcom_slim_ngd_runtime_suspend,
  1978. qcom_slim_ngd_runtime_resume,
  1979. qcom_slim_ngd_runtime_idle
  1980. )
  1981. };
  1982. static struct platform_driver qcom_slim_ngd_ctrl_driver = {
  1983. .probe = qcom_slim_ngd_ctrl_probe,
  1984. .remove = qcom_slim_ngd_ctrl_remove,
  1985. .driver = {
  1986. .name = "qcom,slim-ngd-ctrl",
  1987. .of_match_table = qcom_slim_ngd_dt_match,
  1988. },
  1989. };
  1990. static struct platform_driver qcom_slim_ngd_driver = {
  1991. .probe = qcom_slim_ngd_probe,
  1992. .remove = qcom_slim_ngd_remove,
  1993. .driver = {
  1994. .name = QCOM_SLIM_NGD_DRV_NAME,
  1995. .pm = &qcom_slim_ngd_dev_pm_ops,
  1996. },
  1997. };
  1998. module_platform_driver(qcom_slim_ngd_ctrl_driver);
  1999. MODULE_LICENSE("GPL v2");
  2000. MODULE_DESCRIPTION("Qualcomm SLIMBus NGD controller");