ql4_nx.c 114 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * QLogic iSCSI HBA Driver
  4. * Copyright (c) 2003-2013 QLogic Corporation
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/io.h>
  8. #include <linux/pci.h>
  9. #include <linux/ratelimit.h>
  10. #include "ql4_def.h"
  11. #include "ql4_glbl.h"
  12. #include "ql4_inline.h"
  13. #include <linux/io-64-nonatomic-lo-hi.h>
  14. #define TIMEOUT_100_MS 100
  15. #define MASK(n) DMA_BIT_MASK(n)
  16. #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
  17. #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
  18. #define MS_WIN(addr) (addr & 0x0ffc0000)
  19. #define QLA82XX_PCI_MN_2M (0)
  20. #define QLA82XX_PCI_MS_2M (0x80000)
  21. #define QLA82XX_PCI_OCM0_2M (0xc0000)
  22. #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
  23. #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  24. /* CRB window related */
  25. #define CRB_BLK(off) ((off >> 20) & 0x3f)
  26. #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  27. #define CRB_WINDOW_2M (0x130060)
  28. #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  29. ((off) & 0xf0000))
  30. #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
  31. #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
  32. #define CRB_INDIRECT_2M (0x1e0000UL)
  33. static inline void __iomem *
  34. qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
  35. {
  36. if ((off < ha->first_page_group_end) &&
  37. (off >= ha->first_page_group_start))
  38. return (void __iomem *)(ha->nx_pcibase + off);
  39. return NULL;
  40. }
  41. static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8,
  42. 0x410000AC, 0x410000B8, 0x410000BC };
  43. #define MAX_CRB_XFORM 60
  44. static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  45. static int qla4_8xxx_crb_table_initialized;
  46. #define qla4_8xxx_crb_addr_transform(name) \
  47. (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  48. QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  49. static void
  50. qla4_82xx_crb_addr_transform_setup(void)
  51. {
  52. qla4_8xxx_crb_addr_transform(XDMA);
  53. qla4_8xxx_crb_addr_transform(TIMR);
  54. qla4_8xxx_crb_addr_transform(SRE);
  55. qla4_8xxx_crb_addr_transform(SQN3);
  56. qla4_8xxx_crb_addr_transform(SQN2);
  57. qla4_8xxx_crb_addr_transform(SQN1);
  58. qla4_8xxx_crb_addr_transform(SQN0);
  59. qla4_8xxx_crb_addr_transform(SQS3);
  60. qla4_8xxx_crb_addr_transform(SQS2);
  61. qla4_8xxx_crb_addr_transform(SQS1);
  62. qla4_8xxx_crb_addr_transform(SQS0);
  63. qla4_8xxx_crb_addr_transform(RPMX7);
  64. qla4_8xxx_crb_addr_transform(RPMX6);
  65. qla4_8xxx_crb_addr_transform(RPMX5);
  66. qla4_8xxx_crb_addr_transform(RPMX4);
  67. qla4_8xxx_crb_addr_transform(RPMX3);
  68. qla4_8xxx_crb_addr_transform(RPMX2);
  69. qla4_8xxx_crb_addr_transform(RPMX1);
  70. qla4_8xxx_crb_addr_transform(RPMX0);
  71. qla4_8xxx_crb_addr_transform(ROMUSB);
  72. qla4_8xxx_crb_addr_transform(SN);
  73. qla4_8xxx_crb_addr_transform(QMN);
  74. qla4_8xxx_crb_addr_transform(QMS);
  75. qla4_8xxx_crb_addr_transform(PGNI);
  76. qla4_8xxx_crb_addr_transform(PGND);
  77. qla4_8xxx_crb_addr_transform(PGN3);
  78. qla4_8xxx_crb_addr_transform(PGN2);
  79. qla4_8xxx_crb_addr_transform(PGN1);
  80. qla4_8xxx_crb_addr_transform(PGN0);
  81. qla4_8xxx_crb_addr_transform(PGSI);
  82. qla4_8xxx_crb_addr_transform(PGSD);
  83. qla4_8xxx_crb_addr_transform(PGS3);
  84. qla4_8xxx_crb_addr_transform(PGS2);
  85. qla4_8xxx_crb_addr_transform(PGS1);
  86. qla4_8xxx_crb_addr_transform(PGS0);
  87. qla4_8xxx_crb_addr_transform(PS);
  88. qla4_8xxx_crb_addr_transform(PH);
  89. qla4_8xxx_crb_addr_transform(NIU);
  90. qla4_8xxx_crb_addr_transform(I2Q);
  91. qla4_8xxx_crb_addr_transform(EG);
  92. qla4_8xxx_crb_addr_transform(MN);
  93. qla4_8xxx_crb_addr_transform(MS);
  94. qla4_8xxx_crb_addr_transform(CAS2);
  95. qla4_8xxx_crb_addr_transform(CAS1);
  96. qla4_8xxx_crb_addr_transform(CAS0);
  97. qla4_8xxx_crb_addr_transform(CAM);
  98. qla4_8xxx_crb_addr_transform(C2C1);
  99. qla4_8xxx_crb_addr_transform(C2C0);
  100. qla4_8xxx_crb_addr_transform(SMB);
  101. qla4_8xxx_crb_addr_transform(OCM0);
  102. qla4_8xxx_crb_addr_transform(I2C0);
  103. qla4_8xxx_crb_table_initialized = 1;
  104. }
  105. static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
  106. {{{0, 0, 0, 0} } }, /* 0: PCI */
  107. {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
  108. {1, 0x0110000, 0x0120000, 0x130000},
  109. {1, 0x0120000, 0x0122000, 0x124000},
  110. {1, 0x0130000, 0x0132000, 0x126000},
  111. {1, 0x0140000, 0x0142000, 0x128000},
  112. {1, 0x0150000, 0x0152000, 0x12a000},
  113. {1, 0x0160000, 0x0170000, 0x110000},
  114. {1, 0x0170000, 0x0172000, 0x12e000},
  115. {0, 0x0000000, 0x0000000, 0x000000},
  116. {0, 0x0000000, 0x0000000, 0x000000},
  117. {0, 0x0000000, 0x0000000, 0x000000},
  118. {0, 0x0000000, 0x0000000, 0x000000},
  119. {0, 0x0000000, 0x0000000, 0x000000},
  120. {0, 0x0000000, 0x0000000, 0x000000},
  121. {1, 0x01e0000, 0x01e0800, 0x122000},
  122. {0, 0x0000000, 0x0000000, 0x000000} } },
  123. {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  124. {{{0, 0, 0, 0} } }, /* 3: */
  125. {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  126. {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
  127. {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
  128. {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
  129. {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
  130. {0, 0x0000000, 0x0000000, 0x000000},
  131. {0, 0x0000000, 0x0000000, 0x000000},
  132. {0, 0x0000000, 0x0000000, 0x000000},
  133. {0, 0x0000000, 0x0000000, 0x000000},
  134. {0, 0x0000000, 0x0000000, 0x000000},
  135. {0, 0x0000000, 0x0000000, 0x000000},
  136. {0, 0x0000000, 0x0000000, 0x000000},
  137. {0, 0x0000000, 0x0000000, 0x000000},
  138. {0, 0x0000000, 0x0000000, 0x000000},
  139. {0, 0x0000000, 0x0000000, 0x000000},
  140. {0, 0x0000000, 0x0000000, 0x000000},
  141. {0, 0x0000000, 0x0000000, 0x000000},
  142. {0, 0x0000000, 0x0000000, 0x000000},
  143. {0, 0x0000000, 0x0000000, 0x000000},
  144. {1, 0x08f0000, 0x08f2000, 0x172000} } },
  145. {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
  146. {0, 0x0000000, 0x0000000, 0x000000},
  147. {0, 0x0000000, 0x0000000, 0x000000},
  148. {0, 0x0000000, 0x0000000, 0x000000},
  149. {0, 0x0000000, 0x0000000, 0x000000},
  150. {0, 0x0000000, 0x0000000, 0x000000},
  151. {0, 0x0000000, 0x0000000, 0x000000},
  152. {0, 0x0000000, 0x0000000, 0x000000},
  153. {0, 0x0000000, 0x0000000, 0x000000},
  154. {0, 0x0000000, 0x0000000, 0x000000},
  155. {0, 0x0000000, 0x0000000, 0x000000},
  156. {0, 0x0000000, 0x0000000, 0x000000},
  157. {0, 0x0000000, 0x0000000, 0x000000},
  158. {0, 0x0000000, 0x0000000, 0x000000},
  159. {0, 0x0000000, 0x0000000, 0x000000},
  160. {1, 0x09f0000, 0x09f2000, 0x176000} } },
  161. {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
  162. {0, 0x0000000, 0x0000000, 0x000000},
  163. {0, 0x0000000, 0x0000000, 0x000000},
  164. {0, 0x0000000, 0x0000000, 0x000000},
  165. {0, 0x0000000, 0x0000000, 0x000000},
  166. {0, 0x0000000, 0x0000000, 0x000000},
  167. {0, 0x0000000, 0x0000000, 0x000000},
  168. {0, 0x0000000, 0x0000000, 0x000000},
  169. {0, 0x0000000, 0x0000000, 0x000000},
  170. {0, 0x0000000, 0x0000000, 0x000000},
  171. {0, 0x0000000, 0x0000000, 0x000000},
  172. {0, 0x0000000, 0x0000000, 0x000000},
  173. {0, 0x0000000, 0x0000000, 0x000000},
  174. {0, 0x0000000, 0x0000000, 0x000000},
  175. {0, 0x0000000, 0x0000000, 0x000000},
  176. {1, 0x0af0000, 0x0af2000, 0x17a000} } },
  177. {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
  178. {0, 0x0000000, 0x0000000, 0x000000},
  179. {0, 0x0000000, 0x0000000, 0x000000},
  180. {0, 0x0000000, 0x0000000, 0x000000},
  181. {0, 0x0000000, 0x0000000, 0x000000},
  182. {0, 0x0000000, 0x0000000, 0x000000},
  183. {0, 0x0000000, 0x0000000, 0x000000},
  184. {0, 0x0000000, 0x0000000, 0x000000},
  185. {0, 0x0000000, 0x0000000, 0x000000},
  186. {0, 0x0000000, 0x0000000, 0x000000},
  187. {0, 0x0000000, 0x0000000, 0x000000},
  188. {0, 0x0000000, 0x0000000, 0x000000},
  189. {0, 0x0000000, 0x0000000, 0x000000},
  190. {0, 0x0000000, 0x0000000, 0x000000},
  191. {0, 0x0000000, 0x0000000, 0x000000},
  192. {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
  193. {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
  194. {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
  195. {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
  196. {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
  197. {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
  198. {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
  199. {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
  200. {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
  201. {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
  202. {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
  203. {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
  204. {{{0, 0, 0, 0} } }, /* 23: */
  205. {{{0, 0, 0, 0} } }, /* 24: */
  206. {{{0, 0, 0, 0} } }, /* 25: */
  207. {{{0, 0, 0, 0} } }, /* 26: */
  208. {{{0, 0, 0, 0} } }, /* 27: */
  209. {{{0, 0, 0, 0} } }, /* 28: */
  210. {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
  211. {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
  212. {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
  213. {{{0} } }, /* 32: PCI */
  214. {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
  215. {1, 0x2110000, 0x2120000, 0x130000},
  216. {1, 0x2120000, 0x2122000, 0x124000},
  217. {1, 0x2130000, 0x2132000, 0x126000},
  218. {1, 0x2140000, 0x2142000, 0x128000},
  219. {1, 0x2150000, 0x2152000, 0x12a000},
  220. {1, 0x2160000, 0x2170000, 0x110000},
  221. {1, 0x2170000, 0x2172000, 0x12e000},
  222. {0, 0x0000000, 0x0000000, 0x000000},
  223. {0, 0x0000000, 0x0000000, 0x000000},
  224. {0, 0x0000000, 0x0000000, 0x000000},
  225. {0, 0x0000000, 0x0000000, 0x000000},
  226. {0, 0x0000000, 0x0000000, 0x000000},
  227. {0, 0x0000000, 0x0000000, 0x000000},
  228. {0, 0x0000000, 0x0000000, 0x000000},
  229. {0, 0x0000000, 0x0000000, 0x000000} } },
  230. {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
  231. {{{0} } }, /* 35: */
  232. {{{0} } }, /* 36: */
  233. {{{0} } }, /* 37: */
  234. {{{0} } }, /* 38: */
  235. {{{0} } }, /* 39: */
  236. {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
  237. {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
  238. {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
  239. {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
  240. {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
  241. {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
  242. {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
  243. {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
  244. {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
  245. {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
  246. {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
  247. {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
  248. {{{0} } }, /* 52: */
  249. {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
  250. {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
  251. {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
  252. {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
  253. {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
  254. {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
  255. {{{0} } }, /* 59: I2C0 */
  256. {{{0} } }, /* 60: I2C1 */
  257. {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
  258. {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
  259. {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
  260. };
  261. /*
  262. * top 12 bits of crb internal address (hub, agent)
  263. */
  264. static unsigned qla4_82xx_crb_hub_agt[64] = {
  265. 0,
  266. QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
  267. QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
  268. QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
  269. 0,
  270. QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
  271. QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
  272. QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
  273. QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
  274. QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
  275. QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
  276. QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
  277. QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
  278. QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
  279. QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
  280. QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
  281. QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
  282. QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
  283. QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
  284. QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
  285. QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
  286. QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
  287. QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
  288. QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
  289. QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
  290. QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
  291. QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
  292. 0,
  293. QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
  294. QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
  295. 0,
  296. QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
  297. 0,
  298. QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
  299. QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
  300. 0,
  301. 0,
  302. 0,
  303. 0,
  304. 0,
  305. QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
  306. 0,
  307. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
  308. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
  309. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
  310. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
  311. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
  312. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
  313. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
  314. QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
  315. QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
  316. QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
  317. 0,
  318. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
  319. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
  320. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
  321. QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
  322. 0,
  323. QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
  324. QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
  325. QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
  326. 0,
  327. QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
  328. 0,
  329. };
  330. /* Device states */
  331. static char *qdev_state[] = {
  332. "Unknown",
  333. "Cold",
  334. "Initializing",
  335. "Ready",
  336. "Need Reset",
  337. "Need Quiescent",
  338. "Failed",
  339. "Quiescent",
  340. };
  341. /*
  342. * In: 'off' is offset from CRB space in 128M pci map
  343. * Out: 'off' is 2M pci map addr
  344. * side effect: lock crb window
  345. */
  346. static void
  347. qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
  348. {
  349. u32 win_read;
  350. ha->crb_win = CRB_HI(*off);
  351. writel(ha->crb_win,
  352. (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  353. /* Read back value to make sure write has gone through before trying
  354. * to use it. */
  355. win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  356. if (win_read != ha->crb_win) {
  357. DEBUG2(ql4_printk(KERN_INFO, ha,
  358. "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
  359. " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
  360. }
  361. *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
  362. }
  363. #define CRB_WIN_LOCK_TIMEOUT 100000000
  364. /*
  365. * Context: atomic
  366. */
  367. static int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
  368. {
  369. int done = 0, timeout = 0;
  370. while (!done) {
  371. /* acquire semaphore3 from PCI HW block */
  372. done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
  373. if (done == 1)
  374. break;
  375. if (timeout >= CRB_WIN_LOCK_TIMEOUT)
  376. return -1;
  377. timeout++;
  378. udelay(10);
  379. }
  380. qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
  381. return 0;
  382. }
  383. void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
  384. {
  385. qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
  386. }
  387. void
  388. qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
  389. {
  390. unsigned long flags = 0;
  391. int rv;
  392. rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
  393. BUG_ON(rv == -1);
  394. if (rv == 1) {
  395. write_lock_irqsave(&ha->hw_lock, flags);
  396. qla4_82xx_crb_win_lock(ha);
  397. qla4_82xx_pci_set_crbwindow_2M(ha, &off);
  398. }
  399. writel(data, (void __iomem *)off);
  400. if (rv == 1) {
  401. qla4_82xx_crb_win_unlock(ha);
  402. write_unlock_irqrestore(&ha->hw_lock, flags);
  403. }
  404. }
  405. uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
  406. {
  407. unsigned long flags = 0;
  408. int rv;
  409. u32 data;
  410. rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
  411. BUG_ON(rv == -1);
  412. if (rv == 1) {
  413. write_lock_irqsave(&ha->hw_lock, flags);
  414. qla4_82xx_crb_win_lock(ha);
  415. qla4_82xx_pci_set_crbwindow_2M(ha, &off);
  416. }
  417. data = readl((void __iomem *)off);
  418. if (rv == 1) {
  419. qla4_82xx_crb_win_unlock(ha);
  420. write_unlock_irqrestore(&ha->hw_lock, flags);
  421. }
  422. return data;
  423. }
  424. /* Minidump related functions */
  425. int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
  426. {
  427. uint32_t win_read, off_value;
  428. int rval = QLA_SUCCESS;
  429. off_value = off & 0xFFFF0000;
  430. writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  431. /*
  432. * Read back value to make sure write has gone through before trying
  433. * to use it.
  434. */
  435. win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  436. if (win_read != off_value) {
  437. DEBUG2(ql4_printk(KERN_INFO, ha,
  438. "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
  439. __func__, off_value, win_read, off));
  440. rval = QLA_ERROR;
  441. } else {
  442. off_value = off & 0x0000FFFF;
  443. *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
  444. ha->nx_pcibase));
  445. }
  446. return rval;
  447. }
  448. int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
  449. {
  450. uint32_t win_read, off_value;
  451. int rval = QLA_SUCCESS;
  452. off_value = off & 0xFFFF0000;
  453. writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  454. /* Read back value to make sure write has gone through before trying
  455. * to use it.
  456. */
  457. win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  458. if (win_read != off_value) {
  459. DEBUG2(ql4_printk(KERN_INFO, ha,
  460. "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
  461. __func__, off_value, win_read, off));
  462. rval = QLA_ERROR;
  463. } else {
  464. off_value = off & 0x0000FFFF;
  465. writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
  466. ha->nx_pcibase));
  467. }
  468. return rval;
  469. }
  470. #define IDC_LOCK_TIMEOUT 100000000
  471. /**
  472. * qla4_82xx_idc_lock - hw_lock
  473. * @ha: pointer to adapter structure
  474. *
  475. * General purpose lock used to synchronize access to
  476. * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
  477. *
  478. * Context: task, can sleep
  479. **/
  480. int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
  481. {
  482. int done = 0, timeout = 0;
  483. might_sleep();
  484. while (!done) {
  485. /* acquire semaphore5 from PCI HW block */
  486. done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
  487. if (done == 1)
  488. break;
  489. if (timeout >= IDC_LOCK_TIMEOUT)
  490. return -1;
  491. timeout++;
  492. msleep(100);
  493. }
  494. return 0;
  495. }
  496. void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
  497. {
  498. qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
  499. }
  500. int
  501. qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
  502. {
  503. struct crb_128M_2M_sub_block_map *m;
  504. if (*off >= QLA82XX_CRB_MAX)
  505. return -1;
  506. if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
  507. *off = (*off - QLA82XX_PCI_CAMQM) +
  508. QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
  509. return 0;
  510. }
  511. if (*off < QLA82XX_PCI_CRBSPACE)
  512. return -1;
  513. *off -= QLA82XX_PCI_CRBSPACE;
  514. /*
  515. * Try direct map
  516. */
  517. m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
  518. if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
  519. *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
  520. return 0;
  521. }
  522. /*
  523. * Not in direct map, use crb window
  524. */
  525. return 1;
  526. }
  527. /*
  528. * check memory access boundary.
  529. * used by test agent. support ddr access only for now
  530. */
  531. static unsigned long
  532. qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
  533. unsigned long long addr, int size)
  534. {
  535. if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
  536. QLA8XXX_ADDR_DDR_NET_MAX) ||
  537. !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
  538. QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
  539. ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
  540. return 0;
  541. }
  542. return 1;
  543. }
  544. static int qla4_82xx_pci_set_window_warning_count;
  545. static unsigned long
  546. qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
  547. {
  548. int window;
  549. u32 win_read;
  550. if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
  551. QLA8XXX_ADDR_DDR_NET_MAX)) {
  552. /* DDR network side */
  553. window = MN_WIN(addr);
  554. ha->ddr_mn_window = window;
  555. qla4_82xx_wr_32(ha, ha->mn_win_crb |
  556. QLA82XX_PCI_CRBSPACE, window);
  557. win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
  558. QLA82XX_PCI_CRBSPACE);
  559. if ((win_read << 17) != window) {
  560. ql4_printk(KERN_WARNING, ha,
  561. "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
  562. __func__, window, win_read);
  563. }
  564. addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
  565. } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
  566. QLA8XXX_ADDR_OCM0_MAX)) {
  567. unsigned int temp1;
  568. /* if bits 19:18&17:11 are on */
  569. if ((addr & 0x00ff800) == 0xff800) {
  570. printk("%s: QM access not handled.\n", __func__);
  571. addr = -1UL;
  572. }
  573. window = OCM_WIN(addr);
  574. ha->ddr_mn_window = window;
  575. qla4_82xx_wr_32(ha, ha->mn_win_crb |
  576. QLA82XX_PCI_CRBSPACE, window);
  577. win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
  578. QLA82XX_PCI_CRBSPACE);
  579. temp1 = ((window & 0x1FF) << 7) |
  580. ((window & 0x0FFFE0000) >> 17);
  581. if (win_read != temp1) {
  582. printk("%s: Written OCMwin (0x%x) != Read"
  583. " OCMwin (0x%x)\n", __func__, temp1, win_read);
  584. }
  585. addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
  586. } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
  587. QLA82XX_P3_ADDR_QDR_NET_MAX)) {
  588. /* QDR network side */
  589. window = MS_WIN(addr);
  590. ha->qdr_sn_window = window;
  591. qla4_82xx_wr_32(ha, ha->ms_win_crb |
  592. QLA82XX_PCI_CRBSPACE, window);
  593. win_read = qla4_82xx_rd_32(ha,
  594. ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
  595. if (win_read != window) {
  596. printk("%s: Written MSwin (0x%x) != Read "
  597. "MSwin (0x%x)\n", __func__, window, win_read);
  598. }
  599. addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
  600. } else {
  601. /*
  602. * peg gdb frequently accesses memory that doesn't exist,
  603. * this limits the chit chat so debugging isn't slowed down.
  604. */
  605. if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
  606. (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
  607. printk("%s: Warning:%s Unknown address range!\n",
  608. __func__, DRIVER_NAME);
  609. }
  610. addr = -1UL;
  611. }
  612. return addr;
  613. }
  614. /* check if address is in the same windows as the previous access */
  615. static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
  616. unsigned long long addr)
  617. {
  618. int window;
  619. unsigned long long qdr_max;
  620. qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
  621. if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
  622. QLA8XXX_ADDR_DDR_NET_MAX)) {
  623. /* DDR network side */
  624. BUG(); /* MN access can not come here */
  625. } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
  626. QLA8XXX_ADDR_OCM0_MAX)) {
  627. return 1;
  628. } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
  629. QLA8XXX_ADDR_OCM1_MAX)) {
  630. return 1;
  631. } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
  632. qdr_max)) {
  633. /* QDR network side */
  634. window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
  635. if (ha->qdr_sn_window == window)
  636. return 1;
  637. }
  638. return 0;
  639. }
  640. static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
  641. u64 off, void *data, int size)
  642. {
  643. unsigned long flags;
  644. void __iomem *addr;
  645. int ret = 0;
  646. u64 start;
  647. void __iomem *mem_ptr = NULL;
  648. unsigned long mem_base;
  649. unsigned long mem_page;
  650. write_lock_irqsave(&ha->hw_lock, flags);
  651. /*
  652. * If attempting to access unknown address or straddle hw windows,
  653. * do not access.
  654. */
  655. start = qla4_82xx_pci_set_window(ha, off);
  656. if ((start == -1UL) ||
  657. (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
  658. write_unlock_irqrestore(&ha->hw_lock, flags);
  659. printk(KERN_ERR"%s out of bound pci memory access. "
  660. "offset is 0x%llx\n", DRIVER_NAME, off);
  661. return -1;
  662. }
  663. addr = qla4_8xxx_pci_base_offsetfset(ha, start);
  664. if (!addr) {
  665. write_unlock_irqrestore(&ha->hw_lock, flags);
  666. mem_base = pci_resource_start(ha->pdev, 0);
  667. mem_page = start & PAGE_MASK;
  668. /* Map two pages whenever user tries to access addresses in two
  669. consecutive pages.
  670. */
  671. if (mem_page != ((start + size - 1) & PAGE_MASK))
  672. mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
  673. else
  674. mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
  675. if (mem_ptr == NULL) {
  676. *(u8 *)data = 0;
  677. return -1;
  678. }
  679. addr = mem_ptr;
  680. addr += start & (PAGE_SIZE - 1);
  681. write_lock_irqsave(&ha->hw_lock, flags);
  682. }
  683. switch (size) {
  684. case 1:
  685. *(u8 *)data = readb(addr);
  686. break;
  687. case 2:
  688. *(u16 *)data = readw(addr);
  689. break;
  690. case 4:
  691. *(u32 *)data = readl(addr);
  692. break;
  693. case 8:
  694. *(u64 *)data = readq(addr);
  695. break;
  696. default:
  697. ret = -1;
  698. break;
  699. }
  700. write_unlock_irqrestore(&ha->hw_lock, flags);
  701. if (mem_ptr)
  702. iounmap(mem_ptr);
  703. return ret;
  704. }
  705. static int
  706. qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
  707. void *data, int size)
  708. {
  709. unsigned long flags;
  710. void __iomem *addr;
  711. int ret = 0;
  712. u64 start;
  713. void __iomem *mem_ptr = NULL;
  714. unsigned long mem_base;
  715. unsigned long mem_page;
  716. write_lock_irqsave(&ha->hw_lock, flags);
  717. /*
  718. * If attempting to access unknown address or straddle hw windows,
  719. * do not access.
  720. */
  721. start = qla4_82xx_pci_set_window(ha, off);
  722. if ((start == -1UL) ||
  723. (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
  724. write_unlock_irqrestore(&ha->hw_lock, flags);
  725. printk(KERN_ERR"%s out of bound pci memory access. "
  726. "offset is 0x%llx\n", DRIVER_NAME, off);
  727. return -1;
  728. }
  729. addr = qla4_8xxx_pci_base_offsetfset(ha, start);
  730. if (!addr) {
  731. write_unlock_irqrestore(&ha->hw_lock, flags);
  732. mem_base = pci_resource_start(ha->pdev, 0);
  733. mem_page = start & PAGE_MASK;
  734. /* Map two pages whenever user tries to access addresses in two
  735. consecutive pages.
  736. */
  737. if (mem_page != ((start + size - 1) & PAGE_MASK))
  738. mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
  739. else
  740. mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
  741. if (mem_ptr == NULL)
  742. return -1;
  743. addr = mem_ptr;
  744. addr += start & (PAGE_SIZE - 1);
  745. write_lock_irqsave(&ha->hw_lock, flags);
  746. }
  747. switch (size) {
  748. case 1:
  749. writeb(*(u8 *)data, addr);
  750. break;
  751. case 2:
  752. writew(*(u16 *)data, addr);
  753. break;
  754. case 4:
  755. writel(*(u32 *)data, addr);
  756. break;
  757. case 8:
  758. writeq(*(u64 *)data, addr);
  759. break;
  760. default:
  761. ret = -1;
  762. break;
  763. }
  764. write_unlock_irqrestore(&ha->hw_lock, flags);
  765. if (mem_ptr)
  766. iounmap(mem_ptr);
  767. return ret;
  768. }
  769. #define MTU_FUDGE_FACTOR 100
  770. static unsigned long
  771. qla4_82xx_decode_crb_addr(unsigned long addr)
  772. {
  773. int i;
  774. unsigned long base_addr, offset, pci_base;
  775. if (!qla4_8xxx_crb_table_initialized)
  776. qla4_82xx_crb_addr_transform_setup();
  777. pci_base = ADDR_ERROR;
  778. base_addr = addr & 0xfff00000;
  779. offset = addr & 0x000fffff;
  780. for (i = 0; i < MAX_CRB_XFORM; i++) {
  781. if (crb_addr_xform[i] == base_addr) {
  782. pci_base = i << 20;
  783. break;
  784. }
  785. }
  786. if (pci_base == ADDR_ERROR)
  787. return pci_base;
  788. else
  789. return pci_base + offset;
  790. }
  791. static long rom_max_timeout = 100;
  792. static long qla4_82xx_rom_lock_timeout = 100;
  793. /*
  794. * Context: task, can_sleep
  795. */
  796. static int
  797. qla4_82xx_rom_lock(struct scsi_qla_host *ha)
  798. {
  799. int done = 0, timeout = 0;
  800. might_sleep();
  801. while (!done) {
  802. /* acquire semaphore2 from PCI HW block */
  803. done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
  804. if (done == 1)
  805. break;
  806. if (timeout >= qla4_82xx_rom_lock_timeout)
  807. return -1;
  808. timeout++;
  809. msleep(20);
  810. }
  811. qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  812. return 0;
  813. }
  814. static void
  815. qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
  816. {
  817. qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
  818. }
  819. static int
  820. qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
  821. {
  822. long timeout = 0;
  823. long done = 0 ;
  824. while (done == 0) {
  825. done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
  826. done &= 2;
  827. timeout++;
  828. if (timeout >= rom_max_timeout) {
  829. printk("%s: Timeout reached waiting for rom done",
  830. DRIVER_NAME);
  831. return -1;
  832. }
  833. }
  834. return 0;
  835. }
  836. static int
  837. qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
  838. {
  839. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
  840. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  841. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
  842. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  843. if (qla4_82xx_wait_rom_done(ha)) {
  844. printk("%s: Error waiting for rom done\n", DRIVER_NAME);
  845. return -1;
  846. }
  847. /* reset abyte_cnt and dummy_byte_cnt */
  848. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  849. udelay(10);
  850. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
  851. *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
  852. return 0;
  853. }
  854. static int
  855. qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
  856. {
  857. int ret, loops = 0;
  858. while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
  859. udelay(100);
  860. loops++;
  861. }
  862. if (loops >= 50000) {
  863. ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
  864. DRIVER_NAME);
  865. return -1;
  866. }
  867. ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
  868. qla4_82xx_rom_unlock(ha);
  869. return ret;
  870. }
  871. /*
  872. * This routine does CRB initialize sequence
  873. * to put the ISP into operational state
  874. */
  875. static int
  876. qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
  877. {
  878. int addr, val;
  879. int i ;
  880. struct crb_addr_pair *buf;
  881. unsigned long off;
  882. unsigned offset, n;
  883. struct crb_addr_pair {
  884. long addr;
  885. long data;
  886. };
  887. /* Halt all the indiviual PEGs and other blocks of the ISP */
  888. qla4_82xx_rom_lock(ha);
  889. /* disable all I2Q */
  890. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
  891. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
  892. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
  893. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
  894. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
  895. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
  896. /* disable all niu interrupts */
  897. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
  898. /* disable xge rx/tx */
  899. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
  900. /* disable xg1 rx/tx */
  901. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
  902. /* disable sideband mac */
  903. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
  904. /* disable ap0 mac */
  905. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
  906. /* disable ap1 mac */
  907. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
  908. /* halt sre */
  909. val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
  910. qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
  911. /* halt epg */
  912. qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
  913. /* halt timers */
  914. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
  915. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
  916. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
  917. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
  918. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
  919. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
  920. /* halt pegs */
  921. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
  922. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
  923. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
  924. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
  925. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
  926. msleep(5);
  927. /* big hammer */
  928. if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
  929. /* don't reset CAM block on reset */
  930. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
  931. else
  932. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
  933. qla4_82xx_rom_unlock(ha);
  934. /* Read the signature value from the flash.
  935. * Offset 0: Contain signature (0xcafecafe)
  936. * Offset 4: Offset and number of addr/value pairs
  937. * that present in CRB initialize sequence
  938. */
  939. if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
  940. qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
  941. ql4_printk(KERN_WARNING, ha,
  942. "[ERROR] Reading crb_init area: n: %08x\n", n);
  943. return -1;
  944. }
  945. /* Offset in flash = lower 16 bits
  946. * Number of enteries = upper 16 bits
  947. */
  948. offset = n & 0xffffU;
  949. n = (n >> 16) & 0xffffU;
  950. /* number of addr/value pair should not exceed 1024 enteries */
  951. if (n >= 1024) {
  952. ql4_printk(KERN_WARNING, ha,
  953. "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
  954. DRIVER_NAME, __func__, n);
  955. return -1;
  956. }
  957. ql4_printk(KERN_INFO, ha,
  958. "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
  959. buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  960. if (buf == NULL) {
  961. ql4_printk(KERN_WARNING, ha,
  962. "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
  963. return -1;
  964. }
  965. for (i = 0; i < n; i++) {
  966. if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
  967. qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
  968. 0) {
  969. kfree(buf);
  970. return -1;
  971. }
  972. buf[i].addr = addr;
  973. buf[i].data = val;
  974. }
  975. for (i = 0; i < n; i++) {
  976. /* Translate internal CRB initialization
  977. * address to PCI bus address
  978. */
  979. off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
  980. QLA82XX_PCI_CRBSPACE;
  981. /* Not all CRB addr/value pair to be written,
  982. * some of them are skipped
  983. */
  984. /* skip if LS bit is set*/
  985. if (off & 0x1) {
  986. DEBUG2(ql4_printk(KERN_WARNING, ha,
  987. "Skip CRB init replay for offset = 0x%lx\n", off));
  988. continue;
  989. }
  990. /* skipping cold reboot MAGIC */
  991. if (off == QLA82XX_CAM_RAM(0x1fc))
  992. continue;
  993. /* do not reset PCI */
  994. if (off == (ROMUSB_GLB + 0xbc))
  995. continue;
  996. /* skip core clock, so that firmware can increase the clock */
  997. if (off == (ROMUSB_GLB + 0xc8))
  998. continue;
  999. /* skip the function enable register */
  1000. if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
  1001. continue;
  1002. if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
  1003. continue;
  1004. if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
  1005. continue;
  1006. if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
  1007. continue;
  1008. if (off == ADDR_ERROR) {
  1009. ql4_printk(KERN_WARNING, ha,
  1010. "%s: [ERROR] Unknown addr: 0x%08lx\n",
  1011. DRIVER_NAME, buf[i].addr);
  1012. continue;
  1013. }
  1014. qla4_82xx_wr_32(ha, off, buf[i].data);
  1015. /* ISP requires much bigger delay to settle down,
  1016. * else crb_window returns 0xffffffff
  1017. */
  1018. if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
  1019. msleep(1000);
  1020. /* ISP requires millisec delay between
  1021. * successive CRB register updation
  1022. */
  1023. msleep(1);
  1024. }
  1025. kfree(buf);
  1026. /* Resetting the data and instruction cache */
  1027. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
  1028. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
  1029. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
  1030. /* Clear all protocol processing engines */
  1031. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
  1032. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
  1033. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
  1034. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
  1035. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
  1036. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
  1037. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
  1038. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
  1039. return 0;
  1040. }
  1041. /**
  1042. * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory
  1043. * @ha: Pointer to adapter structure
  1044. * @addr: Flash address to write to
  1045. * @data: Data to be written
  1046. * @count: word_count to be written
  1047. *
  1048. * Return: On success return QLA_SUCCESS
  1049. * On error return QLA_ERROR
  1050. **/
  1051. int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
  1052. uint32_t *data, uint32_t count)
  1053. {
  1054. int i, j;
  1055. uint32_t agt_ctrl;
  1056. unsigned long flags;
  1057. int ret_val = QLA_SUCCESS;
  1058. /* Only 128-bit aligned access */
  1059. if (addr & 0xF) {
  1060. ret_val = QLA_ERROR;
  1061. goto exit_ms_mem_write;
  1062. }
  1063. write_lock_irqsave(&ha->hw_lock, flags);
  1064. /* Write address */
  1065. ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0);
  1066. if (ret_val == QLA_ERROR) {
  1067. ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n",
  1068. __func__);
  1069. goto exit_ms_mem_write_unlock;
  1070. }
  1071. for (i = 0; i < count; i++, addr += 16) {
  1072. if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
  1073. QLA8XXX_ADDR_QDR_NET_MAX)) ||
  1074. (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
  1075. QLA8XXX_ADDR_DDR_NET_MAX)))) {
  1076. ret_val = QLA_ERROR;
  1077. goto exit_ms_mem_write_unlock;
  1078. }
  1079. ret_val = ha->isp_ops->wr_reg_indirect(ha,
  1080. MD_MIU_TEST_AGT_ADDR_LO,
  1081. addr);
  1082. /* Write data */
  1083. ret_val |= ha->isp_ops->wr_reg_indirect(ha,
  1084. MD_MIU_TEST_AGT_WRDATA_LO,
  1085. *data++);
  1086. ret_val |= ha->isp_ops->wr_reg_indirect(ha,
  1087. MD_MIU_TEST_AGT_WRDATA_HI,
  1088. *data++);
  1089. ret_val |= ha->isp_ops->wr_reg_indirect(ha,
  1090. MD_MIU_TEST_AGT_WRDATA_ULO,
  1091. *data++);
  1092. ret_val |= ha->isp_ops->wr_reg_indirect(ha,
  1093. MD_MIU_TEST_AGT_WRDATA_UHI,
  1094. *data++);
  1095. if (ret_val == QLA_ERROR) {
  1096. ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n",
  1097. __func__);
  1098. goto exit_ms_mem_write_unlock;
  1099. }
  1100. /* Check write status */
  1101. ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
  1102. MIU_TA_CTL_WRITE_ENABLE);
  1103. ret_val |= ha->isp_ops->wr_reg_indirect(ha,
  1104. MD_MIU_TEST_AGT_CTRL,
  1105. MIU_TA_CTL_WRITE_START);
  1106. if (ret_val == QLA_ERROR) {
  1107. ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n",
  1108. __func__);
  1109. goto exit_ms_mem_write_unlock;
  1110. }
  1111. for (j = 0; j < MAX_CTL_CHECK; j++) {
  1112. ret_val = ha->isp_ops->rd_reg_indirect(ha,
  1113. MD_MIU_TEST_AGT_CTRL,
  1114. &agt_ctrl);
  1115. if (ret_val == QLA_ERROR) {
  1116. ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n",
  1117. __func__);
  1118. goto exit_ms_mem_write_unlock;
  1119. }
  1120. if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
  1121. break;
  1122. }
  1123. /* Status check failed */
  1124. if (j >= MAX_CTL_CHECK) {
  1125. printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n",
  1126. __func__);
  1127. ret_val = QLA_ERROR;
  1128. goto exit_ms_mem_write_unlock;
  1129. }
  1130. }
  1131. exit_ms_mem_write_unlock:
  1132. write_unlock_irqrestore(&ha->hw_lock, flags);
  1133. exit_ms_mem_write:
  1134. return ret_val;
  1135. }
  1136. static int
  1137. qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
  1138. {
  1139. int i, rval = 0;
  1140. long size = 0;
  1141. long flashaddr, memaddr;
  1142. u64 data;
  1143. u32 high, low;
  1144. flashaddr = memaddr = ha->hw.flt_region_bootload;
  1145. size = (image_start - flashaddr) / 8;
  1146. DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
  1147. ha->host_no, __func__, flashaddr, image_start));
  1148. for (i = 0; i < size; i++) {
  1149. if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
  1150. (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
  1151. (int *)&high))) {
  1152. rval = -1;
  1153. goto exit_load_from_flash;
  1154. }
  1155. data = ((u64)high << 32) | low ;
  1156. rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
  1157. if (rval)
  1158. goto exit_load_from_flash;
  1159. flashaddr += 8;
  1160. memaddr += 8;
  1161. if (i % 0x1000 == 0)
  1162. msleep(1);
  1163. }
  1164. udelay(100);
  1165. read_lock(&ha->hw_lock);
  1166. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
  1167. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
  1168. read_unlock(&ha->hw_lock);
  1169. exit_load_from_flash:
  1170. return rval;
  1171. }
  1172. static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
  1173. {
  1174. u32 rst;
  1175. qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
  1176. if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
  1177. printk(KERN_WARNING "%s: Error during CRB Initialization\n",
  1178. __func__);
  1179. return QLA_ERROR;
  1180. }
  1181. udelay(500);
  1182. /* at this point, QM is in reset. This could be a problem if there are
  1183. * incoming d* transition queue messages. QM/PCIE could wedge.
  1184. * To get around this, QM is brought out of reset.
  1185. */
  1186. rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
  1187. /* unreset qm */
  1188. rst &= ~(1 << 28);
  1189. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
  1190. if (qla4_82xx_load_from_flash(ha, image_start)) {
  1191. printk("%s: Error trying to load fw from flash!\n", __func__);
  1192. return QLA_ERROR;
  1193. }
  1194. return QLA_SUCCESS;
  1195. }
  1196. int
  1197. qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
  1198. u64 off, void *data, int size)
  1199. {
  1200. int i, j = 0, k, start, end, loop, sz[2], off0[2];
  1201. int shift_amount;
  1202. uint32_t temp;
  1203. uint64_t off8, val, mem_crb, word[2] = {0, 0};
  1204. /*
  1205. * If not MN, go check for MS or invalid.
  1206. */
  1207. if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
  1208. mem_crb = QLA82XX_CRB_QDR_NET;
  1209. else {
  1210. mem_crb = QLA82XX_CRB_DDR_NET;
  1211. if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
  1212. return qla4_82xx_pci_mem_read_direct(ha,
  1213. off, data, size);
  1214. }
  1215. off8 = off & 0xfffffff0;
  1216. off0[0] = off & 0xf;
  1217. sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
  1218. shift_amount = 4;
  1219. loop = ((off0[0] + size - 1) >> shift_amount) + 1;
  1220. off0[1] = 0;
  1221. sz[1] = size - sz[0];
  1222. for (i = 0; i < loop; i++) {
  1223. temp = off8 + (i << shift_amount);
  1224. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
  1225. temp = 0;
  1226. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
  1227. temp = MIU_TA_CTL_ENABLE;
  1228. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
  1229. temp = MIU_TA_CTL_START_ENABLE;
  1230. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
  1231. for (j = 0; j < MAX_CTL_CHECK; j++) {
  1232. temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
  1233. if ((temp & MIU_TA_CTL_BUSY) == 0)
  1234. break;
  1235. }
  1236. if (j >= MAX_CTL_CHECK) {
  1237. printk_ratelimited(KERN_ERR
  1238. "%s: failed to read through agent\n",
  1239. __func__);
  1240. break;
  1241. }
  1242. start = off0[i] >> 2;
  1243. end = (off0[i] + sz[i] - 1) >> 2;
  1244. for (k = start; k <= end; k++) {
  1245. temp = qla4_82xx_rd_32(ha,
  1246. mem_crb + MIU_TEST_AGT_RDDATA(k));
  1247. word[i] |= ((uint64_t)temp << (32 * (k & 1)));
  1248. }
  1249. }
  1250. if (j >= MAX_CTL_CHECK)
  1251. return -1;
  1252. if ((off0[0] & 7) == 0) {
  1253. val = word[0];
  1254. } else {
  1255. val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
  1256. ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
  1257. }
  1258. switch (size) {
  1259. case 1:
  1260. *(uint8_t *)data = val;
  1261. break;
  1262. case 2:
  1263. *(uint16_t *)data = val;
  1264. break;
  1265. case 4:
  1266. *(uint32_t *)data = val;
  1267. break;
  1268. case 8:
  1269. *(uint64_t *)data = val;
  1270. break;
  1271. }
  1272. return 0;
  1273. }
  1274. int
  1275. qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
  1276. u64 off, void *data, int size)
  1277. {
  1278. int i, j, ret = 0, loop, sz[2], off0;
  1279. int scale, shift_amount, startword;
  1280. uint32_t temp;
  1281. uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
  1282. /*
  1283. * If not MN, go check for MS or invalid.
  1284. */
  1285. if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
  1286. mem_crb = QLA82XX_CRB_QDR_NET;
  1287. else {
  1288. mem_crb = QLA82XX_CRB_DDR_NET;
  1289. if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
  1290. return qla4_82xx_pci_mem_write_direct(ha,
  1291. off, data, size);
  1292. }
  1293. off0 = off & 0x7;
  1294. sz[0] = (size < (8 - off0)) ? size : (8 - off0);
  1295. sz[1] = size - sz[0];
  1296. off8 = off & 0xfffffff0;
  1297. loop = (((off & 0xf) + size - 1) >> 4) + 1;
  1298. shift_amount = 4;
  1299. scale = 2;
  1300. startword = (off & 0xf)/8;
  1301. for (i = 0; i < loop; i++) {
  1302. if (qla4_82xx_pci_mem_read_2M(ha, off8 +
  1303. (i << shift_amount), &word[i * scale], 8))
  1304. return -1;
  1305. }
  1306. switch (size) {
  1307. case 1:
  1308. tmpw = *((uint8_t *)data);
  1309. break;
  1310. case 2:
  1311. tmpw = *((uint16_t *)data);
  1312. break;
  1313. case 4:
  1314. tmpw = *((uint32_t *)data);
  1315. break;
  1316. case 8:
  1317. default:
  1318. tmpw = *((uint64_t *)data);
  1319. break;
  1320. }
  1321. if (sz[0] == 8)
  1322. word[startword] = tmpw;
  1323. else {
  1324. word[startword] &=
  1325. ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
  1326. word[startword] |= tmpw << (off0 * 8);
  1327. }
  1328. if (sz[1] != 0) {
  1329. word[startword+1] &= ~(~0ULL << (sz[1] * 8));
  1330. word[startword+1] |= tmpw >> (sz[0] * 8);
  1331. }
  1332. for (i = 0; i < loop; i++) {
  1333. temp = off8 + (i << shift_amount);
  1334. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
  1335. temp = 0;
  1336. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
  1337. temp = word[i * scale] & 0xffffffff;
  1338. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
  1339. temp = (word[i * scale] >> 32) & 0xffffffff;
  1340. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
  1341. temp = word[i*scale + 1] & 0xffffffff;
  1342. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
  1343. temp);
  1344. temp = (word[i*scale + 1] >> 32) & 0xffffffff;
  1345. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
  1346. temp);
  1347. temp = MIU_TA_CTL_WRITE_ENABLE;
  1348. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
  1349. temp = MIU_TA_CTL_WRITE_START;
  1350. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
  1351. for (j = 0; j < MAX_CTL_CHECK; j++) {
  1352. temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
  1353. if ((temp & MIU_TA_CTL_BUSY) == 0)
  1354. break;
  1355. }
  1356. if (j >= MAX_CTL_CHECK) {
  1357. if (printk_ratelimit())
  1358. ql4_printk(KERN_ERR, ha,
  1359. "%s: failed to read through agent\n",
  1360. __func__);
  1361. ret = -1;
  1362. break;
  1363. }
  1364. }
  1365. return ret;
  1366. }
  1367. static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
  1368. {
  1369. u32 val = 0;
  1370. int retries = 60;
  1371. if (!pegtune_val) {
  1372. do {
  1373. val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
  1374. if ((val == PHAN_INITIALIZE_COMPLETE) ||
  1375. (val == PHAN_INITIALIZE_ACK))
  1376. return 0;
  1377. set_current_state(TASK_UNINTERRUPTIBLE);
  1378. schedule_timeout(500);
  1379. } while (--retries);
  1380. if (!retries) {
  1381. pegtune_val = qla4_82xx_rd_32(ha,
  1382. QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
  1383. printk(KERN_WARNING "%s: init failed, "
  1384. "pegtune_val = %x\n", __func__, pegtune_val);
  1385. return -1;
  1386. }
  1387. }
  1388. return 0;
  1389. }
  1390. static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
  1391. {
  1392. uint32_t state = 0;
  1393. int loops = 0;
  1394. /* Window 1 call */
  1395. read_lock(&ha->hw_lock);
  1396. state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
  1397. read_unlock(&ha->hw_lock);
  1398. while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
  1399. udelay(100);
  1400. /* Window 1 call */
  1401. read_lock(&ha->hw_lock);
  1402. state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
  1403. read_unlock(&ha->hw_lock);
  1404. loops++;
  1405. }
  1406. if (loops >= 30000) {
  1407. DEBUG2(ql4_printk(KERN_INFO, ha,
  1408. "Receive Peg initialization not complete: 0x%x.\n", state));
  1409. return QLA_ERROR;
  1410. }
  1411. return QLA_SUCCESS;
  1412. }
  1413. void
  1414. qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
  1415. {
  1416. uint32_t drv_active;
  1417. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  1418. /*
  1419. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1420. * shift 1 by func_num to set a bit for the function.
  1421. * For ISP8022, drv_active has 4 bits per function
  1422. */
  1423. if (is_qla8032(ha) || is_qla8042(ha))
  1424. drv_active |= (1 << ha->func_num);
  1425. else
  1426. drv_active |= (1 << (ha->func_num * 4));
  1427. ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
  1428. __func__, ha->host_no, drv_active);
  1429. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
  1430. }
  1431. void
  1432. qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
  1433. {
  1434. uint32_t drv_active;
  1435. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  1436. /*
  1437. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1438. * shift 1 by func_num to set a bit for the function.
  1439. * For ISP8022, drv_active has 4 bits per function
  1440. */
  1441. if (is_qla8032(ha) || is_qla8042(ha))
  1442. drv_active &= ~(1 << (ha->func_num));
  1443. else
  1444. drv_active &= ~(1 << (ha->func_num * 4));
  1445. ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
  1446. __func__, ha->host_no, drv_active);
  1447. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
  1448. }
  1449. inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
  1450. {
  1451. uint32_t drv_state, drv_active;
  1452. int rval;
  1453. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  1454. drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
  1455. /*
  1456. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1457. * shift 1 by func_num to set a bit for the function.
  1458. * For ISP8022, drv_active has 4 bits per function
  1459. */
  1460. if (is_qla8032(ha) || is_qla8042(ha))
  1461. rval = drv_state & (1 << ha->func_num);
  1462. else
  1463. rval = drv_state & (1 << (ha->func_num * 4));
  1464. if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
  1465. rval = 1;
  1466. return rval;
  1467. }
  1468. void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
  1469. {
  1470. uint32_t drv_state;
  1471. drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
  1472. /*
  1473. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1474. * shift 1 by func_num to set a bit for the function.
  1475. * For ISP8022, drv_active has 4 bits per function
  1476. */
  1477. if (is_qla8032(ha) || is_qla8042(ha))
  1478. drv_state |= (1 << ha->func_num);
  1479. else
  1480. drv_state |= (1 << (ha->func_num * 4));
  1481. ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
  1482. __func__, ha->host_no, drv_state);
  1483. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
  1484. }
  1485. void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
  1486. {
  1487. uint32_t drv_state;
  1488. drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
  1489. /*
  1490. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1491. * shift 1 by func_num to set a bit for the function.
  1492. * For ISP8022, drv_active has 4 bits per function
  1493. */
  1494. if (is_qla8032(ha) || is_qla8042(ha))
  1495. drv_state &= ~(1 << ha->func_num);
  1496. else
  1497. drv_state &= ~(1 << (ha->func_num * 4));
  1498. ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
  1499. __func__, ha->host_no, drv_state);
  1500. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
  1501. }
  1502. static inline void
  1503. qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
  1504. {
  1505. uint32_t qsnt_state;
  1506. qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
  1507. /*
  1508. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1509. * shift 1 by func_num to set a bit for the function.
  1510. * For ISP8022, drv_active has 4 bits per function.
  1511. */
  1512. if (is_qla8032(ha) || is_qla8042(ha))
  1513. qsnt_state |= (1 << ha->func_num);
  1514. else
  1515. qsnt_state |= (2 << (ha->func_num * 4));
  1516. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
  1517. }
  1518. static int
  1519. qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
  1520. {
  1521. uint16_t lnk;
  1522. /* scrub dma mask expansion register */
  1523. qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
  1524. /* Overwrite stale initialization register values */
  1525. qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
  1526. qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
  1527. qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
  1528. qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
  1529. if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
  1530. printk("%s: Error trying to start fw!\n", __func__);
  1531. return QLA_ERROR;
  1532. }
  1533. /* Handshake with the card before we register the devices. */
  1534. if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
  1535. printk("%s: Error during card handshake!\n", __func__);
  1536. return QLA_ERROR;
  1537. }
  1538. /* Negotiated Link width */
  1539. pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
  1540. ha->link_width = (lnk >> 4) & 0x3f;
  1541. /* Synchronize with Receive peg */
  1542. return qla4_82xx_rcvpeg_ready(ha);
  1543. }
  1544. int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
  1545. {
  1546. int rval;
  1547. /*
  1548. * FW Load priority:
  1549. * 1) Operational firmware residing in flash.
  1550. * 2) Fail
  1551. */
  1552. ql4_printk(KERN_INFO, ha,
  1553. "FW: Retrieving flash offsets from FLT/FDT ...\n");
  1554. rval = qla4_8xxx_get_flash_info(ha);
  1555. if (rval != QLA_SUCCESS)
  1556. return rval;
  1557. ql4_printk(KERN_INFO, ha,
  1558. "FW: Attempting to load firmware from flash...\n");
  1559. rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
  1560. if (rval != QLA_SUCCESS) {
  1561. ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
  1562. " FAILED...\n");
  1563. return rval;
  1564. }
  1565. return rval;
  1566. }
  1567. void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
  1568. {
  1569. if (qla4_82xx_rom_lock(ha)) {
  1570. /* Someone else is holding the lock. */
  1571. dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
  1572. }
  1573. /*
  1574. * Either we got the lock, or someone
  1575. * else died while holding it.
  1576. * In either case, unlock.
  1577. */
  1578. qla4_82xx_rom_unlock(ha);
  1579. }
  1580. static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha,
  1581. uint32_t addr1, uint32_t mask)
  1582. {
  1583. unsigned long timeout;
  1584. uint32_t rval = QLA_SUCCESS;
  1585. uint32_t temp;
  1586. timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
  1587. do {
  1588. ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
  1589. if ((temp & mask) != 0)
  1590. break;
  1591. if (time_after_eq(jiffies, timeout)) {
  1592. ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n");
  1593. return QLA_ERROR;
  1594. }
  1595. } while (1);
  1596. return rval;
  1597. }
  1598. static uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1,
  1599. uint32_t addr3, uint32_t mask, uint32_t addr,
  1600. uint32_t *data_ptr)
  1601. {
  1602. int rval = QLA_SUCCESS;
  1603. uint32_t temp;
  1604. uint32_t data;
  1605. rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
  1606. if (rval)
  1607. goto exit_ipmdio_rd_reg;
  1608. temp = (0x40000000 | addr);
  1609. ha->isp_ops->wr_reg_indirect(ha, addr1, temp);
  1610. rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
  1611. if (rval)
  1612. goto exit_ipmdio_rd_reg;
  1613. ha->isp_ops->rd_reg_indirect(ha, addr3, &data);
  1614. *data_ptr = data;
  1615. exit_ipmdio_rd_reg:
  1616. return rval;
  1617. }
  1618. static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha,
  1619. uint32_t addr1,
  1620. uint32_t addr2,
  1621. uint32_t addr3,
  1622. uint32_t mask)
  1623. {
  1624. unsigned long timeout;
  1625. uint32_t temp;
  1626. uint32_t rval = QLA_SUCCESS;
  1627. timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
  1628. do {
  1629. ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp);
  1630. if ((temp & 0x1) != 1)
  1631. break;
  1632. if (time_after_eq(jiffies, timeout)) {
  1633. ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n");
  1634. return QLA_ERROR;
  1635. }
  1636. } while (1);
  1637. return rval;
  1638. }
  1639. static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha,
  1640. uint32_t addr1, uint32_t addr3,
  1641. uint32_t mask, uint32_t addr,
  1642. uint32_t value)
  1643. {
  1644. int rval = QLA_SUCCESS;
  1645. rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
  1646. if (rval)
  1647. goto exit_ipmdio_wr_reg;
  1648. ha->isp_ops->wr_reg_indirect(ha, addr3, value);
  1649. ha->isp_ops->wr_reg_indirect(ha, addr1, addr);
  1650. rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
  1651. if (rval)
  1652. goto exit_ipmdio_wr_reg;
  1653. exit_ipmdio_wr_reg:
  1654. return rval;
  1655. }
  1656. static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
  1657. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  1658. uint32_t **d_ptr)
  1659. {
  1660. uint32_t r_addr, r_stride, loop_cnt, i, r_value;
  1661. struct qla8xxx_minidump_entry_crb *crb_hdr;
  1662. uint32_t *data_ptr = *d_ptr;
  1663. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  1664. crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
  1665. r_addr = crb_hdr->addr;
  1666. r_stride = crb_hdr->crb_strd.addr_stride;
  1667. loop_cnt = crb_hdr->op_count;
  1668. for (i = 0; i < loop_cnt; i++) {
  1669. ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
  1670. *data_ptr++ = cpu_to_le32(r_addr);
  1671. *data_ptr++ = cpu_to_le32(r_value);
  1672. r_addr += r_stride;
  1673. }
  1674. *d_ptr = data_ptr;
  1675. }
  1676. static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha)
  1677. {
  1678. int rval = QLA_SUCCESS;
  1679. uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
  1680. uint64_t dma_base_addr = 0;
  1681. struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
  1682. tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
  1683. ha->fw_dump_tmplt_hdr;
  1684. dma_eng_num =
  1685. tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
  1686. dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
  1687. (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
  1688. /* Read the pex-dma's command-status-and-control register. */
  1689. rval = ha->isp_ops->rd_reg_indirect(ha,
  1690. (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
  1691. &cmd_sts_and_cntrl);
  1692. if (rval)
  1693. return QLA_ERROR;
  1694. /* Check if requested pex-dma engine is available. */
  1695. if (cmd_sts_and_cntrl & BIT_31)
  1696. return QLA_SUCCESS;
  1697. else
  1698. return QLA_ERROR;
  1699. }
  1700. static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
  1701. struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr)
  1702. {
  1703. int rval = QLA_SUCCESS, wait = 0;
  1704. uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
  1705. uint64_t dma_base_addr = 0;
  1706. struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
  1707. tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
  1708. ha->fw_dump_tmplt_hdr;
  1709. dma_eng_num =
  1710. tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
  1711. dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
  1712. (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
  1713. rval = ha->isp_ops->wr_reg_indirect(ha,
  1714. dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW,
  1715. m_hdr->desc_card_addr);
  1716. if (rval)
  1717. goto error_exit;
  1718. rval = ha->isp_ops->wr_reg_indirect(ha,
  1719. dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0);
  1720. if (rval)
  1721. goto error_exit;
  1722. rval = ha->isp_ops->wr_reg_indirect(ha,
  1723. dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL,
  1724. m_hdr->start_dma_cmd);
  1725. if (rval)
  1726. goto error_exit;
  1727. /* Wait for dma operation to complete. */
  1728. for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) {
  1729. rval = ha->isp_ops->rd_reg_indirect(ha,
  1730. (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
  1731. &cmd_sts_and_cntrl);
  1732. if (rval)
  1733. goto error_exit;
  1734. if ((cmd_sts_and_cntrl & BIT_1) == 0)
  1735. break;
  1736. else
  1737. udelay(10);
  1738. }
  1739. /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
  1740. if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) {
  1741. rval = QLA_ERROR;
  1742. goto error_exit;
  1743. }
  1744. error_exit:
  1745. return rval;
  1746. }
  1747. static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha,
  1748. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  1749. uint32_t **d_ptr)
  1750. {
  1751. int rval = QLA_SUCCESS;
  1752. struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
  1753. uint32_t size, read_size;
  1754. uint8_t *data_ptr = (uint8_t *)*d_ptr;
  1755. void *rdmem_buffer = NULL;
  1756. dma_addr_t rdmem_dma;
  1757. struct qla4_83xx_pex_dma_descriptor dma_desc;
  1758. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  1759. rval = qla4_83xx_check_dma_engine_state(ha);
  1760. if (rval != QLA_SUCCESS) {
  1761. DEBUG2(ql4_printk(KERN_INFO, ha,
  1762. "%s: DMA engine not available. Fallback to rdmem-read.\n",
  1763. __func__));
  1764. return QLA_ERROR;
  1765. }
  1766. m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr;
  1767. rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
  1768. QLA83XX_PEX_DMA_READ_SIZE,
  1769. &rdmem_dma, GFP_KERNEL);
  1770. if (!rdmem_buffer) {
  1771. DEBUG2(ql4_printk(KERN_INFO, ha,
  1772. "%s: Unable to allocate rdmem dma buffer\n",
  1773. __func__));
  1774. return QLA_ERROR;
  1775. }
  1776. /* Prepare pex-dma descriptor to be written to MS memory. */
  1777. /* dma-desc-cmd layout:
  1778. * 0-3: dma-desc-cmd 0-3
  1779. * 4-7: pcid function number
  1780. * 8-15: dma-desc-cmd 8-15
  1781. */
  1782. dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
  1783. dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
  1784. dma_desc.dma_bus_addr = rdmem_dma;
  1785. size = 0;
  1786. read_size = 0;
  1787. /*
  1788. * Perform rdmem operation using pex-dma.
  1789. * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE.
  1790. */
  1791. while (read_size < m_hdr->read_data_size) {
  1792. if (m_hdr->read_data_size - read_size >=
  1793. QLA83XX_PEX_DMA_READ_SIZE)
  1794. size = QLA83XX_PEX_DMA_READ_SIZE;
  1795. else {
  1796. size = (m_hdr->read_data_size - read_size);
  1797. if (rdmem_buffer)
  1798. dma_free_coherent(&ha->pdev->dev,
  1799. QLA83XX_PEX_DMA_READ_SIZE,
  1800. rdmem_buffer, rdmem_dma);
  1801. rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size,
  1802. &rdmem_dma,
  1803. GFP_KERNEL);
  1804. if (!rdmem_buffer) {
  1805. DEBUG2(ql4_printk(KERN_INFO, ha,
  1806. "%s: Unable to allocate rdmem dma buffer\n",
  1807. __func__));
  1808. return QLA_ERROR;
  1809. }
  1810. dma_desc.dma_bus_addr = rdmem_dma;
  1811. }
  1812. dma_desc.src_addr = m_hdr->read_addr + read_size;
  1813. dma_desc.cmd.read_data_size = size;
  1814. /* Prepare: Write pex-dma descriptor to MS memory. */
  1815. rval = qla4_8xxx_ms_mem_write_128b(ha,
  1816. (uint64_t)m_hdr->desc_card_addr,
  1817. (uint32_t *)&dma_desc,
  1818. (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
  1819. if (rval != QLA_SUCCESS) {
  1820. ql4_printk(KERN_INFO, ha,
  1821. "%s: Error writing rdmem-dma-init to MS !!!\n",
  1822. __func__);
  1823. goto error_exit;
  1824. }
  1825. DEBUG2(ql4_printk(KERN_INFO, ha,
  1826. "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n",
  1827. __func__, size));
  1828. /* Execute: Start pex-dma operation. */
  1829. rval = qla4_83xx_start_pex_dma(ha, m_hdr);
  1830. if (rval != QLA_SUCCESS) {
  1831. DEBUG2(ql4_printk(KERN_INFO, ha,
  1832. "scsi(%ld): start-pex-dma failed rval=0x%x\n",
  1833. ha->host_no, rval));
  1834. goto error_exit;
  1835. }
  1836. memcpy(data_ptr, rdmem_buffer, size);
  1837. data_ptr += size;
  1838. read_size += size;
  1839. }
  1840. DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
  1841. *d_ptr = (uint32_t *)data_ptr;
  1842. error_exit:
  1843. if (rdmem_buffer)
  1844. dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer,
  1845. rdmem_dma);
  1846. return rval;
  1847. }
  1848. static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
  1849. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  1850. uint32_t **d_ptr)
  1851. {
  1852. uint32_t addr, r_addr, c_addr, t_r_addr;
  1853. uint32_t i, k, loop_count, t_value, r_cnt, r_value;
  1854. unsigned long p_wait, w_time, p_mask;
  1855. uint32_t c_value_w, c_value_r;
  1856. struct qla8xxx_minidump_entry_cache *cache_hdr;
  1857. int rval = QLA_ERROR;
  1858. uint32_t *data_ptr = *d_ptr;
  1859. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  1860. cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
  1861. loop_count = cache_hdr->op_count;
  1862. r_addr = cache_hdr->read_addr;
  1863. c_addr = cache_hdr->control_addr;
  1864. c_value_w = cache_hdr->cache_ctrl.write_value;
  1865. t_r_addr = cache_hdr->tag_reg_addr;
  1866. t_value = cache_hdr->addr_ctrl.init_tag_value;
  1867. r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
  1868. p_wait = cache_hdr->cache_ctrl.poll_wait;
  1869. p_mask = cache_hdr->cache_ctrl.poll_mask;
  1870. for (i = 0; i < loop_count; i++) {
  1871. ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
  1872. if (c_value_w)
  1873. ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
  1874. if (p_mask) {
  1875. w_time = jiffies + p_wait;
  1876. do {
  1877. ha->isp_ops->rd_reg_indirect(ha, c_addr,
  1878. &c_value_r);
  1879. if ((c_value_r & p_mask) == 0) {
  1880. break;
  1881. } else if (time_after_eq(jiffies, w_time)) {
  1882. /* capturing dump failed */
  1883. return rval;
  1884. }
  1885. } while (1);
  1886. }
  1887. addr = r_addr;
  1888. for (k = 0; k < r_cnt; k++) {
  1889. ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
  1890. *data_ptr++ = cpu_to_le32(r_value);
  1891. addr += cache_hdr->read_ctrl.read_addr_stride;
  1892. }
  1893. t_value += cache_hdr->addr_ctrl.tag_value_stride;
  1894. }
  1895. *d_ptr = data_ptr;
  1896. return QLA_SUCCESS;
  1897. }
  1898. static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
  1899. struct qla8xxx_minidump_entry_hdr *entry_hdr)
  1900. {
  1901. struct qla8xxx_minidump_entry_crb *crb_entry;
  1902. uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
  1903. uint32_t crb_addr;
  1904. unsigned long wtime;
  1905. struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
  1906. int i;
  1907. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  1908. tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
  1909. ha->fw_dump_tmplt_hdr;
  1910. crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
  1911. crb_addr = crb_entry->addr;
  1912. for (i = 0; i < crb_entry->op_count; i++) {
  1913. opcode = crb_entry->crb_ctrl.opcode;
  1914. if (opcode & QLA8XXX_DBG_OPCODE_WR) {
  1915. ha->isp_ops->wr_reg_indirect(ha, crb_addr,
  1916. crb_entry->value_1);
  1917. opcode &= ~QLA8XXX_DBG_OPCODE_WR;
  1918. }
  1919. if (opcode & QLA8XXX_DBG_OPCODE_RW) {
  1920. ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
  1921. ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
  1922. opcode &= ~QLA8XXX_DBG_OPCODE_RW;
  1923. }
  1924. if (opcode & QLA8XXX_DBG_OPCODE_AND) {
  1925. ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
  1926. read_value &= crb_entry->value_2;
  1927. opcode &= ~QLA8XXX_DBG_OPCODE_AND;
  1928. if (opcode & QLA8XXX_DBG_OPCODE_OR) {
  1929. read_value |= crb_entry->value_3;
  1930. opcode &= ~QLA8XXX_DBG_OPCODE_OR;
  1931. }
  1932. ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
  1933. }
  1934. if (opcode & QLA8XXX_DBG_OPCODE_OR) {
  1935. ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
  1936. read_value |= crb_entry->value_3;
  1937. ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
  1938. opcode &= ~QLA8XXX_DBG_OPCODE_OR;
  1939. }
  1940. if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
  1941. poll_time = crb_entry->crb_strd.poll_timeout;
  1942. wtime = jiffies + poll_time;
  1943. ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
  1944. do {
  1945. if ((read_value & crb_entry->value_2) ==
  1946. crb_entry->value_1) {
  1947. break;
  1948. } else if (time_after_eq(jiffies, wtime)) {
  1949. /* capturing dump failed */
  1950. rval = QLA_ERROR;
  1951. break;
  1952. } else {
  1953. ha->isp_ops->rd_reg_indirect(ha,
  1954. crb_addr, &read_value);
  1955. }
  1956. } while (1);
  1957. opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
  1958. }
  1959. if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
  1960. if (crb_entry->crb_strd.state_index_a) {
  1961. index = crb_entry->crb_strd.state_index_a;
  1962. addr = tmplt_hdr->saved_state_array[index];
  1963. } else {
  1964. addr = crb_addr;
  1965. }
  1966. ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
  1967. index = crb_entry->crb_ctrl.state_index_v;
  1968. tmplt_hdr->saved_state_array[index] = read_value;
  1969. opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
  1970. }
  1971. if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
  1972. if (crb_entry->crb_strd.state_index_a) {
  1973. index = crb_entry->crb_strd.state_index_a;
  1974. addr = tmplt_hdr->saved_state_array[index];
  1975. } else {
  1976. addr = crb_addr;
  1977. }
  1978. if (crb_entry->crb_ctrl.state_index_v) {
  1979. index = crb_entry->crb_ctrl.state_index_v;
  1980. read_value =
  1981. tmplt_hdr->saved_state_array[index];
  1982. } else {
  1983. read_value = crb_entry->value_1;
  1984. }
  1985. ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
  1986. opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
  1987. }
  1988. if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
  1989. index = crb_entry->crb_ctrl.state_index_v;
  1990. read_value = tmplt_hdr->saved_state_array[index];
  1991. read_value <<= crb_entry->crb_ctrl.shl;
  1992. read_value >>= crb_entry->crb_ctrl.shr;
  1993. if (crb_entry->value_2)
  1994. read_value &= crb_entry->value_2;
  1995. read_value |= crb_entry->value_3;
  1996. read_value += crb_entry->value_1;
  1997. tmplt_hdr->saved_state_array[index] = read_value;
  1998. opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
  1999. }
  2000. crb_addr += crb_entry->crb_strd.addr_stride;
  2001. }
  2002. DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
  2003. return rval;
  2004. }
  2005. static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
  2006. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2007. uint32_t **d_ptr)
  2008. {
  2009. uint32_t r_addr, r_stride, loop_cnt, i, r_value;
  2010. struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
  2011. uint32_t *data_ptr = *d_ptr;
  2012. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  2013. ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
  2014. r_addr = ocm_hdr->read_addr;
  2015. r_stride = ocm_hdr->read_addr_stride;
  2016. loop_cnt = ocm_hdr->op_count;
  2017. DEBUG2(ql4_printk(KERN_INFO, ha,
  2018. "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
  2019. __func__, r_addr, r_stride, loop_cnt));
  2020. for (i = 0; i < loop_cnt; i++) {
  2021. r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
  2022. *data_ptr++ = cpu_to_le32(r_value);
  2023. r_addr += r_stride;
  2024. }
  2025. DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
  2026. __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
  2027. *d_ptr = data_ptr;
  2028. }
  2029. static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
  2030. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2031. uint32_t **d_ptr)
  2032. {
  2033. uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
  2034. struct qla8xxx_minidump_entry_mux *mux_hdr;
  2035. uint32_t *data_ptr = *d_ptr;
  2036. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  2037. mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
  2038. r_addr = mux_hdr->read_addr;
  2039. s_addr = mux_hdr->select_addr;
  2040. s_stride = mux_hdr->select_value_stride;
  2041. s_value = mux_hdr->select_value;
  2042. loop_cnt = mux_hdr->op_count;
  2043. for (i = 0; i < loop_cnt; i++) {
  2044. ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
  2045. ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
  2046. *data_ptr++ = cpu_to_le32(s_value);
  2047. *data_ptr++ = cpu_to_le32(r_value);
  2048. s_value += s_stride;
  2049. }
  2050. *d_ptr = data_ptr;
  2051. }
  2052. static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
  2053. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2054. uint32_t **d_ptr)
  2055. {
  2056. uint32_t addr, r_addr, c_addr, t_r_addr;
  2057. uint32_t i, k, loop_count, t_value, r_cnt, r_value;
  2058. uint32_t c_value_w;
  2059. struct qla8xxx_minidump_entry_cache *cache_hdr;
  2060. uint32_t *data_ptr = *d_ptr;
  2061. cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
  2062. loop_count = cache_hdr->op_count;
  2063. r_addr = cache_hdr->read_addr;
  2064. c_addr = cache_hdr->control_addr;
  2065. c_value_w = cache_hdr->cache_ctrl.write_value;
  2066. t_r_addr = cache_hdr->tag_reg_addr;
  2067. t_value = cache_hdr->addr_ctrl.init_tag_value;
  2068. r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
  2069. for (i = 0; i < loop_count; i++) {
  2070. ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
  2071. ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
  2072. addr = r_addr;
  2073. for (k = 0; k < r_cnt; k++) {
  2074. ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
  2075. *data_ptr++ = cpu_to_le32(r_value);
  2076. addr += cache_hdr->read_ctrl.read_addr_stride;
  2077. }
  2078. t_value += cache_hdr->addr_ctrl.tag_value_stride;
  2079. }
  2080. *d_ptr = data_ptr;
  2081. }
  2082. static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
  2083. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2084. uint32_t **d_ptr)
  2085. {
  2086. uint32_t s_addr, r_addr;
  2087. uint32_t r_stride, r_value, r_cnt, qid = 0;
  2088. uint32_t i, k, loop_cnt;
  2089. struct qla8xxx_minidump_entry_queue *q_hdr;
  2090. uint32_t *data_ptr = *d_ptr;
  2091. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  2092. q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
  2093. s_addr = q_hdr->select_addr;
  2094. r_cnt = q_hdr->rd_strd.read_addr_cnt;
  2095. r_stride = q_hdr->rd_strd.read_addr_stride;
  2096. loop_cnt = q_hdr->op_count;
  2097. for (i = 0; i < loop_cnt; i++) {
  2098. ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
  2099. r_addr = q_hdr->read_addr;
  2100. for (k = 0; k < r_cnt; k++) {
  2101. ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
  2102. *data_ptr++ = cpu_to_le32(r_value);
  2103. r_addr += r_stride;
  2104. }
  2105. qid += q_hdr->q_strd.queue_id_stride;
  2106. }
  2107. *d_ptr = data_ptr;
  2108. }
  2109. #define MD_DIRECT_ROM_WINDOW 0x42110030
  2110. #define MD_DIRECT_ROM_READ_BASE 0x42150000
  2111. static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
  2112. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2113. uint32_t **d_ptr)
  2114. {
  2115. uint32_t r_addr, r_value;
  2116. uint32_t i, loop_cnt;
  2117. struct qla8xxx_minidump_entry_rdrom *rom_hdr;
  2118. uint32_t *data_ptr = *d_ptr;
  2119. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  2120. rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
  2121. r_addr = rom_hdr->read_addr;
  2122. loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
  2123. DEBUG2(ql4_printk(KERN_INFO, ha,
  2124. "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
  2125. __func__, r_addr, loop_cnt));
  2126. for (i = 0; i < loop_cnt; i++) {
  2127. ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
  2128. (r_addr & 0xFFFF0000));
  2129. ha->isp_ops->rd_reg_indirect(ha,
  2130. MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
  2131. &r_value);
  2132. *data_ptr++ = cpu_to_le32(r_value);
  2133. r_addr += sizeof(uint32_t);
  2134. }
  2135. *d_ptr = data_ptr;
  2136. }
  2137. #define MD_MIU_TEST_AGT_CTRL 0x41000090
  2138. #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
  2139. #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
  2140. static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
  2141. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2142. uint32_t **d_ptr)
  2143. {
  2144. uint32_t r_addr, r_value, r_data;
  2145. uint32_t i, j, loop_cnt;
  2146. struct qla8xxx_minidump_entry_rdmem *m_hdr;
  2147. unsigned long flags;
  2148. uint32_t *data_ptr = *d_ptr;
  2149. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  2150. m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
  2151. r_addr = m_hdr->read_addr;
  2152. loop_cnt = m_hdr->read_data_size/16;
  2153. DEBUG2(ql4_printk(KERN_INFO, ha,
  2154. "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
  2155. __func__, r_addr, m_hdr->read_data_size));
  2156. if (r_addr & 0xf) {
  2157. DEBUG2(ql4_printk(KERN_INFO, ha,
  2158. "[%s]: Read addr 0x%x not 16 bytes aligned\n",
  2159. __func__, r_addr));
  2160. return QLA_ERROR;
  2161. }
  2162. if (m_hdr->read_data_size % 16) {
  2163. DEBUG2(ql4_printk(KERN_INFO, ha,
  2164. "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
  2165. __func__, m_hdr->read_data_size));
  2166. return QLA_ERROR;
  2167. }
  2168. DEBUG2(ql4_printk(KERN_INFO, ha,
  2169. "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
  2170. __func__, r_addr, m_hdr->read_data_size, loop_cnt));
  2171. write_lock_irqsave(&ha->hw_lock, flags);
  2172. for (i = 0; i < loop_cnt; i++) {
  2173. ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
  2174. r_addr);
  2175. r_value = 0;
  2176. ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
  2177. r_value);
  2178. r_value = MIU_TA_CTL_ENABLE;
  2179. ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
  2180. r_value = MIU_TA_CTL_START_ENABLE;
  2181. ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
  2182. for (j = 0; j < MAX_CTL_CHECK; j++) {
  2183. ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
  2184. &r_value);
  2185. if ((r_value & MIU_TA_CTL_BUSY) == 0)
  2186. break;
  2187. }
  2188. if (j >= MAX_CTL_CHECK) {
  2189. printk_ratelimited(KERN_ERR
  2190. "%s: failed to read through agent\n",
  2191. __func__);
  2192. write_unlock_irqrestore(&ha->hw_lock, flags);
  2193. return QLA_SUCCESS;
  2194. }
  2195. for (j = 0; j < 4; j++) {
  2196. ha->isp_ops->rd_reg_indirect(ha,
  2197. MD_MIU_TEST_AGT_RDDATA[j],
  2198. &r_data);
  2199. *data_ptr++ = cpu_to_le32(r_data);
  2200. }
  2201. r_addr += 16;
  2202. }
  2203. write_unlock_irqrestore(&ha->hw_lock, flags);
  2204. DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
  2205. __func__, (loop_cnt * 16)));
  2206. *d_ptr = data_ptr;
  2207. return QLA_SUCCESS;
  2208. }
  2209. static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
  2210. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2211. uint32_t **d_ptr)
  2212. {
  2213. uint32_t *data_ptr = *d_ptr;
  2214. int rval = QLA_SUCCESS;
  2215. rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr);
  2216. if (rval != QLA_SUCCESS)
  2217. rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
  2218. &data_ptr);
  2219. *d_ptr = data_ptr;
  2220. return rval;
  2221. }
  2222. static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
  2223. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2224. int index)
  2225. {
  2226. entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
  2227. DEBUG2(ql4_printk(KERN_INFO, ha,
  2228. "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
  2229. ha->host_no, index, entry_hdr->entry_type,
  2230. entry_hdr->d_ctrl.entry_capture_mask));
  2231. /* If driver encounters a new entry type that it cannot process,
  2232. * it should just skip the entry and adjust the total buffer size by
  2233. * from subtracting the skipped bytes from it
  2234. */
  2235. ha->fw_dump_skip_size += entry_hdr->entry_capture_size;
  2236. }
  2237. /* ISP83xx functions to process new minidump entries... */
  2238. static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
  2239. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2240. uint32_t **d_ptr)
  2241. {
  2242. uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
  2243. uint16_t s_stride, i;
  2244. uint32_t *data_ptr = *d_ptr;
  2245. uint32_t rval = QLA_SUCCESS;
  2246. struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
  2247. pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
  2248. s_addr = le32_to_cpu(pollrd_hdr->select_addr);
  2249. r_addr = le32_to_cpu(pollrd_hdr->read_addr);
  2250. s_value = le32_to_cpu(pollrd_hdr->select_value);
  2251. s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
  2252. poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
  2253. poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
  2254. for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
  2255. ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
  2256. poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
  2257. while (1) {
  2258. ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
  2259. if ((r_value & poll_mask) != 0) {
  2260. break;
  2261. } else {
  2262. msleep(1);
  2263. if (--poll_wait == 0) {
  2264. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
  2265. __func__);
  2266. rval = QLA_ERROR;
  2267. goto exit_process_pollrd;
  2268. }
  2269. }
  2270. }
  2271. ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
  2272. *data_ptr++ = cpu_to_le32(s_value);
  2273. *data_ptr++ = cpu_to_le32(r_value);
  2274. s_value += s_stride;
  2275. }
  2276. *d_ptr = data_ptr;
  2277. exit_process_pollrd:
  2278. return rval;
  2279. }
  2280. static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha,
  2281. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2282. uint32_t **d_ptr)
  2283. {
  2284. int loop_cnt;
  2285. uint32_t addr1, addr2, value, data, temp, wrval;
  2286. uint8_t stride, stride2;
  2287. uint16_t count;
  2288. uint32_t poll, mask, modify_mask;
  2289. uint32_t wait_count = 0;
  2290. uint32_t *data_ptr = *d_ptr;
  2291. struct qla8044_minidump_entry_rddfe *rddfe;
  2292. uint32_t rval = QLA_SUCCESS;
  2293. rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr;
  2294. addr1 = le32_to_cpu(rddfe->addr_1);
  2295. value = le32_to_cpu(rddfe->value);
  2296. stride = le32_to_cpu(rddfe->stride);
  2297. stride2 = le32_to_cpu(rddfe->stride2);
  2298. count = le32_to_cpu(rddfe->count);
  2299. poll = le32_to_cpu(rddfe->poll);
  2300. mask = le32_to_cpu(rddfe->mask);
  2301. modify_mask = le32_to_cpu(rddfe->modify_mask);
  2302. addr2 = addr1 + stride;
  2303. for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
  2304. ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value));
  2305. wait_count = 0;
  2306. while (wait_count < poll) {
  2307. ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
  2308. if ((temp & mask) != 0)
  2309. break;
  2310. wait_count++;
  2311. }
  2312. if (wait_count == poll) {
  2313. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
  2314. rval = QLA_ERROR;
  2315. goto exit_process_rddfe;
  2316. } else {
  2317. ha->isp_ops->rd_reg_indirect(ha, addr2, &temp);
  2318. temp = temp & modify_mask;
  2319. temp = (temp | ((loop_cnt << 16) | loop_cnt));
  2320. wrval = ((temp << 16) | temp);
  2321. ha->isp_ops->wr_reg_indirect(ha, addr2, wrval);
  2322. ha->isp_ops->wr_reg_indirect(ha, addr1, value);
  2323. wait_count = 0;
  2324. while (wait_count < poll) {
  2325. ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
  2326. if ((temp & mask) != 0)
  2327. break;
  2328. wait_count++;
  2329. }
  2330. if (wait_count == poll) {
  2331. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
  2332. __func__);
  2333. rval = QLA_ERROR;
  2334. goto exit_process_rddfe;
  2335. }
  2336. ha->isp_ops->wr_reg_indirect(ha, addr1,
  2337. ((0x40000000 | value) +
  2338. stride2));
  2339. wait_count = 0;
  2340. while (wait_count < poll) {
  2341. ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
  2342. if ((temp & mask) != 0)
  2343. break;
  2344. wait_count++;
  2345. }
  2346. if (wait_count == poll) {
  2347. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
  2348. __func__);
  2349. rval = QLA_ERROR;
  2350. goto exit_process_rddfe;
  2351. }
  2352. ha->isp_ops->rd_reg_indirect(ha, addr2, &data);
  2353. *data_ptr++ = cpu_to_le32(wrval);
  2354. *data_ptr++ = cpu_to_le32(data);
  2355. }
  2356. }
  2357. *d_ptr = data_ptr;
  2358. exit_process_rddfe:
  2359. return rval;
  2360. }
  2361. static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha,
  2362. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2363. uint32_t **d_ptr)
  2364. {
  2365. int rval = QLA_SUCCESS;
  2366. uint32_t addr1, addr2, value1, value2, data, selval;
  2367. uint8_t stride1, stride2;
  2368. uint32_t addr3, addr4, addr5, addr6, addr7;
  2369. uint16_t count, loop_cnt;
  2370. uint32_t mask;
  2371. uint32_t *data_ptr = *d_ptr;
  2372. struct qla8044_minidump_entry_rdmdio *rdmdio;
  2373. rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr;
  2374. addr1 = le32_to_cpu(rdmdio->addr_1);
  2375. addr2 = le32_to_cpu(rdmdio->addr_2);
  2376. value1 = le32_to_cpu(rdmdio->value_1);
  2377. stride1 = le32_to_cpu(rdmdio->stride_1);
  2378. stride2 = le32_to_cpu(rdmdio->stride_2);
  2379. count = le32_to_cpu(rdmdio->count);
  2380. mask = le32_to_cpu(rdmdio->mask);
  2381. value2 = le32_to_cpu(rdmdio->value_2);
  2382. addr3 = addr1 + stride1;
  2383. for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
  2384. rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
  2385. addr3, mask);
  2386. if (rval)
  2387. goto exit_process_rdmdio;
  2388. addr4 = addr2 - stride1;
  2389. rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4,
  2390. value2);
  2391. if (rval)
  2392. goto exit_process_rdmdio;
  2393. addr5 = addr2 - (2 * stride1);
  2394. rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5,
  2395. value1);
  2396. if (rval)
  2397. goto exit_process_rdmdio;
  2398. addr6 = addr2 - (3 * stride1);
  2399. rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask,
  2400. addr6, 0x2);
  2401. if (rval)
  2402. goto exit_process_rdmdio;
  2403. rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
  2404. addr3, mask);
  2405. if (rval)
  2406. goto exit_process_rdmdio;
  2407. addr7 = addr2 - (4 * stride1);
  2408. rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3,
  2409. mask, addr7, &data);
  2410. if (rval)
  2411. goto exit_process_rdmdio;
  2412. selval = (value2 << 18) | (value1 << 2) | 2;
  2413. stride2 = le32_to_cpu(rdmdio->stride_2);
  2414. *data_ptr++ = cpu_to_le32(selval);
  2415. *data_ptr++ = cpu_to_le32(data);
  2416. value1 = value1 + stride2;
  2417. *d_ptr = data_ptr;
  2418. }
  2419. exit_process_rdmdio:
  2420. return rval;
  2421. }
  2422. static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha,
  2423. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2424. uint32_t **d_ptr)
  2425. {
  2426. uint32_t addr1, addr2, value1, value2, poll, r_value;
  2427. struct qla8044_minidump_entry_pollwr *pollwr_hdr;
  2428. uint32_t wait_count = 0;
  2429. uint32_t rval = QLA_SUCCESS;
  2430. pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
  2431. addr1 = le32_to_cpu(pollwr_hdr->addr_1);
  2432. addr2 = le32_to_cpu(pollwr_hdr->addr_2);
  2433. value1 = le32_to_cpu(pollwr_hdr->value_1);
  2434. value2 = le32_to_cpu(pollwr_hdr->value_2);
  2435. poll = le32_to_cpu(pollwr_hdr->poll);
  2436. while (wait_count < poll) {
  2437. ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
  2438. if ((r_value & poll) != 0)
  2439. break;
  2440. wait_count++;
  2441. }
  2442. if (wait_count == poll) {
  2443. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
  2444. rval = QLA_ERROR;
  2445. goto exit_process_pollwr;
  2446. }
  2447. ha->isp_ops->wr_reg_indirect(ha, addr2, value2);
  2448. ha->isp_ops->wr_reg_indirect(ha, addr1, value1);
  2449. wait_count = 0;
  2450. while (wait_count < poll) {
  2451. ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
  2452. if ((r_value & poll) != 0)
  2453. break;
  2454. wait_count++;
  2455. }
  2456. exit_process_pollwr:
  2457. return rval;
  2458. }
  2459. static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
  2460. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2461. uint32_t **d_ptr)
  2462. {
  2463. uint32_t sel_val1, sel_val2, t_sel_val, data, i;
  2464. uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
  2465. struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
  2466. uint32_t *data_ptr = *d_ptr;
  2467. rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
  2468. sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
  2469. sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
  2470. sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
  2471. sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
  2472. sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
  2473. read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
  2474. for (i = 0; i < rdmux2_hdr->op_count; i++) {
  2475. ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
  2476. t_sel_val = sel_val1 & sel_val_mask;
  2477. *data_ptr++ = cpu_to_le32(t_sel_val);
  2478. ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
  2479. ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
  2480. *data_ptr++ = cpu_to_le32(data);
  2481. ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
  2482. t_sel_val = sel_val2 & sel_val_mask;
  2483. *data_ptr++ = cpu_to_le32(t_sel_val);
  2484. ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
  2485. ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
  2486. *data_ptr++ = cpu_to_le32(data);
  2487. sel_val1 += rdmux2_hdr->select_value_stride;
  2488. sel_val2 += rdmux2_hdr->select_value_stride;
  2489. }
  2490. *d_ptr = data_ptr;
  2491. }
  2492. static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
  2493. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2494. uint32_t **d_ptr)
  2495. {
  2496. uint32_t poll_wait, poll_mask, r_value, data;
  2497. uint32_t addr_1, addr_2, value_1, value_2;
  2498. uint32_t *data_ptr = *d_ptr;
  2499. uint32_t rval = QLA_SUCCESS;
  2500. struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
  2501. poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
  2502. addr_1 = le32_to_cpu(poll_hdr->addr_1);
  2503. addr_2 = le32_to_cpu(poll_hdr->addr_2);
  2504. value_1 = le32_to_cpu(poll_hdr->value_1);
  2505. value_2 = le32_to_cpu(poll_hdr->value_2);
  2506. poll_mask = le32_to_cpu(poll_hdr->poll_mask);
  2507. ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
  2508. poll_wait = le32_to_cpu(poll_hdr->poll_wait);
  2509. while (1) {
  2510. ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
  2511. if ((r_value & poll_mask) != 0) {
  2512. break;
  2513. } else {
  2514. msleep(1);
  2515. if (--poll_wait == 0) {
  2516. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
  2517. __func__);
  2518. rval = QLA_ERROR;
  2519. goto exit_process_pollrdmwr;
  2520. }
  2521. }
  2522. }
  2523. ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
  2524. data &= le32_to_cpu(poll_hdr->modify_mask);
  2525. ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
  2526. ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
  2527. poll_wait = le32_to_cpu(poll_hdr->poll_wait);
  2528. while (1) {
  2529. ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
  2530. if ((r_value & poll_mask) != 0) {
  2531. break;
  2532. } else {
  2533. msleep(1);
  2534. if (--poll_wait == 0) {
  2535. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
  2536. __func__);
  2537. rval = QLA_ERROR;
  2538. goto exit_process_pollrdmwr;
  2539. }
  2540. }
  2541. }
  2542. *data_ptr++ = cpu_to_le32(addr_2);
  2543. *data_ptr++ = cpu_to_le32(data);
  2544. *d_ptr = data_ptr;
  2545. exit_process_pollrdmwr:
  2546. return rval;
  2547. }
  2548. static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
  2549. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2550. uint32_t **d_ptr)
  2551. {
  2552. uint32_t fl_addr, u32_count, rval;
  2553. struct qla8xxx_minidump_entry_rdrom *rom_hdr;
  2554. uint32_t *data_ptr = *d_ptr;
  2555. rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
  2556. fl_addr = le32_to_cpu(rom_hdr->read_addr);
  2557. u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
  2558. DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
  2559. __func__, fl_addr, u32_count));
  2560. rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
  2561. (u8 *)(data_ptr), u32_count);
  2562. if (rval == QLA_ERROR) {
  2563. ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
  2564. __func__, u32_count);
  2565. goto exit_process_rdrom;
  2566. }
  2567. data_ptr += u32_count;
  2568. *d_ptr = data_ptr;
  2569. exit_process_rdrom:
  2570. return rval;
  2571. }
  2572. /**
  2573. * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
  2574. * @ha: pointer to adapter structure
  2575. **/
  2576. static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
  2577. {
  2578. int num_entry_hdr = 0;
  2579. struct qla8xxx_minidump_entry_hdr *entry_hdr;
  2580. struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
  2581. uint32_t *data_ptr;
  2582. uint32_t data_collected = 0;
  2583. int i, rval = QLA_ERROR;
  2584. uint64_t now;
  2585. uint32_t timestamp;
  2586. ha->fw_dump_skip_size = 0;
  2587. if (!ha->fw_dump) {
  2588. ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
  2589. __func__, ha->host_no);
  2590. return rval;
  2591. }
  2592. tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
  2593. ha->fw_dump_tmplt_hdr;
  2594. data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
  2595. ha->fw_dump_tmplt_size);
  2596. data_collected += ha->fw_dump_tmplt_size;
  2597. num_entry_hdr = tmplt_hdr->num_of_entries;
  2598. ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
  2599. __func__, data_ptr);
  2600. ql4_printk(KERN_INFO, ha,
  2601. "[%s]: no of entry headers in Template: 0x%x\n",
  2602. __func__, num_entry_hdr);
  2603. ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
  2604. __func__, ha->fw_dump_capture_mask);
  2605. ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
  2606. __func__, ha->fw_dump_size, ha->fw_dump_size);
  2607. /* Update current timestamp before taking dump */
  2608. now = get_jiffies_64();
  2609. timestamp = (u32)(jiffies_to_msecs(now) / 1000);
  2610. tmplt_hdr->driver_timestamp = timestamp;
  2611. entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
  2612. (((uint8_t *)ha->fw_dump_tmplt_hdr) +
  2613. tmplt_hdr->first_entry_offset);
  2614. if (is_qla8032(ha) || is_qla8042(ha))
  2615. tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
  2616. tmplt_hdr->ocm_window_reg[ha->func_num];
  2617. /* Walk through the entry headers - validate/perform required action */
  2618. for (i = 0; i < num_entry_hdr; i++) {
  2619. if (data_collected > ha->fw_dump_size) {
  2620. ql4_printk(KERN_INFO, ha,
  2621. "Data collected: [0x%x], Total Dump size: [0x%x]\n",
  2622. data_collected, ha->fw_dump_size);
  2623. return rval;
  2624. }
  2625. if (!(entry_hdr->d_ctrl.entry_capture_mask &
  2626. ha->fw_dump_capture_mask)) {
  2627. entry_hdr->d_ctrl.driver_flags |=
  2628. QLA8XXX_DBG_SKIPPED_FLAG;
  2629. goto skip_nxt_entry;
  2630. }
  2631. DEBUG2(ql4_printk(KERN_INFO, ha,
  2632. "Data collected: [0x%x], Dump size left:[0x%x]\n",
  2633. data_collected,
  2634. (ha->fw_dump_size - data_collected)));
  2635. /* Decode the entry type and take required action to capture
  2636. * debug data
  2637. */
  2638. switch (entry_hdr->entry_type) {
  2639. case QLA8XXX_RDEND:
  2640. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2641. break;
  2642. case QLA8XXX_CNTRL:
  2643. rval = qla4_8xxx_minidump_process_control(ha,
  2644. entry_hdr);
  2645. if (rval != QLA_SUCCESS) {
  2646. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2647. goto md_failed;
  2648. }
  2649. break;
  2650. case QLA8XXX_RDCRB:
  2651. qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
  2652. &data_ptr);
  2653. break;
  2654. case QLA8XXX_RDMEM:
  2655. rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
  2656. &data_ptr);
  2657. if (rval != QLA_SUCCESS) {
  2658. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2659. goto md_failed;
  2660. }
  2661. break;
  2662. case QLA8XXX_BOARD:
  2663. case QLA8XXX_RDROM:
  2664. if (is_qla8022(ha)) {
  2665. qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
  2666. &data_ptr);
  2667. } else if (is_qla8032(ha) || is_qla8042(ha)) {
  2668. rval = qla4_83xx_minidump_process_rdrom(ha,
  2669. entry_hdr,
  2670. &data_ptr);
  2671. if (rval != QLA_SUCCESS)
  2672. qla4_8xxx_mark_entry_skipped(ha,
  2673. entry_hdr,
  2674. i);
  2675. }
  2676. break;
  2677. case QLA8XXX_L2DTG:
  2678. case QLA8XXX_L2ITG:
  2679. case QLA8XXX_L2DAT:
  2680. case QLA8XXX_L2INS:
  2681. rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
  2682. &data_ptr);
  2683. if (rval != QLA_SUCCESS) {
  2684. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2685. goto md_failed;
  2686. }
  2687. break;
  2688. case QLA8XXX_L1DTG:
  2689. case QLA8XXX_L1ITG:
  2690. case QLA8XXX_L1DAT:
  2691. case QLA8XXX_L1INS:
  2692. qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
  2693. &data_ptr);
  2694. break;
  2695. case QLA8XXX_RDOCM:
  2696. qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
  2697. &data_ptr);
  2698. break;
  2699. case QLA8XXX_RDMUX:
  2700. qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
  2701. &data_ptr);
  2702. break;
  2703. case QLA8XXX_QUEUE:
  2704. qla4_8xxx_minidump_process_queue(ha, entry_hdr,
  2705. &data_ptr);
  2706. break;
  2707. case QLA83XX_POLLRD:
  2708. if (is_qla8022(ha)) {
  2709. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2710. break;
  2711. }
  2712. rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
  2713. &data_ptr);
  2714. if (rval != QLA_SUCCESS)
  2715. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2716. break;
  2717. case QLA83XX_RDMUX2:
  2718. if (is_qla8022(ha)) {
  2719. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2720. break;
  2721. }
  2722. qla83xx_minidump_process_rdmux2(ha, entry_hdr,
  2723. &data_ptr);
  2724. break;
  2725. case QLA83XX_POLLRDMWR:
  2726. if (is_qla8022(ha)) {
  2727. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2728. break;
  2729. }
  2730. rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
  2731. &data_ptr);
  2732. if (rval != QLA_SUCCESS)
  2733. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2734. break;
  2735. case QLA8044_RDDFE:
  2736. rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr,
  2737. &data_ptr);
  2738. if (rval != QLA_SUCCESS)
  2739. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2740. break;
  2741. case QLA8044_RDMDIO:
  2742. rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr,
  2743. &data_ptr);
  2744. if (rval != QLA_SUCCESS)
  2745. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2746. break;
  2747. case QLA8044_POLLWR:
  2748. rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr,
  2749. &data_ptr);
  2750. if (rval != QLA_SUCCESS)
  2751. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2752. break;
  2753. case QLA8XXX_RDNOP:
  2754. default:
  2755. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2756. break;
  2757. }
  2758. data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;
  2759. skip_nxt_entry:
  2760. /* next entry in the template */
  2761. entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
  2762. (((uint8_t *)entry_hdr) +
  2763. entry_hdr->entry_size);
  2764. }
  2765. if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) {
  2766. ql4_printk(KERN_INFO, ha,
  2767. "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
  2768. data_collected, ha->fw_dump_size);
  2769. rval = QLA_ERROR;
  2770. goto md_failed;
  2771. }
  2772. DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
  2773. __func__, i));
  2774. md_failed:
  2775. return rval;
  2776. }
  2777. /**
  2778. * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
  2779. * @ha: pointer to adapter structure
  2780. * @code: uevent code to act upon
  2781. **/
  2782. static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
  2783. {
  2784. char event_string[40];
  2785. char *envp[] = { event_string, NULL };
  2786. switch (code) {
  2787. case QL4_UEVENT_CODE_FW_DUMP:
  2788. snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
  2789. ha->host_no);
  2790. break;
  2791. default:
  2792. /*do nothing*/
  2793. break;
  2794. }
  2795. kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
  2796. }
  2797. void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
  2798. {
  2799. if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
  2800. !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
  2801. if (!qla4_8xxx_collect_md_data(ha)) {
  2802. qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
  2803. set_bit(AF_82XX_FW_DUMPED, &ha->flags);
  2804. } else {
  2805. ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
  2806. __func__);
  2807. }
  2808. }
  2809. }
  2810. /**
  2811. * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
  2812. * @ha: pointer to adapter structure
  2813. *
  2814. * Note: IDC lock must be held upon entry
  2815. **/
  2816. int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
  2817. {
  2818. int rval = QLA_ERROR;
  2819. int i;
  2820. uint32_t old_count, count;
  2821. int need_reset = 0;
  2822. need_reset = ha->isp_ops->need_reset(ha);
  2823. if (need_reset) {
  2824. /* We are trying to perform a recovery here. */
  2825. if (test_bit(AF_FW_RECOVERY, &ha->flags))
  2826. ha->isp_ops->rom_lock_recovery(ha);
  2827. } else {
  2828. old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
  2829. for (i = 0; i < 10; i++) {
  2830. msleep(200);
  2831. count = qla4_8xxx_rd_direct(ha,
  2832. QLA8XXX_PEG_ALIVE_COUNTER);
  2833. if (count != old_count) {
  2834. rval = QLA_SUCCESS;
  2835. goto dev_ready;
  2836. }
  2837. }
  2838. ha->isp_ops->rom_lock_recovery(ha);
  2839. }
  2840. /* set to DEV_INITIALIZING */
  2841. ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
  2842. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
  2843. QLA8XXX_DEV_INITIALIZING);
  2844. ha->isp_ops->idc_unlock(ha);
  2845. if (is_qla8022(ha))
  2846. qla4_8xxx_get_minidump(ha);
  2847. rval = ha->isp_ops->restart_firmware(ha);
  2848. ha->isp_ops->idc_lock(ha);
  2849. if (rval != QLA_SUCCESS) {
  2850. ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
  2851. qla4_8xxx_clear_drv_active(ha);
  2852. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
  2853. QLA8XXX_DEV_FAILED);
  2854. return rval;
  2855. }
  2856. dev_ready:
  2857. ql4_printk(KERN_INFO, ha, "HW State: READY\n");
  2858. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
  2859. return rval;
  2860. }
  2861. /**
  2862. * qla4_82xx_need_reset_handler - Code to start reset sequence
  2863. * @ha: pointer to adapter structure
  2864. *
  2865. * Note: IDC lock must be held upon entry
  2866. **/
  2867. static void
  2868. qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
  2869. {
  2870. uint32_t dev_state, drv_state, drv_active;
  2871. uint32_t active_mask = 0xFFFFFFFF;
  2872. unsigned long reset_timeout;
  2873. ql4_printk(KERN_INFO, ha,
  2874. "Performing ISP error recovery\n");
  2875. if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
  2876. qla4_82xx_idc_unlock(ha);
  2877. ha->isp_ops->disable_intrs(ha);
  2878. qla4_82xx_idc_lock(ha);
  2879. }
  2880. if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
  2881. DEBUG2(ql4_printk(KERN_INFO, ha,
  2882. "%s(%ld): reset acknowledged\n",
  2883. __func__, ha->host_no));
  2884. qla4_8xxx_set_rst_ready(ha);
  2885. } else {
  2886. active_mask = (~(1 << (ha->func_num * 4)));
  2887. }
  2888. /* wait for 10 seconds for reset ack from all functions */
  2889. reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
  2890. drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
  2891. drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  2892. ql4_printk(KERN_INFO, ha,
  2893. "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
  2894. __func__, ha->host_no, drv_state, drv_active);
  2895. while (drv_state != (drv_active & active_mask)) {
  2896. if (time_after_eq(jiffies, reset_timeout)) {
  2897. ql4_printk(KERN_INFO, ha,
  2898. "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
  2899. DRIVER_NAME, drv_state, drv_active);
  2900. break;
  2901. }
  2902. /*
  2903. * When reset_owner times out, check which functions
  2904. * acked/did not ack
  2905. */
  2906. if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
  2907. ql4_printk(KERN_INFO, ha,
  2908. "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
  2909. __func__, ha->host_no, drv_state,
  2910. drv_active);
  2911. }
  2912. qla4_82xx_idc_unlock(ha);
  2913. msleep(1000);
  2914. qla4_82xx_idc_lock(ha);
  2915. drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
  2916. drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  2917. }
  2918. /* Clear RESET OWNER as we are not going to use it any further */
  2919. clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
  2920. dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  2921. ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
  2922. dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
  2923. /* Force to DEV_COLD unless someone else is starting a reset */
  2924. if (dev_state != QLA8XXX_DEV_INITIALIZING) {
  2925. ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
  2926. qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
  2927. qla4_8xxx_set_rst_ready(ha);
  2928. }
  2929. }
  2930. /**
  2931. * qla4_8xxx_need_qsnt_handler - Code to start qsnt
  2932. * @ha: pointer to adapter structure
  2933. **/
  2934. void
  2935. qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
  2936. {
  2937. ha->isp_ops->idc_lock(ha);
  2938. qla4_8xxx_set_qsnt_ready(ha);
  2939. ha->isp_ops->idc_unlock(ha);
  2940. }
  2941. static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
  2942. {
  2943. int idc_ver;
  2944. uint32_t drv_active;
  2945. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  2946. if (drv_active == (1 << (ha->func_num * 4))) {
  2947. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
  2948. QLA82XX_IDC_VERSION);
  2949. ql4_printk(KERN_INFO, ha,
  2950. "%s: IDC version updated to %d\n", __func__,
  2951. QLA82XX_IDC_VERSION);
  2952. } else {
  2953. idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
  2954. if (QLA82XX_IDC_VERSION != idc_ver) {
  2955. ql4_printk(KERN_INFO, ha,
  2956. "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
  2957. __func__, QLA82XX_IDC_VERSION, idc_ver);
  2958. }
  2959. }
  2960. }
  2961. static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
  2962. {
  2963. int idc_ver;
  2964. uint32_t drv_active;
  2965. int rval = QLA_SUCCESS;
  2966. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  2967. if (drv_active == (1 << ha->func_num)) {
  2968. idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
  2969. idc_ver &= (~0xFF);
  2970. idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
  2971. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
  2972. ql4_printk(KERN_INFO, ha,
  2973. "%s: IDC version updated to %d\n", __func__,
  2974. idc_ver);
  2975. } else {
  2976. idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
  2977. idc_ver &= 0xFF;
  2978. if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
  2979. ql4_printk(KERN_INFO, ha,
  2980. "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
  2981. __func__, QLA83XX_IDC_VER_MAJ_VALUE,
  2982. idc_ver);
  2983. rval = QLA_ERROR;
  2984. goto exit_set_idc_ver;
  2985. }
  2986. }
  2987. /* Update IDC_MINOR_VERSION */
  2988. idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
  2989. idc_ver &= ~(0x03 << (ha->func_num * 2));
  2990. idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
  2991. qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
  2992. exit_set_idc_ver:
  2993. return rval;
  2994. }
  2995. int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
  2996. {
  2997. uint32_t drv_active;
  2998. int rval = QLA_SUCCESS;
  2999. if (test_bit(AF_INIT_DONE, &ha->flags))
  3000. goto exit_update_idc_reg;
  3001. ha->isp_ops->idc_lock(ha);
  3002. qla4_8xxx_set_drv_active(ha);
  3003. /*
  3004. * If we are the first driver to load and
  3005. * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
  3006. */
  3007. if (is_qla8032(ha) || is_qla8042(ha)) {
  3008. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  3009. if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
  3010. qla4_83xx_clear_idc_dontreset(ha);
  3011. }
  3012. if (is_qla8022(ha)) {
  3013. qla4_82xx_set_idc_ver(ha);
  3014. } else if (is_qla8032(ha) || is_qla8042(ha)) {
  3015. rval = qla4_83xx_set_idc_ver(ha);
  3016. if (rval == QLA_ERROR)
  3017. qla4_8xxx_clear_drv_active(ha);
  3018. }
  3019. ha->isp_ops->idc_unlock(ha);
  3020. exit_update_idc_reg:
  3021. return rval;
  3022. }
  3023. /**
  3024. * qla4_8xxx_device_state_handler - Adapter state machine
  3025. * @ha: pointer to host adapter structure.
  3026. *
  3027. * Note: IDC lock must be UNLOCKED upon entry
  3028. **/
  3029. int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
  3030. {
  3031. uint32_t dev_state;
  3032. int rval = QLA_SUCCESS;
  3033. unsigned long dev_init_timeout;
  3034. rval = qla4_8xxx_update_idc_reg(ha);
  3035. if (rval == QLA_ERROR)
  3036. goto exit_state_handler;
  3037. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  3038. DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
  3039. dev_state, dev_state < MAX_STATES ?
  3040. qdev_state[dev_state] : "Unknown"));
  3041. /* wait for 30 seconds for device to go ready */
  3042. dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
  3043. ha->isp_ops->idc_lock(ha);
  3044. while (1) {
  3045. if (time_after_eq(jiffies, dev_init_timeout)) {
  3046. ql4_printk(KERN_WARNING, ha,
  3047. "%s: Device Init Failed 0x%x = %s\n",
  3048. DRIVER_NAME,
  3049. dev_state, dev_state < MAX_STATES ?
  3050. qdev_state[dev_state] : "Unknown");
  3051. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
  3052. QLA8XXX_DEV_FAILED);
  3053. }
  3054. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  3055. ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
  3056. dev_state, dev_state < MAX_STATES ?
  3057. qdev_state[dev_state] : "Unknown");
  3058. /* NOTE: Make sure idc unlocked upon exit of switch statement */
  3059. switch (dev_state) {
  3060. case QLA8XXX_DEV_READY:
  3061. goto exit;
  3062. case QLA8XXX_DEV_COLD:
  3063. rval = qla4_8xxx_device_bootstrap(ha);
  3064. goto exit;
  3065. case QLA8XXX_DEV_INITIALIZING:
  3066. ha->isp_ops->idc_unlock(ha);
  3067. msleep(1000);
  3068. ha->isp_ops->idc_lock(ha);
  3069. break;
  3070. case QLA8XXX_DEV_NEED_RESET:
  3071. /*
  3072. * For ISP8324 and ISP8042, if NEED_RESET is set by any
  3073. * driver, it should be honored, irrespective of
  3074. * IDC_CTRL DONTRESET_BIT0
  3075. */
  3076. if (is_qla8032(ha) || is_qla8042(ha)) {
  3077. qla4_83xx_need_reset_handler(ha);
  3078. } else if (is_qla8022(ha)) {
  3079. if (!ql4xdontresethba) {
  3080. qla4_82xx_need_reset_handler(ha);
  3081. /* Update timeout value after need
  3082. * reset handler */
  3083. dev_init_timeout = jiffies +
  3084. (ha->nx_dev_init_timeout * HZ);
  3085. } else {
  3086. ha->isp_ops->idc_unlock(ha);
  3087. msleep(1000);
  3088. ha->isp_ops->idc_lock(ha);
  3089. }
  3090. }
  3091. break;
  3092. case QLA8XXX_DEV_NEED_QUIESCENT:
  3093. /* idc locked/unlocked in handler */
  3094. qla4_8xxx_need_qsnt_handler(ha);
  3095. break;
  3096. case QLA8XXX_DEV_QUIESCENT:
  3097. ha->isp_ops->idc_unlock(ha);
  3098. msleep(1000);
  3099. ha->isp_ops->idc_lock(ha);
  3100. break;
  3101. case QLA8XXX_DEV_FAILED:
  3102. ha->isp_ops->idc_unlock(ha);
  3103. qla4xxx_dead_adapter_cleanup(ha);
  3104. rval = QLA_ERROR;
  3105. ha->isp_ops->idc_lock(ha);
  3106. goto exit;
  3107. default:
  3108. ha->isp_ops->idc_unlock(ha);
  3109. qla4xxx_dead_adapter_cleanup(ha);
  3110. rval = QLA_ERROR;
  3111. ha->isp_ops->idc_lock(ha);
  3112. goto exit;
  3113. }
  3114. }
  3115. exit:
  3116. ha->isp_ops->idc_unlock(ha);
  3117. exit_state_handler:
  3118. return rval;
  3119. }
  3120. int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
  3121. {
  3122. int retval;
  3123. /* clear the interrupt */
  3124. if (is_qla8032(ha) || is_qla8042(ha)) {
  3125. writel(0, &ha->qla4_83xx_reg->risc_intr);
  3126. readl(&ha->qla4_83xx_reg->risc_intr);
  3127. } else if (is_qla8022(ha)) {
  3128. writel(0, &ha->qla4_82xx_reg->host_int);
  3129. readl(&ha->qla4_82xx_reg->host_int);
  3130. }
  3131. retval = qla4_8xxx_device_state_handler(ha);
  3132. /* Initialize request and response queues. */
  3133. if (retval == QLA_SUCCESS)
  3134. qla4xxx_init_rings(ha);
  3135. if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
  3136. retval = qla4xxx_request_irqs(ha);
  3137. return retval;
  3138. }
  3139. /*****************************************************************************/
  3140. /* Flash Manipulation Routines */
  3141. /*****************************************************************************/
  3142. #define OPTROM_BURST_SIZE 0x1000
  3143. #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
  3144. #define FARX_DATA_FLAG BIT_31
  3145. #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
  3146. #define FARX_ACCESS_FLASH_DATA 0x7FF00000
  3147. static inline uint32_t
  3148. flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
  3149. {
  3150. return hw->flash_conf_off | faddr;
  3151. }
  3152. static uint32_t *
  3153. qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
  3154. uint32_t faddr, uint32_t length)
  3155. {
  3156. uint32_t i;
  3157. uint32_t val;
  3158. int loops = 0;
  3159. while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
  3160. udelay(100);
  3161. cond_resched();
  3162. loops++;
  3163. }
  3164. if (loops >= 50000) {
  3165. ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
  3166. return dwptr;
  3167. }
  3168. /* Dword reads to flash. */
  3169. for (i = 0; i < length/4; i++, faddr += 4) {
  3170. if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
  3171. ql4_printk(KERN_WARNING, ha,
  3172. "Do ROM fast read failed\n");
  3173. goto done_read;
  3174. }
  3175. dwptr[i] = cpu_to_le32(val);
  3176. }
  3177. done_read:
  3178. qla4_82xx_rom_unlock(ha);
  3179. return dwptr;
  3180. }
  3181. /*
  3182. * Address and length are byte address
  3183. */
  3184. static uint8_t *
  3185. qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
  3186. uint32_t offset, uint32_t length)
  3187. {
  3188. qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
  3189. return buf;
  3190. }
  3191. static int
  3192. qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
  3193. {
  3194. const char *loc, *locations[] = { "DEF", "PCI" };
  3195. /*
  3196. * FLT-location structure resides after the last PCI region.
  3197. */
  3198. /* Begin with sane defaults. */
  3199. loc = locations[0];
  3200. *start = FA_FLASH_LAYOUT_ADDR_82;
  3201. DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
  3202. return QLA_SUCCESS;
  3203. }
  3204. static void
  3205. qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
  3206. {
  3207. const char *loc, *locations[] = { "DEF", "FLT" };
  3208. uint16_t *wptr;
  3209. uint16_t cnt, chksum;
  3210. uint32_t start, status;
  3211. struct qla_flt_header *flt;
  3212. struct qla_flt_region *region;
  3213. struct ql82xx_hw_data *hw = &ha->hw;
  3214. hw->flt_region_flt = flt_addr;
  3215. wptr = (uint16_t *)ha->request_ring;
  3216. flt = (struct qla_flt_header *)ha->request_ring;
  3217. region = (struct qla_flt_region *)&flt[1];
  3218. if (is_qla8022(ha)) {
  3219. qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
  3220. flt_addr << 2, OPTROM_BURST_SIZE);
  3221. } else if (is_qla8032(ha) || is_qla8042(ha)) {
  3222. status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
  3223. (uint8_t *)ha->request_ring,
  3224. 0x400);
  3225. if (status != QLA_SUCCESS)
  3226. goto no_flash_data;
  3227. }
  3228. if (*wptr == cpu_to_le16(0xffff))
  3229. goto no_flash_data;
  3230. if (flt->version != cpu_to_le16(1)) {
  3231. DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
  3232. "version=0x%x length=0x%x checksum=0x%x.\n",
  3233. le16_to_cpu(flt->version), le16_to_cpu(flt->length),
  3234. le16_to_cpu(flt->checksum)));
  3235. goto no_flash_data;
  3236. }
  3237. cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
  3238. for (chksum = 0; cnt; cnt--)
  3239. chksum += le16_to_cpu(*wptr++);
  3240. if (chksum) {
  3241. DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
  3242. "version=0x%x length=0x%x checksum=0x%x.\n",
  3243. le16_to_cpu(flt->version), le16_to_cpu(flt->length),
  3244. chksum));
  3245. goto no_flash_data;
  3246. }
  3247. loc = locations[1];
  3248. cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
  3249. for ( ; cnt; cnt--, region++) {
  3250. /* Store addresses as DWORD offsets. */
  3251. start = le32_to_cpu(region->start) >> 2;
  3252. DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
  3253. "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
  3254. le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
  3255. switch (le32_to_cpu(region->code) & 0xff) {
  3256. case FLT_REG_FDT:
  3257. hw->flt_region_fdt = start;
  3258. break;
  3259. case FLT_REG_BOOT_CODE_82:
  3260. hw->flt_region_boot = start;
  3261. break;
  3262. case FLT_REG_FW_82:
  3263. case FLT_REG_FW_82_1:
  3264. hw->flt_region_fw = start;
  3265. break;
  3266. case FLT_REG_BOOTLOAD_82:
  3267. hw->flt_region_bootload = start;
  3268. break;
  3269. case FLT_REG_ISCSI_PARAM:
  3270. hw->flt_iscsi_param = start;
  3271. break;
  3272. case FLT_REG_ISCSI_CHAP:
  3273. hw->flt_region_chap = start;
  3274. hw->flt_chap_size = le32_to_cpu(region->size);
  3275. break;
  3276. case FLT_REG_ISCSI_DDB:
  3277. hw->flt_region_ddb = start;
  3278. hw->flt_ddb_size = le32_to_cpu(region->size);
  3279. break;
  3280. }
  3281. }
  3282. goto done;
  3283. no_flash_data:
  3284. /* Use hardcoded defaults. */
  3285. loc = locations[0];
  3286. hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82;
  3287. hw->flt_region_boot = FA_BOOT_CODE_ADDR_82;
  3288. hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
  3289. hw->flt_region_fw = FA_RISC_CODE_ADDR_82;
  3290. hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2;
  3291. hw->flt_chap_size = FA_FLASH_CHAP_SIZE;
  3292. hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2;
  3293. hw->flt_ddb_size = FA_FLASH_DDB_SIZE;
  3294. done:
  3295. DEBUG2(ql4_printk(KERN_INFO, ha,
  3296. "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n",
  3297. loc, hw->flt_region_flt, hw->flt_region_fdt,
  3298. hw->flt_region_boot, hw->flt_region_bootload,
  3299. hw->flt_region_fw, hw->flt_region_chap,
  3300. hw->flt_chap_size, hw->flt_region_ddb,
  3301. hw->flt_ddb_size));
  3302. }
  3303. static void
  3304. qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
  3305. {
  3306. #define FLASH_BLK_SIZE_4K 0x1000
  3307. #define FLASH_BLK_SIZE_32K 0x8000
  3308. #define FLASH_BLK_SIZE_64K 0x10000
  3309. const char *loc, *locations[] = { "MID", "FDT" };
  3310. uint16_t cnt, chksum;
  3311. uint16_t *wptr;
  3312. struct qla_fdt_layout *fdt;
  3313. uint16_t mid = 0;
  3314. uint16_t fid = 0;
  3315. struct ql82xx_hw_data *hw = &ha->hw;
  3316. hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  3317. hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
  3318. wptr = (uint16_t *)ha->request_ring;
  3319. fdt = (struct qla_fdt_layout *)ha->request_ring;
  3320. qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
  3321. hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
  3322. if (*wptr == cpu_to_le16(0xffff))
  3323. goto no_flash_data;
  3324. if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
  3325. fdt->sig[3] != 'D')
  3326. goto no_flash_data;
  3327. for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
  3328. cnt++)
  3329. chksum += le16_to_cpu(*wptr++);
  3330. if (chksum) {
  3331. DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
  3332. "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
  3333. le16_to_cpu(fdt->version)));
  3334. goto no_flash_data;
  3335. }
  3336. loc = locations[1];
  3337. mid = le16_to_cpu(fdt->man_id);
  3338. fid = le16_to_cpu(fdt->id);
  3339. hw->fdt_wrt_disable = fdt->wrt_disable_bits;
  3340. hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
  3341. hw->fdt_block_size = le32_to_cpu(fdt->block_size);
  3342. if (fdt->unprotect_sec_cmd) {
  3343. hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
  3344. fdt->unprotect_sec_cmd);
  3345. hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
  3346. flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
  3347. flash_conf_addr(hw, 0x0336);
  3348. }
  3349. goto done;
  3350. no_flash_data:
  3351. loc = locations[0];
  3352. hw->fdt_block_size = FLASH_BLK_SIZE_64K;
  3353. done:
  3354. DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
  3355. "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
  3356. hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
  3357. hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
  3358. hw->fdt_block_size));
  3359. }
  3360. static void
  3361. qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
  3362. {
  3363. #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
  3364. uint32_t *wptr;
  3365. if (!is_qla8022(ha))
  3366. return;
  3367. wptr = (uint32_t *)ha->request_ring;
  3368. qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
  3369. QLA82XX_IDC_PARAM_ADDR , 8);
  3370. if (*wptr == cpu_to_le32(0xffffffff)) {
  3371. ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
  3372. ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
  3373. } else {
  3374. ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
  3375. ha->nx_reset_timeout = le32_to_cpu(*wptr);
  3376. }
  3377. DEBUG2(ql4_printk(KERN_DEBUG, ha,
  3378. "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
  3379. DEBUG2(ql4_printk(KERN_DEBUG, ha,
  3380. "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
  3381. return;
  3382. }
  3383. void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
  3384. int in_count)
  3385. {
  3386. int i;
  3387. /* Load all mailbox registers, except mailbox 0. */
  3388. for (i = 1; i < in_count; i++)
  3389. writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
  3390. /* Wakeup firmware */
  3391. writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
  3392. readl(&ha->qla4_82xx_reg->mailbox_in[0]);
  3393. writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
  3394. readl(&ha->qla4_82xx_reg->hint);
  3395. }
  3396. void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
  3397. {
  3398. int intr_status;
  3399. intr_status = readl(&ha->qla4_82xx_reg->host_int);
  3400. if (intr_status & ISRX_82XX_RISC_INT) {
  3401. ha->mbox_status_count = out_count;
  3402. intr_status = readl(&ha->qla4_82xx_reg->host_status);
  3403. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  3404. if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  3405. (!ha->pdev->msi_enabled && !ha->pdev->msix_enabled))
  3406. qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
  3407. 0xfbff);
  3408. }
  3409. }
  3410. int
  3411. qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
  3412. {
  3413. int ret;
  3414. uint32_t flt_addr;
  3415. ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
  3416. if (ret != QLA_SUCCESS)
  3417. return ret;
  3418. qla4_8xxx_get_flt_info(ha, flt_addr);
  3419. if (is_qla8022(ha)) {
  3420. qla4_82xx_get_fdt_info(ha);
  3421. qla4_82xx_get_idc_param(ha);
  3422. } else if (is_qla8032(ha) || is_qla8042(ha)) {
  3423. qla4_83xx_get_idc_param(ha);
  3424. }
  3425. return QLA_SUCCESS;
  3426. }
  3427. /**
  3428. * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
  3429. * @ha: pointer to host adapter structure.
  3430. *
  3431. * Remarks:
  3432. * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
  3433. * not be available after successful return. Driver must cleanup potential
  3434. * outstanding I/O's after calling this funcion.
  3435. **/
  3436. int
  3437. qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
  3438. {
  3439. int status;
  3440. uint32_t mbox_cmd[MBOX_REG_COUNT];
  3441. uint32_t mbox_sts[MBOX_REG_COUNT];
  3442. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  3443. memset(&mbox_sts, 0, sizeof(mbox_sts));
  3444. mbox_cmd[0] = MBOX_CMD_STOP_FW;
  3445. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
  3446. &mbox_cmd[0], &mbox_sts[0]);
  3447. DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
  3448. __func__, status));
  3449. return status;
  3450. }
  3451. /**
  3452. * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
  3453. * @ha: pointer to host adapter structure.
  3454. **/
  3455. int
  3456. qla4_82xx_isp_reset(struct scsi_qla_host *ha)
  3457. {
  3458. int rval;
  3459. uint32_t dev_state;
  3460. qla4_82xx_idc_lock(ha);
  3461. dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  3462. if (dev_state == QLA8XXX_DEV_READY) {
  3463. ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
  3464. qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3465. QLA8XXX_DEV_NEED_RESET);
  3466. set_bit(AF_8XXX_RST_OWNER, &ha->flags);
  3467. } else
  3468. ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
  3469. qla4_82xx_idc_unlock(ha);
  3470. rval = qla4_8xxx_device_state_handler(ha);
  3471. qla4_82xx_idc_lock(ha);
  3472. qla4_8xxx_clear_rst_ready(ha);
  3473. qla4_82xx_idc_unlock(ha);
  3474. if (rval == QLA_SUCCESS) {
  3475. ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
  3476. clear_bit(AF_FW_RECOVERY, &ha->flags);
  3477. }
  3478. return rval;
  3479. }
  3480. /**
  3481. * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
  3482. * @ha: pointer to host adapter structure.
  3483. *
  3484. **/
  3485. int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
  3486. {
  3487. uint32_t mbox_cmd[MBOX_REG_COUNT];
  3488. uint32_t mbox_sts[MBOX_REG_COUNT];
  3489. struct mbx_sys_info *sys_info;
  3490. dma_addr_t sys_info_dma;
  3491. int status = QLA_ERROR;
  3492. sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
  3493. &sys_info_dma, GFP_KERNEL);
  3494. if (sys_info == NULL) {
  3495. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  3496. ha->host_no, __func__));
  3497. return status;
  3498. }
  3499. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  3500. memset(&mbox_sts, 0, sizeof(mbox_sts));
  3501. mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
  3502. mbox_cmd[1] = LSDW(sys_info_dma);
  3503. mbox_cmd[2] = MSDW(sys_info_dma);
  3504. mbox_cmd[4] = sizeof(*sys_info);
  3505. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
  3506. &mbox_sts[0]) != QLA_SUCCESS) {
  3507. DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
  3508. ha->host_no, __func__));
  3509. goto exit_validate_mac82;
  3510. }
  3511. /* Make sure we receive the minimum required data to cache internally */
  3512. if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) <
  3513. offsetof(struct mbx_sys_info, reserved)) {
  3514. DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
  3515. " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
  3516. goto exit_validate_mac82;
  3517. }
  3518. /* Save M.A.C. address & serial_number */
  3519. ha->port_num = sys_info->port_num;
  3520. memcpy(ha->my_mac, &sys_info->mac_addr[0],
  3521. min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
  3522. memcpy(ha->serial_number, &sys_info->serial_number,
  3523. min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
  3524. memcpy(ha->model_name, &sys_info->board_id_str,
  3525. min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
  3526. ha->phy_port_cnt = sys_info->phys_port_cnt;
  3527. ha->phy_port_num = sys_info->port_num;
  3528. ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
  3529. DEBUG2(printk("scsi%ld: %s: mac %pM serial %s\n",
  3530. ha->host_no, __func__, ha->my_mac, ha->serial_number));
  3531. status = QLA_SUCCESS;
  3532. exit_validate_mac82:
  3533. dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
  3534. sys_info_dma);
  3535. return status;
  3536. }
  3537. /* Interrupt handling helpers. */
  3538. int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
  3539. {
  3540. uint32_t mbox_cmd[MBOX_REG_COUNT];
  3541. uint32_t mbox_sts[MBOX_REG_COUNT];
  3542. DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
  3543. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  3544. memset(&mbox_sts, 0, sizeof(mbox_sts));
  3545. mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
  3546. mbox_cmd[1] = INTR_ENABLE;
  3547. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  3548. &mbox_sts[0]) != QLA_SUCCESS) {
  3549. DEBUG2(ql4_printk(KERN_INFO, ha,
  3550. "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
  3551. __func__, mbox_sts[0]));
  3552. return QLA_ERROR;
  3553. }
  3554. return QLA_SUCCESS;
  3555. }
  3556. int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
  3557. {
  3558. uint32_t mbox_cmd[MBOX_REG_COUNT];
  3559. uint32_t mbox_sts[MBOX_REG_COUNT];
  3560. DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
  3561. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  3562. memset(&mbox_sts, 0, sizeof(mbox_sts));
  3563. mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
  3564. mbox_cmd[1] = INTR_DISABLE;
  3565. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  3566. &mbox_sts[0]) != QLA_SUCCESS) {
  3567. DEBUG2(ql4_printk(KERN_INFO, ha,
  3568. "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
  3569. __func__, mbox_sts[0]));
  3570. return QLA_ERROR;
  3571. }
  3572. return QLA_SUCCESS;
  3573. }
  3574. void
  3575. qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
  3576. {
  3577. qla4_8xxx_intr_enable(ha);
  3578. spin_lock_irq(&ha->hardware_lock);
  3579. /* BIT 10 - reset */
  3580. qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
  3581. spin_unlock_irq(&ha->hardware_lock);
  3582. set_bit(AF_INTERRUPTS_ON, &ha->flags);
  3583. }
  3584. void
  3585. qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
  3586. {
  3587. if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
  3588. qla4_8xxx_intr_disable(ha);
  3589. spin_lock_irq(&ha->hardware_lock);
  3590. /* BIT 10 - set */
  3591. qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
  3592. spin_unlock_irq(&ha->hardware_lock);
  3593. }
  3594. int
  3595. qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
  3596. {
  3597. int ret;
  3598. ret = pci_alloc_irq_vectors(ha->pdev, QLA_MSIX_ENTRIES,
  3599. QLA_MSIX_ENTRIES, PCI_IRQ_MSIX);
  3600. if (ret < 0) {
  3601. ql4_printk(KERN_WARNING, ha,
  3602. "MSI-X: Failed to enable support -- %d/%d\n",
  3603. QLA_MSIX_ENTRIES, ret);
  3604. return ret;
  3605. }
  3606. ret = request_irq(pci_irq_vector(ha->pdev, 0),
  3607. qla4_8xxx_default_intr_handler, 0, "qla4xxx (default)",
  3608. ha);
  3609. if (ret)
  3610. goto out_free_vectors;
  3611. ret = request_irq(pci_irq_vector(ha->pdev, 1),
  3612. qla4_8xxx_msix_rsp_q, 0, "qla4xxx (rsp_q)", ha);
  3613. if (ret)
  3614. goto out_free_default_irq;
  3615. return 0;
  3616. out_free_default_irq:
  3617. free_irq(pci_irq_vector(ha->pdev, 0), ha);
  3618. out_free_vectors:
  3619. pci_free_irq_vectors(ha->pdev);
  3620. return ret;
  3621. }
  3622. int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha)
  3623. {
  3624. int status = QLA_SUCCESS;
  3625. /* Dont retry adapter initialization if IRQ allocation failed */
  3626. if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) {
  3627. ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n",
  3628. __func__);
  3629. status = QLA_ERROR;
  3630. goto exit_init_adapter_failure;
  3631. }
  3632. /* Since interrupts are registered in start_firmware for
  3633. * 8xxx, release them here if initialize_adapter fails
  3634. * and retry adapter initialization */
  3635. qla4xxx_free_irqs(ha);
  3636. exit_init_adapter_failure:
  3637. return status;
  3638. }