qla_mr.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * QLogic Fibre Channel HBA Driver
  4. * Copyright (c) 2003-2014 QLogic Corporation
  5. */
  6. #ifndef __QLA_MR_H
  7. #define __QLA_MR_H
  8. #include "qla_dsd.h"
  9. /*
  10. * The PCI VendorID and DeviceID for our board.
  11. */
  12. #define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001
  13. /* FX00 specific definitions */
  14. #define FX00_COMMAND_TYPE_7 0x07 /* Command Type 7 entry for 7XXX */
  15. struct cmd_type_7_fx00 {
  16. uint8_t entry_type; /* Entry type. */
  17. uint8_t entry_count; /* Entry count. */
  18. uint8_t sys_define; /* System defined. */
  19. uint8_t entry_status; /* Entry Status. */
  20. uint32_t handle; /* System handle. */
  21. uint8_t reserved_0;
  22. uint8_t port_path_ctrl;
  23. uint16_t reserved_1;
  24. __le16 tgt_idx; /* Target Idx. */
  25. uint16_t timeout; /* Command timeout. */
  26. __le16 dseg_count; /* Data segment count. */
  27. uint8_t scsi_rsp_dsd_len;
  28. uint8_t reserved_2;
  29. struct scsi_lun lun; /* LUN (LE). */
  30. uint8_t cntrl_flags;
  31. uint8_t task_mgmt_flags; /* Task management flags. */
  32. uint8_t task;
  33. uint8_t crn;
  34. uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
  35. __le32 byte_count; /* Total byte count. */
  36. struct dsd64 dsd;
  37. };
  38. #define STATUS_TYPE_FX00 0x01 /* Status entry. */
  39. struct sts_entry_fx00 {
  40. uint8_t entry_type; /* Entry type. */
  41. uint8_t entry_count; /* Entry count. */
  42. uint8_t sys_define; /* System defined. */
  43. uint8_t entry_status; /* Entry Status. */
  44. uint32_t handle; /* System handle. */
  45. uint32_t reserved_3; /* System handle. */
  46. __le16 comp_status; /* Completion status. */
  47. uint16_t reserved_0; /* OX_ID used by the firmware. */
  48. __le32 residual_len; /* FW calc residual transfer length. */
  49. uint16_t reserved_1;
  50. uint16_t state_flags; /* State flags. */
  51. uint16_t reserved_2;
  52. __le16 scsi_status; /* SCSI status. */
  53. uint32_t sense_len; /* FCP SENSE length. */
  54. uint8_t data[32]; /* FCP response/sense information. */
  55. };
  56. #define MAX_HANDLE_COUNT 15
  57. #define MULTI_STATUS_TYPE_FX00 0x0D
  58. struct multi_sts_entry_fx00 {
  59. uint8_t entry_type; /* Entry type. */
  60. uint8_t entry_count; /* Entry count. */
  61. uint8_t handle_count;
  62. uint8_t entry_status;
  63. __le32 handles[MAX_HANDLE_COUNT];
  64. };
  65. #define TSK_MGMT_IOCB_TYPE_FX00 0x05
  66. struct tsk_mgmt_entry_fx00 {
  67. uint8_t entry_type; /* Entry type. */
  68. uint8_t entry_count; /* Entry count. */
  69. uint8_t sys_define;
  70. uint8_t entry_status; /* Entry Status. */
  71. uint32_t handle; /* System handle. */
  72. uint32_t reserved_0;
  73. __le16 tgt_id; /* Target Idx. */
  74. uint16_t reserved_1;
  75. uint16_t reserved_3;
  76. uint16_t reserved_4;
  77. struct scsi_lun lun; /* LUN (LE). */
  78. __le32 control_flags; /* Control Flags. */
  79. uint8_t reserved_2[32];
  80. };
  81. #define ABORT_IOCB_TYPE_FX00 0x08 /* Abort IOCB status. */
  82. struct abort_iocb_entry_fx00 {
  83. uint8_t entry_type; /* Entry type. */
  84. uint8_t entry_count; /* Entry count. */
  85. uint8_t sys_define; /* System defined. */
  86. uint8_t entry_status; /* Entry Status. */
  87. uint32_t handle; /* System handle. */
  88. __le32 reserved_0;
  89. __le16 tgt_id_sts; /* Completion status. */
  90. __le16 options;
  91. uint32_t abort_handle; /* System handle. */
  92. __le32 reserved_2;
  93. __le16 req_que_no;
  94. uint8_t reserved_1[38];
  95. };
  96. #define IOCTL_IOSB_TYPE_FX00 0x0C
  97. struct ioctl_iocb_entry_fx00 {
  98. uint8_t entry_type; /* Entry type. */
  99. uint8_t entry_count; /* Entry count. */
  100. uint8_t sys_define; /* System defined. */
  101. uint8_t entry_status; /* Entry Status. */
  102. uint32_t handle; /* System handle. */
  103. uint32_t reserved_0; /* System handle. */
  104. uint16_t comp_func_num;
  105. __le16 fw_iotcl_flags;
  106. __le32 dataword_r; /* Data word returned */
  107. uint32_t adapid; /* Adapter ID */
  108. uint32_t dataword_r_extra;
  109. __le32 seq_no;
  110. uint8_t reserved_2[20];
  111. uint32_t residuallen;
  112. __le32 status;
  113. };
  114. #define STATUS_CONT_TYPE_FX00 0x04
  115. #define FX00_IOCB_TYPE 0x0B
  116. struct fxdisc_entry_fx00 {
  117. uint8_t entry_type; /* Entry type. */
  118. uint8_t entry_count; /* Entry count. */
  119. uint8_t sys_define; /* System Defined. */
  120. uint8_t entry_status; /* Entry Status. */
  121. uint32_t handle; /* System handle. */
  122. __le32 reserved_0; /* System handle. */
  123. __le16 func_num;
  124. __le16 req_xfrcnt;
  125. __le16 req_dsdcnt;
  126. __le16 rsp_xfrcnt;
  127. __le16 rsp_dsdcnt;
  128. uint8_t flags;
  129. uint8_t reserved_1;
  130. /*
  131. * Use array size 1 below to prevent that Coverity complains about
  132. * the append_dsd64() calls for the two arrays below.
  133. */
  134. struct dsd64 dseg_rq[1];
  135. struct dsd64 dseg_rsp[1];
  136. __le32 dataword;
  137. __le32 adapid;
  138. __le32 adapid_hi;
  139. __le32 dataword_extra;
  140. };
  141. struct qlafx00_tgt_node_info {
  142. uint8_t tgt_node_wwpn[WWN_SIZE];
  143. uint8_t tgt_node_wwnn[WWN_SIZE];
  144. uint32_t tgt_node_state;
  145. uint8_t reserved[128];
  146. uint32_t reserved_1[8];
  147. uint64_t reserved_2[4];
  148. } __packed;
  149. #define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info)
  150. #define QLAFX00_LINK_STATUS_DOWN 0x10
  151. #define QLAFX00_LINK_STATUS_UP 0x11
  152. #define QLAFX00_PORT_SPEED_2G 0x2
  153. #define QLAFX00_PORT_SPEED_4G 0x4
  154. #define QLAFX00_PORT_SPEED_8G 0x8
  155. #define QLAFX00_PORT_SPEED_10G 0xa
  156. struct port_info_data {
  157. uint8_t port_state;
  158. uint8_t port_type;
  159. uint16_t port_identifier;
  160. uint32_t up_port_state;
  161. uint8_t fw_ver_num[32];
  162. uint8_t portal_attrib;
  163. uint16_t host_option;
  164. uint8_t reset_delay;
  165. uint8_t pdwn_retry_cnt;
  166. uint16_t max_luns2tgt;
  167. uint8_t risc_ver;
  168. uint8_t pconn_option;
  169. uint16_t risc_option;
  170. uint16_t max_frame_len;
  171. uint16_t max_iocb_alloc;
  172. uint16_t exec_throttle;
  173. uint8_t retry_cnt;
  174. uint8_t retry_delay;
  175. uint8_t port_name[8];
  176. uint8_t port_id[3];
  177. uint8_t link_status;
  178. uint8_t plink_rate;
  179. uint32_t link_config;
  180. uint16_t adap_haddr;
  181. uint8_t tgt_disc;
  182. uint8_t log_tout;
  183. uint8_t node_name[8];
  184. uint16_t erisc_opt1;
  185. uint8_t resp_acc_tmr;
  186. uint8_t intr_del_tmr;
  187. uint8_t erisc_opt2;
  188. uint8_t alt_port_name[8];
  189. uint8_t alt_node_name[8];
  190. uint8_t link_down_tout;
  191. uint8_t conn_type;
  192. uint8_t fc_fw_mode;
  193. uint32_t uiReserved[48];
  194. } __packed;
  195. /* OS Type Designations */
  196. #define OS_TYPE_UNKNOWN 0
  197. #define OS_TYPE_LINUX 2
  198. /* Linux Info */
  199. #define SYSNAME_LENGTH 128
  200. #define NODENAME_LENGTH 64
  201. #define RELEASE_LENGTH 64
  202. #define VERSION_LENGTH 64
  203. #define MACHINE_LENGTH 64
  204. #define DOMNAME_LENGTH 64
  205. struct host_system_info {
  206. uint32_t os_type;
  207. char sysname[SYSNAME_LENGTH];
  208. char nodename[NODENAME_LENGTH];
  209. char release[RELEASE_LENGTH];
  210. char version[VERSION_LENGTH];
  211. char machine[MACHINE_LENGTH];
  212. char domainname[DOMNAME_LENGTH];
  213. char hostdriver[VERSION_LENGTH];
  214. uint32_t reserved[64];
  215. } __packed;
  216. struct register_host_info {
  217. struct host_system_info hsi; /* host system info */
  218. uint64_t utc; /* UTC (system time) */
  219. uint32_t reserved[64]; /* future additions */
  220. } __packed;
  221. #define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data))
  222. #define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32)
  223. struct config_info_data {
  224. uint8_t model_num[16];
  225. uint8_t model_description[80];
  226. uint8_t reserved0[160];
  227. uint8_t symbolic_name[64];
  228. uint8_t serial_num[32];
  229. uint8_t hw_version[16];
  230. uint8_t fw_version[16];
  231. uint8_t uboot_version[16];
  232. uint8_t fru_serial_num[32];
  233. uint8_t fc_port_count;
  234. uint8_t iscsi_port_count;
  235. uint8_t reserved1[2];
  236. uint8_t mode;
  237. uint8_t log_level;
  238. uint8_t reserved2[2];
  239. uint32_t log_size;
  240. uint8_t tgt_pres_mode;
  241. uint8_t iqn_flags;
  242. uint8_t lun_mapping;
  243. uint64_t adapter_id;
  244. uint32_t cluster_key_len;
  245. uint8_t cluster_key[16];
  246. uint64_t cluster_master_id;
  247. uint64_t cluster_slave_id;
  248. uint8_t cluster_flags;
  249. uint32_t enabled_capabilities;
  250. uint32_t nominal_temp_value;
  251. } __packed;
  252. #define FXDISC_GET_CONFIG_INFO 0x01
  253. #define FXDISC_GET_PORT_INFO 0x02
  254. #define FXDISC_GET_TGT_NODE_INFO 0x80
  255. #define FXDISC_GET_TGT_NODE_LIST 0x81
  256. #define FXDISC_REG_HOST_INFO 0x99
  257. #define FXDISC_ABORT_IOCTL 0xff
  258. #define QLAFX00_HBA_ICNTRL_REG 0x20B08
  259. #define QLAFX00_ICR_ENB_MASK 0x80000000
  260. #define QLAFX00_ICR_DIS_MASK 0x7fffffff
  261. #define QLAFX00_HST_RST_REG 0x18264
  262. #define QLAFX00_SOC_TEMP_REG 0x184C4
  263. #define QLAFX00_HST_TO_HBA_REG 0x20A04
  264. #define QLAFX00_HBA_TO_HOST_REG 0x21B70
  265. #define QLAFX00_HST_INT_STS_BITS 0x7
  266. #define QLAFX00_BAR1_BASE_ADDR_REG 0x40018
  267. #define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824
  268. #define QLAFX00_INTR_MB_CMPLT 0x1
  269. #define QLAFX00_INTR_RSP_CMPLT 0x2
  270. #define QLAFX00_INTR_ASYNC_CMPLT 0x4
  271. #define QLAFX00_MBA_SYSTEM_ERR 0x8002
  272. #define QLAFX00_MBA_TEMP_OVER 0x8005
  273. #define QLAFX00_MBA_TEMP_NORM 0x8006
  274. #define QLAFX00_MBA_TEMP_CRIT 0x8007
  275. #define QLAFX00_MBA_LINK_UP 0x8011
  276. #define QLAFX00_MBA_LINK_DOWN 0x8012
  277. #define QLAFX00_MBA_PORT_UPDATE 0x8014
  278. #define QLAFX00_MBA_SHUTDOWN_RQSTD 0x8062
  279. #define SOC_SW_RST_CONTROL_REG_CORE0 0x0020800
  280. #define SOC_FABRIC_RST_CONTROL_REG 0x0020840
  281. #define SOC_FABRIC_CONTROL_REG 0x0020200
  282. #define SOC_FABRIC_CONFIG_REG 0x0020204
  283. #define SOC_PWR_MANAGEMENT_PWR_DOWN_REG 0x001820C
  284. #define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00
  285. #define SOC_CORE_TIMER_REG 0x0021850
  286. #define SOC_IRQ_ACK_REG 0x00218b4
  287. #define CONTINUE_A64_TYPE_FX00 0x03 /* Continuation entry. */
  288. #define QLAFX00_SET_HST_INTR(ha, value) \
  289. wrt_reg_dword((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \
  290. value)
  291. #define QLAFX00_CLR_HST_INTR(ha, value) \
  292. wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
  293. ~value)
  294. #define QLAFX00_RD_INTR_REG(ha) \
  295. rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
  296. #define QLAFX00_CLR_INTR_REG(ha, value) \
  297. wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
  298. ~value)
  299. #define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\
  300. wrt_reg_dword((ha)->cregbase + off, val)
  301. #define QLAFX00_GET_HBA_SOC_REG(ha, off)\
  302. rd_reg_dword((ha)->cregbase + off)
  303. #define QLAFX00_HBA_RST_REG(ha, val)\
  304. wrt_reg_dword((ha)->cregbase + QLAFX00_HST_RST_REG, val)
  305. #define QLAFX00_RD_ICNTRL_REG(ha) \
  306. rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
  307. #define QLAFX00_ENABLE_ICNTRL_REG(ha) \
  308. wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
  309. (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \
  310. QLAFX00_ICR_ENB_MASK))
  311. #define QLAFX00_DISABLE_ICNTRL_REG(ha) \
  312. wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
  313. (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \
  314. QLAFX00_ICR_DIS_MASK))
  315. #define QLAFX00_RD_REG(ha, off) \
  316. rd_reg_dword((ha)->cregbase + off)
  317. #define QLAFX00_WR_REG(ha, off, val) \
  318. wrt_reg_dword((ha)->cregbase + off, val)
  319. struct qla_mt_iocb_rqst_fx00 {
  320. __le32 reserved_0;
  321. __le16 func_type;
  322. uint8_t flags;
  323. uint8_t reserved_1;
  324. __le32 dataword;
  325. __le32 adapid;
  326. __le32 adapid_hi;
  327. __le32 dataword_extra;
  328. __le16 req_len;
  329. __le16 reserved_2;
  330. __le16 rsp_len;
  331. __le16 reserved_3;
  332. };
  333. struct qla_mt_iocb_rsp_fx00 {
  334. uint32_t reserved_1;
  335. uint16_t func_type;
  336. __le16 ioctl_flags;
  337. __le32 ioctl_data;
  338. uint32_t adapid;
  339. uint32_t adapid_hi;
  340. uint32_t reserved_2;
  341. __le32 seq_number;
  342. uint8_t reserved_3[20];
  343. int32_t res_count;
  344. __le32 status;
  345. };
  346. #define MAILBOX_REGISTER_COUNT_FX00 16
  347. #define AEN_MAILBOX_REGISTER_COUNT_FX00 8
  348. #define MAX_FIBRE_DEVICES_FX00 512
  349. #define MAX_LUNS_FX00 0x1024
  350. #define MAX_TARGETS_FX00 MAX_ISA_DEVICES
  351. #define REQUEST_ENTRY_CNT_FX00 512 /* Number of request entries. */
  352. #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
  353. /*
  354. * Firmware state codes for QLAFX00 adapters
  355. */
  356. #define FSTATE_FX00_CONFIG_WAIT 0x0000 /* Waiting for driver to issue
  357. * Initialize FW Mbox cmd
  358. */
  359. #define FSTATE_FX00_INITIALIZED 0x1000 /* FW has been initialized by
  360. * the driver
  361. */
  362. #define FX00_DEF_RATOV 10
  363. struct mr_data_fx00 {
  364. uint8_t symbolic_name[64];
  365. uint8_t serial_num[32];
  366. uint8_t hw_version[16];
  367. uint8_t fw_version[16];
  368. uint8_t uboot_version[16];
  369. uint8_t fru_serial_num[32];
  370. fc_port_t fcport; /* fcport used for requests
  371. * that are not linked
  372. * to a particular target
  373. */
  374. uint8_t fw_hbt_en;
  375. uint8_t fw_hbt_cnt;
  376. uint8_t fw_hbt_miss_cnt;
  377. uint32_t old_fw_hbt_cnt;
  378. uint16_t fw_reset_timer_tick;
  379. uint8_t fw_reset_timer_exp;
  380. uint16_t fw_critemp_timer_tick;
  381. uint32_t old_aenmbx0_state;
  382. uint32_t critical_temperature;
  383. bool extended_io_enabled;
  384. bool host_info_resend;
  385. uint8_t hinfo_resend_timer_tick;
  386. };
  387. #define QLAFX00_EXTENDED_IO_EN_MASK 0x20
  388. /*
  389. * SoC Junction Temperature is stored in
  390. * bits 9:1 of SoC Junction Temperature Register
  391. * in a firmware specific format format.
  392. * To get the temperature in Celsius degrees
  393. * the value from this bitfiled should be converted
  394. * using this formula:
  395. * Temperature (degrees C) = ((3,153,000 - (10,000 * X)) / 13,825)
  396. * where X is the bit field value
  397. * this macro reads the register, extracts the bitfield value,
  398. * performs the calcualtions and returns temperature in Celsius
  399. */
  400. #define QLAFX00_GET_TEMPERATURE(ha) ((3153000 - (10000 * \
  401. ((QLAFX00_RD_REG(ha, QLAFX00_SOC_TEMP_REG) & 0x3FE) >> 1))) / 13825)
  402. #define QLAFX00_LOOP_DOWN_TIME 615 /* 600 */
  403. #define QLAFX00_HEARTBEAT_INTERVAL 6 /* number of seconds */
  404. #define QLAFX00_HEARTBEAT_MISS_CNT 3 /* number of miss */
  405. #define QLAFX00_RESET_INTERVAL 120 /* number of seconds */
  406. #define QLAFX00_MAX_RESET_INTERVAL 600 /* number of seconds */
  407. #define QLAFX00_CRITEMP_INTERVAL 60 /* number of seconds */
  408. #define QLAFX00_HINFO_RESEND_INTERVAL 60 /* number of seconds */
  409. #define QLAFX00_CRITEMP_THRSHLD 80 /* Celsius degrees */
  410. /* Max conncurrent IOs that can be queued */
  411. #define QLAFX00_MAX_CANQUEUE 1024
  412. /* IOCTL IOCB abort success */
  413. #define QLAFX00_IOCTL_ICOB_ABORT_SUCCESS 0x68
  414. #endif