mpi2_pci.h 4.5 KB

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  1. /*
  2. * Copyright 2000-2020 Broadcom Inc. All rights reserved.
  3. *
  4. *
  5. * Name: mpi2_pci.h
  6. * Title: MPI PCIe Attached Devices structures and definitions.
  7. * Creation Date: October 9, 2012
  8. *
  9. * mpi2_pci.h Version: 02.00.04
  10. *
  11. * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
  12. * prefix are for use only on MPI v2.5 products, and must not be used
  13. * with MPI v2.0 products. Unless otherwise noted, names beginning with
  14. * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
  15. *
  16. * Version History
  17. * ---------------
  18. *
  19. * Date Version Description
  20. * -------- -------- ------------------------------------------------------
  21. * 03-16-15 02.00.00 Initial version.
  22. * 02-17-16 02.00.01 Removed AHCI support.
  23. * Removed SOP support.
  24. * 07-01-16 02.00.02 Added MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP to
  25. * NVME Encapsulated Request.
  26. * 07-22-18 02.00.03 Updted flags field for NVME Encapsulated req
  27. * 12-17-18 02.00.04 Added MPI26_PCIE_DEVINFO_SCSI
  28. * Shortten some defines to be compatible with DOS
  29. * --------------------------------------------------------------------------
  30. */
  31. #ifndef MPI2_PCI_H
  32. #define MPI2_PCI_H
  33. /*
  34. *Values for the PCIe DeviceInfo field used in PCIe Device Status Change Event
  35. *data and PCIe Configuration pages.
  36. */
  37. #define MPI26_PCIE_DEVINFO_DIRECT_ATTACH (0x00000010)
  38. #define MPI26_PCIE_DEVINFO_MASK_DEVICE_TYPE (0x0000000F)
  39. #define MPI26_PCIE_DEVINFO_NO_DEVICE (0x00000000)
  40. #define MPI26_PCIE_DEVINFO_PCI_SWITCH (0x00000001)
  41. #define MPI26_PCIE_DEVINFO_NVME (0x00000003)
  42. #define MPI26_PCIE_DEVINFO_SCSI (0x00000004)
  43. /****************************************************************************
  44. * NVMe Encapsulated message
  45. ****************************************************************************/
  46. /*NVME Encapsulated Request Message */
  47. typedef struct _MPI26_NVME_ENCAPSULATED_REQUEST {
  48. U16 DevHandle; /*0x00 */
  49. U8 ChainOffset; /*0x02 */
  50. U8 Function; /*0x03 */
  51. U16 EncapsulatedCommandLength; /*0x04 */
  52. U8 Reserved1; /*0x06 */
  53. U8 MsgFlags; /*0x07 */
  54. U8 VP_ID; /*0x08 */
  55. U8 VF_ID; /*0x09 */
  56. U16 Reserved2; /*0x0A */
  57. U32 Reserved3; /*0x0C */
  58. U64 ErrorResponseBaseAddress; /*0x10 */
  59. U16 ErrorResponseAllocationLength; /*0x18 */
  60. U16 Flags; /*0x1A */
  61. U32 DataLength; /*0x1C */
  62. U8 NVMe_Command[4]; /*0x20 */
  63. } MPI26_NVME_ENCAPSULATED_REQUEST, *PTR_MPI26_NVME_ENCAPSULATED_REQUEST,
  64. Mpi26NVMeEncapsulatedRequest_t, *pMpi26NVMeEncapsulatedRequest_t;
  65. /*defines for the Flags field */
  66. #define MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP (0x0020)
  67. /*Submission Queue Type*/
  68. #define MPI26_NVME_FLAGS_SUBMISSIONQ_MASK (0x0010)
  69. #define MPI26_NVME_FLAGS_SUBMISSIONQ_IO (0x0000)
  70. #define MPI26_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0010)
  71. /*Error Response Address Space */
  72. #define MPI26_NVME_FLAGS_ERR_RSP_ADDR_MASK (0x000C)
  73. #define MPI26_NVME_FLAGS_ERR_RSP_ADDR_SYSTEM (0x0000)
  74. #define MPI26_NVME_FLAGS_ERR_RSP_ADDR_IOCTL (0x0008)
  75. /* Data Direction*/
  76. #define MPI26_NVME_FLAGS_DATADIRECTION_MASK (0x0003)
  77. #define MPI26_NVME_FLAGS_NODATATRANSFER (0x0000)
  78. #define MPI26_NVME_FLAGS_WRITE (0x0001)
  79. #define MPI26_NVME_FLAGS_READ (0x0002)
  80. #define MPI26_NVME_FLAGS_BIDIRECTIONAL (0x0003)
  81. /*NVMe Encapuslated Reply Message */
  82. typedef struct _MPI26_NVME_ENCAPSULATED_ERROR_REPLY {
  83. U16 DevHandle; /*0x00 */
  84. U8 MsgLength; /*0x02 */
  85. U8 Function; /*0x03 */
  86. U16 EncapsulatedCommandLength; /*0x04 */
  87. U8 Reserved1; /*0x06 */
  88. U8 MsgFlags; /*0x07 */
  89. U8 VP_ID; /*0x08 */
  90. U8 VF_ID; /*0x09 */
  91. U16 Reserved2; /*0x0A */
  92. U16 Reserved3; /*0x0C */
  93. U16 IOCStatus; /*0x0E */
  94. U32 IOCLogInfo; /*0x10 */
  95. U16 ErrorResponseCount; /*0x14 */
  96. U16 Reserved4; /*0x16 */
  97. } MPI26_NVME_ENCAPSULATED_ERROR_REPLY,
  98. *PTR_MPI26_NVME_ENCAPSULATED_ERROR_REPLY,
  99. Mpi26NVMeEncapsulatedErrorReply_t,
  100. *pMpi26NVMeEncapsulatedErrorReply_t;
  101. #endif