ocxl_hw.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * CXL Flash Device Driver
  4. *
  5. * Written by: Matthew R. Ochs <[email protected]>, IBM Corporation
  6. * Uma Krishnan <[email protected]>, IBM Corporation
  7. *
  8. * Copyright (C) 2018 IBM Corporation
  9. */
  10. #define OCXL_MAX_IRQS 4 /* Max interrupts per process */
  11. struct ocxlflash_irqs {
  12. int hwirq;
  13. u32 virq;
  14. void __iomem *vtrig;
  15. };
  16. /* OCXL hardware AFU associated with the host */
  17. struct ocxl_hw_afu {
  18. struct ocxlflash_context *ocxl_ctx; /* Host context */
  19. struct pci_dev *pdev; /* PCI device */
  20. struct device *dev; /* Generic device */
  21. bool perst_same_image; /* Same image loaded on perst */
  22. struct ocxl_fn_config fcfg; /* DVSEC config of the function */
  23. struct ocxl_afu_config acfg; /* AFU configuration data */
  24. int fn_actag_base; /* Function acTag base */
  25. int fn_actag_enabled; /* Function acTag number enabled */
  26. int afu_actag_base; /* AFU acTag base */
  27. int afu_actag_enabled; /* AFU acTag number enabled */
  28. phys_addr_t ppmmio_phys; /* Per process MMIO space */
  29. phys_addr_t gmmio_phys; /* Global AFU MMIO space */
  30. void __iomem *gmmio_virt; /* Global MMIO map */
  31. void *link_token; /* Link token for the SPA */
  32. struct idr idr; /* IDR to manage contexts */
  33. int max_pasid; /* Maximum number of contexts */
  34. bool is_present; /* Function has AFUs defined */
  35. };
  36. enum ocxlflash_ctx_state {
  37. CLOSED,
  38. OPENED,
  39. STARTED
  40. };
  41. struct ocxlflash_context {
  42. struct ocxl_hw_afu *hw_afu; /* HW AFU back pointer */
  43. struct address_space *mapping; /* Mapping for pseudo filesystem */
  44. bool master; /* Whether this is a master context */
  45. int pe; /* Process element */
  46. phys_addr_t psn_phys; /* Process mapping */
  47. u64 psn_size; /* Process mapping size */
  48. spinlock_t slock; /* Protects irq/fault/event updates */
  49. wait_queue_head_t wq; /* Wait queue for poll and interrupts */
  50. struct mutex state_mutex; /* Mutex to update context state */
  51. enum ocxlflash_ctx_state state; /* Context state */
  52. struct ocxlflash_irqs *irqs; /* Pointer to array of structures */
  53. int num_irqs; /* Number of interrupts */
  54. bool pending_irq; /* Pending interrupt on the context */
  55. ulong irq_bitmap; /* Bits indicating pending irq num */
  56. u64 fault_addr; /* Address that triggered the fault */
  57. u64 fault_dsisr; /* Value of dsisr register at fault */
  58. bool pending_fault; /* Pending translation fault */
  59. };