aic94xx_reg.h 9.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Aic94xx SAS/SATA driver hardware registers definitions.
  4. *
  5. * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
  6. * Copyright (C) 2005 Luben Tuikov <[email protected]>
  7. */
  8. #ifndef _AIC94XX_REG_H_
  9. #define _AIC94XX_REG_H_
  10. #include <asm/io.h>
  11. #include "aic94xx_hwi.h"
  12. /* Values */
  13. #define AIC9410_DEV_REV_B0 0x8
  14. /* MBAR0, SWA, SWB, SWC, internal memory space addresses */
  15. #define REG_BASE_ADDR 0xB8000000
  16. #define REG_BASE_ADDR_CSEQCIO 0xB8002000
  17. #define REG_BASE_ADDR_EXSI 0xB8042800
  18. #define MBAR0_SWA_SIZE 0x58
  19. extern u32 MBAR0_SWB_SIZE;
  20. #define MBAR0_SWC_SIZE 0x8
  21. /* MBAR1, points to On Chip Memory */
  22. #define OCM_BASE_ADDR 0xA0000000
  23. #define OCM_MAX_SIZE 0x20000
  24. /* Smallest address possible to reference */
  25. #define ALL_BASE_ADDR OCM_BASE_ADDR
  26. /* PCI configuration space registers */
  27. #define PCI_IOBAR_OFFSET 4
  28. #define PCI_CONF_MBAR1 0x6C
  29. #define PCI_CONF_MBAR0_SWA 0x70
  30. #define PCI_CONF_MBAR0_SWB 0x74
  31. #define PCI_CONF_MBAR0_SWC 0x78
  32. #define PCI_CONF_MBAR_KEY 0x7C
  33. #define PCI_CONF_FLSH_BAR 0xB8
  34. #include "aic94xx_reg_def.h"
  35. u8 asd_read_reg_byte(struct asd_ha_struct *asd_ha, u32 reg);
  36. u16 asd_read_reg_word(struct asd_ha_struct *asd_ha, u32 reg);
  37. u32 asd_read_reg_dword(struct asd_ha_struct *asd_ha, u32 reg);
  38. void asd_write_reg_byte(struct asd_ha_struct *asd_ha, u32 reg, u8 val);
  39. void asd_write_reg_word(struct asd_ha_struct *asd_ha, u32 reg, u16 val);
  40. void asd_write_reg_dword(struct asd_ha_struct *asd_ha, u32 reg, u32 val);
  41. void asd_read_reg_string(struct asd_ha_struct *asd_ha, void *dst,
  42. u32 offs, int count);
  43. void asd_write_reg_string(struct asd_ha_struct *asd_ha, void *src,
  44. u32 offs, int count);
  45. #define ASD_READ_OCM(type, ord, S) \
  46. static inline type asd_read_ocm_##ord (struct asd_ha_struct *asd_ha, \
  47. u32 offs) \
  48. { \
  49. struct asd_ha_addrspace *io_handle = &asd_ha->io_handle[1]; \
  50. type val = read##S (io_handle->addr + (unsigned long) offs); \
  51. rmb(); \
  52. return val; \
  53. }
  54. ASD_READ_OCM(u8, byte, b);
  55. ASD_READ_OCM(u16,word, w);
  56. ASD_READ_OCM(u32,dword,l);
  57. #define ASD_WRITE_OCM(type, ord, S) \
  58. static inline void asd_write_ocm_##ord (struct asd_ha_struct *asd_ha, \
  59. u32 offs, type val) \
  60. { \
  61. struct asd_ha_addrspace *io_handle = &asd_ha->io_handle[1]; \
  62. write##S (val, io_handle->addr + (unsigned long) offs); \
  63. return; \
  64. }
  65. ASD_WRITE_OCM(u8, byte, b);
  66. ASD_WRITE_OCM(u16,word, w);
  67. ASD_WRITE_OCM(u32,dword,l);
  68. #define ASD_DDBSITE_READ(type, ord) \
  69. static inline type asd_ddbsite_read_##ord (struct asd_ha_struct *asd_ha, \
  70. u16 ddb_site_no, \
  71. u16 offs) \
  72. { \
  73. asd_write_reg_word(asd_ha, ALTCIOADR, MnDDB_SITE + offs); \
  74. asd_write_reg_word(asd_ha, ADDBPTR, ddb_site_no); \
  75. return asd_read_reg_##ord (asd_ha, CTXACCESS); \
  76. }
  77. ASD_DDBSITE_READ(u32, dword);
  78. ASD_DDBSITE_READ(u16, word);
  79. static inline u8 asd_ddbsite_read_byte(struct asd_ha_struct *asd_ha,
  80. u16 ddb_site_no,
  81. u16 offs)
  82. {
  83. if (offs & 1)
  84. return asd_ddbsite_read_word(asd_ha, ddb_site_no,
  85. offs & ~1) >> 8;
  86. else
  87. return asd_ddbsite_read_word(asd_ha, ddb_site_no,
  88. offs) & 0xFF;
  89. }
  90. #define ASD_DDBSITE_WRITE(type, ord) \
  91. static inline void asd_ddbsite_write_##ord (struct asd_ha_struct *asd_ha, \
  92. u16 ddb_site_no, \
  93. u16 offs, type val) \
  94. { \
  95. asd_write_reg_word(asd_ha, ALTCIOADR, MnDDB_SITE + offs); \
  96. asd_write_reg_word(asd_ha, ADDBPTR, ddb_site_no); \
  97. asd_write_reg_##ord (asd_ha, CTXACCESS, val); \
  98. }
  99. ASD_DDBSITE_WRITE(u32, dword);
  100. ASD_DDBSITE_WRITE(u16, word);
  101. static inline void asd_ddbsite_write_byte(struct asd_ha_struct *asd_ha,
  102. u16 ddb_site_no,
  103. u16 offs, u8 val)
  104. {
  105. u16 base = offs & ~1;
  106. u16 rval = asd_ddbsite_read_word(asd_ha, ddb_site_no, base);
  107. if (offs & 1)
  108. rval = (val << 8) | (rval & 0xFF);
  109. else
  110. rval = (rval & 0xFF00) | val;
  111. asd_ddbsite_write_word(asd_ha, ddb_site_no, base, rval);
  112. }
  113. #define ASD_SCBSITE_READ(type, ord) \
  114. static inline type asd_scbsite_read_##ord (struct asd_ha_struct *asd_ha, \
  115. u16 scb_site_no, \
  116. u16 offs) \
  117. { \
  118. asd_write_reg_word(asd_ha, ALTCIOADR, MnSCB_SITE + offs); \
  119. asd_write_reg_word(asd_ha, ASCBPTR, scb_site_no); \
  120. return asd_read_reg_##ord (asd_ha, CTXACCESS); \
  121. }
  122. ASD_SCBSITE_READ(u32, dword);
  123. ASD_SCBSITE_READ(u16, word);
  124. static inline u8 asd_scbsite_read_byte(struct asd_ha_struct *asd_ha,
  125. u16 scb_site_no,
  126. u16 offs)
  127. {
  128. if (offs & 1)
  129. return asd_scbsite_read_word(asd_ha, scb_site_no,
  130. offs & ~1) >> 8;
  131. else
  132. return asd_scbsite_read_word(asd_ha, scb_site_no,
  133. offs) & 0xFF;
  134. }
  135. #define ASD_SCBSITE_WRITE(type, ord) \
  136. static inline void asd_scbsite_write_##ord (struct asd_ha_struct *asd_ha, \
  137. u16 scb_site_no, \
  138. u16 offs, type val) \
  139. { \
  140. asd_write_reg_word(asd_ha, ALTCIOADR, MnSCB_SITE + offs); \
  141. asd_write_reg_word(asd_ha, ASCBPTR, scb_site_no); \
  142. asd_write_reg_##ord (asd_ha, CTXACCESS, val); \
  143. }
  144. ASD_SCBSITE_WRITE(u32, dword);
  145. ASD_SCBSITE_WRITE(u16, word);
  146. static inline void asd_scbsite_write_byte(struct asd_ha_struct *asd_ha,
  147. u16 scb_site_no,
  148. u16 offs, u8 val)
  149. {
  150. u16 base = offs & ~1;
  151. u16 rval = asd_scbsite_read_word(asd_ha, scb_site_no, base);
  152. if (offs & 1)
  153. rval = (val << 8) | (rval & 0xFF);
  154. else
  155. rval = (rval & 0xFF00) | val;
  156. asd_scbsite_write_word(asd_ha, scb_site_no, base, rval);
  157. }
  158. /**
  159. * asd_ddbsite_update_word -- atomically update a word in a ddb site
  160. * @asd_ha: pointer to host adapter structure
  161. * @ddb_site_no: the DDB site number
  162. * @offs: the offset into the DDB
  163. * @oldval: old value found in that offset
  164. * @newval: the new value to replace it
  165. *
  166. * This function is used when the sequencers are running and we need to
  167. * update a DDB site atomically without expensive pausing and upausing
  168. * of the sequencers and accessing the DDB site through the CIO bus.
  169. *
  170. * Return 0 on success; -EFAULT on parity error; -EAGAIN if the old value
  171. * is different than the current value at that offset.
  172. */
  173. static inline int asd_ddbsite_update_word(struct asd_ha_struct *asd_ha,
  174. u16 ddb_site_no, u16 offs,
  175. u16 oldval, u16 newval)
  176. {
  177. u8 done;
  178. u16 oval = asd_ddbsite_read_word(asd_ha, ddb_site_no, offs);
  179. if (oval != oldval)
  180. return -EAGAIN;
  181. asd_write_reg_word(asd_ha, AOLDDATA, oldval);
  182. asd_write_reg_word(asd_ha, ANEWDATA, newval);
  183. do {
  184. done = asd_read_reg_byte(asd_ha, ATOMICSTATCTL);
  185. } while (!(done & ATOMICDONE));
  186. if (done & ATOMICERR)
  187. return -EFAULT; /* parity error */
  188. else if (done & ATOMICWIN)
  189. return 0; /* success */
  190. else
  191. return -EAGAIN; /* oldval different than current value */
  192. }
  193. static inline int asd_ddbsite_update_byte(struct asd_ha_struct *asd_ha,
  194. u16 ddb_site_no, u16 offs,
  195. u8 _oldval, u8 _newval)
  196. {
  197. u16 base = offs & ~1;
  198. u16 oval;
  199. u16 nval = asd_ddbsite_read_word(asd_ha, ddb_site_no, base);
  200. if (offs & 1) {
  201. if ((nval >> 8) != _oldval)
  202. return -EAGAIN;
  203. nval = (_newval << 8) | (nval & 0xFF);
  204. oval = (_oldval << 8) | (nval & 0xFF);
  205. } else {
  206. if ((nval & 0xFF) != _oldval)
  207. return -EAGAIN;
  208. nval = (nval & 0xFF00) | _newval;
  209. oval = (nval & 0xFF00) | _oldval;
  210. }
  211. return asd_ddbsite_update_word(asd_ha, ddb_site_no, base, oval, nval);
  212. }
  213. static inline void asd_write_reg_addr(struct asd_ha_struct *asd_ha, u32 reg,
  214. dma_addr_t dma_handle)
  215. {
  216. asd_write_reg_dword(asd_ha, reg, ASD_BUSADDR_LO(dma_handle));
  217. asd_write_reg_dword(asd_ha, reg+4, ASD_BUSADDR_HI(dma_handle));
  218. }
  219. static inline u32 asd_get_cmdctx_size(struct asd_ha_struct *asd_ha)
  220. {
  221. /* DCHREVISION returns 0, possibly broken */
  222. u32 ctxmemsize = asd_read_reg_dword(asd_ha, LmMnINT(0,0)) & CTXMEMSIZE;
  223. return ctxmemsize ? 65536 : 32768;
  224. }
  225. static inline u32 asd_get_devctx_size(struct asd_ha_struct *asd_ha)
  226. {
  227. u32 ctxmemsize = asd_read_reg_dword(asd_ha, LmMnINT(0,0)) & CTXMEMSIZE;
  228. return ctxmemsize ? 8192 : 4096;
  229. }
  230. static inline void asd_disable_ints(struct asd_ha_struct *asd_ha)
  231. {
  232. asd_write_reg_dword(asd_ha, CHIMINTEN, RST_CHIMINTEN);
  233. }
  234. static inline void asd_enable_ints(struct asd_ha_struct *asd_ha)
  235. {
  236. /* Enable COM SAS interrupt on errors, COMSTAT */
  237. asd_write_reg_dword(asd_ha, COMSTATEN,
  238. EN_CSBUFPERR | EN_CSERR | EN_OVLYERR);
  239. /* Enable DCH SAS CFIFTOERR */
  240. asd_write_reg_dword(asd_ha, DCHSTATUS, EN_CFIFTOERR);
  241. /* Enable Host Device interrupts */
  242. asd_write_reg_dword(asd_ha, CHIMINTEN, SET_CHIMINTEN);
  243. }
  244. #endif