aic7xxx_osm_pci.c 12 KB

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  1. /*
  2. * Linux driver attachment glue for PCI based controllers.
  3. *
  4. * Copyright (c) 2000-2001 Adaptec Inc.
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14. * substantially similar to the "NO WARRANTY" disclaimer below
  15. * ("Disclaimer") and any redistribution must be conditioned upon
  16. * including a substantially similar Disclaimer requirement for further
  17. * binary redistribution.
  18. * 3. Neither the names of the above-listed copyright holders nor the names
  19. * of any contributors may be used to endorse or promote products derived
  20. * from this software without specific prior written permission.
  21. *
  22. * Alternatively, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2 as published by the Free
  24. * Software Foundation.
  25. *
  26. * NO WARRANTY
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37. * POSSIBILITY OF SUCH DAMAGES.
  38. *
  39. * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c#47 $
  40. */
  41. #include "aic7xxx_osm.h"
  42. #include "aic7xxx_pci.h"
  43. /* Define the macro locally since it's different for different class of chips.
  44. */
  45. #define ID(x) ID_C(x, PCI_CLASS_STORAGE_SCSI)
  46. static const struct pci_device_id ahc_linux_pci_id_table[] = {
  47. /* aic7850 based controllers */
  48. ID(ID_AHA_2902_04_10_15_20C_30C),
  49. /* aic7860 based controllers */
  50. ID(ID_AHA_2930CU),
  51. ID(ID_AHA_1480A & ID_DEV_VENDOR_MASK),
  52. ID(ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK),
  53. ID(ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK),
  54. ID(ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK),
  55. /* aic7870 based controllers */
  56. ID(ID_AHA_2940),
  57. ID(ID_AHA_3940),
  58. ID(ID_AHA_398X),
  59. ID(ID_AHA_2944),
  60. ID(ID_AHA_3944),
  61. ID(ID_AHA_4944),
  62. /* aic7880 based controllers */
  63. ID(ID_AHA_2940U & ID_DEV_VENDOR_MASK),
  64. ID(ID_AHA_3940U & ID_DEV_VENDOR_MASK),
  65. ID(ID_AHA_2944U & ID_DEV_VENDOR_MASK),
  66. ID(ID_AHA_3944U & ID_DEV_VENDOR_MASK),
  67. ID(ID_AHA_398XU & ID_DEV_VENDOR_MASK),
  68. ID(ID_AHA_4944U & ID_DEV_VENDOR_MASK),
  69. ID(ID_AHA_2930U & ID_DEV_VENDOR_MASK),
  70. ID(ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK),
  71. ID(ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK),
  72. /* aic7890 based controllers */
  73. ID(ID_AHA_2930U2),
  74. ID(ID_AHA_2940U2B),
  75. ID(ID_AHA_2940U2_OEM),
  76. ID(ID_AHA_2940U2),
  77. ID(ID_AHA_2950U2B),
  78. ID16(ID_AIC7890_ARO & ID_AIC7895_ARO_MASK),
  79. ID(ID_AAA_131U2),
  80. /* aic7890 based controllers */
  81. ID(ID_AHA_29160),
  82. ID(ID_AHA_29160_CPQ),
  83. ID(ID_AHA_29160N),
  84. ID(ID_AHA_29160C),
  85. ID(ID_AHA_29160B),
  86. ID(ID_AHA_19160B),
  87. ID(ID_AIC7892_ARO),
  88. /* aic7892 based controllers */
  89. ID(ID_AHA_2940U_DUAL),
  90. ID(ID_AHA_3940AU),
  91. ID(ID_AHA_3944AU),
  92. ID(ID_AIC7895_ARO),
  93. ID(ID_AHA_3950U2B_0),
  94. ID(ID_AHA_3950U2B_1),
  95. ID(ID_AHA_3950U2D_0),
  96. ID(ID_AHA_3950U2D_1),
  97. ID(ID_AIC7896_ARO),
  98. /* aic7899 based controllers */
  99. ID(ID_AHA_3960D),
  100. ID(ID_AHA_3960D_CPQ),
  101. ID(ID_AIC7899_ARO),
  102. /* Generic chip probes for devices we don't know exactly. */
  103. ID(ID_AIC7850 & ID_DEV_VENDOR_MASK),
  104. ID(ID_AIC7855 & ID_DEV_VENDOR_MASK),
  105. ID(ID_AIC7859 & ID_DEV_VENDOR_MASK),
  106. ID(ID_AIC7860 & ID_DEV_VENDOR_MASK),
  107. ID(ID_AIC7870 & ID_DEV_VENDOR_MASK),
  108. ID(ID_AIC7880 & ID_DEV_VENDOR_MASK),
  109. ID16(ID_AIC7890 & ID_9005_GENERIC_MASK),
  110. ID16(ID_AIC7892 & ID_9005_GENERIC_MASK),
  111. ID(ID_AIC7895 & ID_DEV_VENDOR_MASK),
  112. ID16(ID_AIC7896 & ID_9005_GENERIC_MASK),
  113. ID16(ID_AIC7899 & ID_9005_GENERIC_MASK),
  114. ID(ID_AIC7810 & ID_DEV_VENDOR_MASK),
  115. ID(ID_AIC7815 & ID_DEV_VENDOR_MASK),
  116. { 0 }
  117. };
  118. MODULE_DEVICE_TABLE(pci, ahc_linux_pci_id_table);
  119. static int __maybe_unused
  120. ahc_linux_pci_dev_suspend(struct device *dev)
  121. {
  122. struct ahc_softc *ahc = dev_get_drvdata(dev);
  123. return ahc_suspend(ahc);
  124. }
  125. static int __maybe_unused
  126. ahc_linux_pci_dev_resume(struct device *dev)
  127. {
  128. struct ahc_softc *ahc = dev_get_drvdata(dev);
  129. ahc_pci_resume(ahc);
  130. return (ahc_resume(ahc));
  131. }
  132. static void
  133. ahc_linux_pci_dev_remove(struct pci_dev *pdev)
  134. {
  135. struct ahc_softc *ahc = pci_get_drvdata(pdev);
  136. u_long s;
  137. if (ahc->platform_data && ahc->platform_data->host)
  138. scsi_remove_host(ahc->platform_data->host);
  139. ahc_lock(ahc, &s);
  140. ahc_intr_enable(ahc, FALSE);
  141. ahc_unlock(ahc, &s);
  142. ahc_free(ahc);
  143. }
  144. static void
  145. ahc_linux_pci_inherit_flags(struct ahc_softc *ahc)
  146. {
  147. struct pci_dev *pdev = ahc->dev_softc, *master_pdev;
  148. unsigned int master_devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
  149. master_pdev = pci_get_slot(pdev->bus, master_devfn);
  150. if (master_pdev) {
  151. struct ahc_softc *master = pci_get_drvdata(master_pdev);
  152. if (master) {
  153. ahc->flags &= ~AHC_BIOS_ENABLED;
  154. ahc->flags |= master->flags & AHC_BIOS_ENABLED;
  155. ahc->flags &= ~AHC_PRIMARY_CHANNEL;
  156. ahc->flags |= master->flags & AHC_PRIMARY_CHANNEL;
  157. } else
  158. printk(KERN_ERR "aic7xxx: no multichannel peer found!\n");
  159. pci_dev_put(master_pdev);
  160. }
  161. }
  162. static int
  163. ahc_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  164. {
  165. char buf[80];
  166. const uint64_t mask_39bit = 0x7FFFFFFFFFULL;
  167. struct ahc_softc *ahc;
  168. ahc_dev_softc_t pci;
  169. const struct ahc_pci_identity *entry;
  170. char *name;
  171. int error;
  172. struct device *dev = &pdev->dev;
  173. pci = pdev;
  174. entry = ahc_find_pci_device(pci);
  175. if (entry == NULL)
  176. return (-ENODEV);
  177. /*
  178. * Allocate a softc for this card and
  179. * set it up for attachment by our
  180. * common detect routine.
  181. */
  182. sprintf(buf, "ahc_pci:%d:%d:%d",
  183. ahc_get_pci_bus(pci),
  184. ahc_get_pci_slot(pci),
  185. ahc_get_pci_function(pci));
  186. name = kstrdup(buf, GFP_ATOMIC);
  187. if (name == NULL)
  188. return (-ENOMEM);
  189. ahc = ahc_alloc(NULL, name);
  190. if (ahc == NULL)
  191. return (-ENOMEM);
  192. if (pci_enable_device(pdev)) {
  193. ahc_free(ahc);
  194. return (-ENODEV);
  195. }
  196. pci_set_master(pdev);
  197. if (sizeof(dma_addr_t) > 4
  198. && ahc->features & AHC_LARGE_SCBS
  199. && dma_set_mask(dev, mask_39bit) == 0
  200. && dma_get_required_mask(dev) > DMA_BIT_MASK(32)) {
  201. ahc->flags |= AHC_39BIT_ADDRESSING;
  202. } else {
  203. if (dma_set_mask(dev, DMA_BIT_MASK(32))) {
  204. ahc_free(ahc);
  205. printk(KERN_WARNING "aic7xxx: No suitable DMA available.\n");
  206. return (-ENODEV);
  207. }
  208. }
  209. ahc->dev_softc = pci;
  210. ahc->dev = &pci->dev;
  211. error = ahc_pci_config(ahc, entry);
  212. if (error != 0) {
  213. ahc_free(ahc);
  214. return (-error);
  215. }
  216. /*
  217. * Second Function PCI devices need to inherit some
  218. * settings from function 0.
  219. */
  220. if ((ahc->features & AHC_MULTI_FUNC) && PCI_FUNC(pdev->devfn) != 0)
  221. ahc_linux_pci_inherit_flags(ahc);
  222. pci_set_drvdata(pdev, ahc);
  223. ahc_linux_register_host(ahc, &aic7xxx_driver_template);
  224. return (0);
  225. }
  226. /******************************* PCI Routines *********************************/
  227. uint32_t
  228. ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width)
  229. {
  230. switch (width) {
  231. case 1:
  232. {
  233. uint8_t retval;
  234. pci_read_config_byte(pci, reg, &retval);
  235. return (retval);
  236. }
  237. case 2:
  238. {
  239. uint16_t retval;
  240. pci_read_config_word(pci, reg, &retval);
  241. return (retval);
  242. }
  243. case 4:
  244. {
  245. uint32_t retval;
  246. pci_read_config_dword(pci, reg, &retval);
  247. return (retval);
  248. }
  249. default:
  250. panic("ahc_pci_read_config: Read size too big");
  251. /* NOTREACHED */
  252. return (0);
  253. }
  254. }
  255. void
  256. ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width)
  257. {
  258. switch (width) {
  259. case 1:
  260. pci_write_config_byte(pci, reg, value);
  261. break;
  262. case 2:
  263. pci_write_config_word(pci, reg, value);
  264. break;
  265. case 4:
  266. pci_write_config_dword(pci, reg, value);
  267. break;
  268. default:
  269. panic("ahc_pci_write_config: Write size too big");
  270. /* NOTREACHED */
  271. }
  272. }
  273. static SIMPLE_DEV_PM_OPS(ahc_linux_pci_dev_pm_ops,
  274. ahc_linux_pci_dev_suspend,
  275. ahc_linux_pci_dev_resume);
  276. static struct pci_driver aic7xxx_pci_driver = {
  277. .name = "aic7xxx",
  278. .probe = ahc_linux_pci_dev_probe,
  279. .driver.pm = &ahc_linux_pci_dev_pm_ops,
  280. .remove = ahc_linux_pci_dev_remove,
  281. .id_table = ahc_linux_pci_id_table
  282. };
  283. int
  284. ahc_linux_pci_init(void)
  285. {
  286. return pci_register_driver(&aic7xxx_pci_driver);
  287. }
  288. void
  289. ahc_linux_pci_exit(void)
  290. {
  291. pci_unregister_driver(&aic7xxx_pci_driver);
  292. }
  293. static int
  294. ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, resource_size_t *base)
  295. {
  296. if (aic7xxx_allow_memio == 0)
  297. return (ENOMEM);
  298. *base = pci_resource_start(ahc->dev_softc, 0);
  299. if (*base == 0)
  300. return (ENOMEM);
  301. if (!request_region(*base, 256, "aic7xxx"))
  302. return (ENOMEM);
  303. return (0);
  304. }
  305. static int
  306. ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
  307. resource_size_t *bus_addr,
  308. uint8_t __iomem **maddr)
  309. {
  310. resource_size_t start;
  311. int error;
  312. error = 0;
  313. start = pci_resource_start(ahc->dev_softc, 1);
  314. if (start != 0) {
  315. *bus_addr = start;
  316. if (!request_mem_region(start, 0x1000, "aic7xxx"))
  317. error = ENOMEM;
  318. if (error == 0) {
  319. *maddr = ioremap(start, 256);
  320. if (*maddr == NULL) {
  321. error = ENOMEM;
  322. release_mem_region(start, 0x1000);
  323. }
  324. }
  325. } else
  326. error = ENOMEM;
  327. return (error);
  328. }
  329. int
  330. ahc_pci_map_registers(struct ahc_softc *ahc)
  331. {
  332. uint32_t command;
  333. resource_size_t base;
  334. uint8_t __iomem *maddr;
  335. int error;
  336. /*
  337. * If its allowed, we prefer memory mapped access.
  338. */
  339. command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, 4);
  340. command &= ~(PCIM_CMD_PORTEN|PCIM_CMD_MEMEN);
  341. base = 0;
  342. maddr = NULL;
  343. error = ahc_linux_pci_reserve_mem_region(ahc, &base, &maddr);
  344. if (error == 0) {
  345. ahc->platform_data->mem_busaddr = base;
  346. ahc->tag = BUS_SPACE_MEMIO;
  347. ahc->bsh.maddr = maddr;
  348. ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
  349. command | PCIM_CMD_MEMEN, 4);
  350. /*
  351. * Do a quick test to see if memory mapped
  352. * I/O is functioning correctly.
  353. */
  354. if (ahc_pci_test_register_access(ahc) != 0) {
  355. printk("aic7xxx: PCI Device %d:%d:%d "
  356. "failed memory mapped test. Using PIO.\n",
  357. ahc_get_pci_bus(ahc->dev_softc),
  358. ahc_get_pci_slot(ahc->dev_softc),
  359. ahc_get_pci_function(ahc->dev_softc));
  360. iounmap(maddr);
  361. release_mem_region(ahc->platform_data->mem_busaddr,
  362. 0x1000);
  363. ahc->bsh.maddr = NULL;
  364. maddr = NULL;
  365. } else
  366. command |= PCIM_CMD_MEMEN;
  367. } else {
  368. printk("aic7xxx: PCI%d:%d:%d MEM region 0x%llx "
  369. "unavailable. Cannot memory map device.\n",
  370. ahc_get_pci_bus(ahc->dev_softc),
  371. ahc_get_pci_slot(ahc->dev_softc),
  372. ahc_get_pci_function(ahc->dev_softc),
  373. (unsigned long long)base);
  374. }
  375. /*
  376. * We always prefer memory mapped access.
  377. */
  378. if (maddr == NULL) {
  379. error = ahc_linux_pci_reserve_io_region(ahc, &base);
  380. if (error == 0) {
  381. ahc->tag = BUS_SPACE_PIO;
  382. ahc->bsh.ioport = (u_long)base;
  383. command |= PCIM_CMD_PORTEN;
  384. } else {
  385. printk("aic7xxx: PCI%d:%d:%d IO region 0x%llx[0..255] "
  386. "unavailable. Cannot map device.\n",
  387. ahc_get_pci_bus(ahc->dev_softc),
  388. ahc_get_pci_slot(ahc->dev_softc),
  389. ahc_get_pci_function(ahc->dev_softc),
  390. (unsigned long long)base);
  391. }
  392. }
  393. ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4);
  394. return (error);
  395. }
  396. int
  397. ahc_pci_map_int(struct ahc_softc *ahc)
  398. {
  399. int error;
  400. error = request_irq(ahc->dev_softc->irq, ahc_linux_isr,
  401. IRQF_SHARED, "aic7xxx", ahc);
  402. if (error == 0)
  403. ahc->platform_data->irq = ahc->dev_softc->irq;
  404. return (-error);
  405. }