rtc-sh.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SuperH On-Chip RTC Support
  4. *
  5. * Copyright (C) 2006 - 2009 Paul Mundt
  6. * Copyright (C) 2006 Jamie Lenehan
  7. * Copyright (C) 2008 Angelo Castello
  8. *
  9. * Based on the old arch/sh/kernel/cpu/rtc.c by:
  10. *
  11. * Copyright (C) 2000 Philipp Rumpf <[email protected]>
  12. * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
  13. */
  14. #include <linux/module.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/kernel.h>
  17. #include <linux/bcd.h>
  18. #include <linux/rtc.h>
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/seq_file.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/io.h>
  25. #include <linux/log2.h>
  26. #include <linux/clk.h>
  27. #include <linux/slab.h>
  28. #ifdef CONFIG_SUPERH
  29. #include <asm/rtc.h>
  30. #else
  31. /* Default values for RZ/A RTC */
  32. #define rtc_reg_size sizeof(u16)
  33. #define RTC_BIT_INVERTED 0 /* no chip bugs */
  34. #define RTC_CAP_4_DIGIT_YEAR (1 << 0)
  35. #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
  36. #endif
  37. #define DRV_NAME "sh-rtc"
  38. #define RTC_REG(r) ((r) * rtc_reg_size)
  39. #define R64CNT RTC_REG(0)
  40. #define RSECCNT RTC_REG(1) /* RTC sec */
  41. #define RMINCNT RTC_REG(2) /* RTC min */
  42. #define RHRCNT RTC_REG(3) /* RTC hour */
  43. #define RWKCNT RTC_REG(4) /* RTC week */
  44. #define RDAYCNT RTC_REG(5) /* RTC day */
  45. #define RMONCNT RTC_REG(6) /* RTC month */
  46. #define RYRCNT RTC_REG(7) /* RTC year */
  47. #define RSECAR RTC_REG(8) /* ALARM sec */
  48. #define RMINAR RTC_REG(9) /* ALARM min */
  49. #define RHRAR RTC_REG(10) /* ALARM hour */
  50. #define RWKAR RTC_REG(11) /* ALARM week */
  51. #define RDAYAR RTC_REG(12) /* ALARM day */
  52. #define RMONAR RTC_REG(13) /* ALARM month */
  53. #define RCR1 RTC_REG(14) /* Control */
  54. #define RCR2 RTC_REG(15) /* Control */
  55. /*
  56. * Note on RYRAR and RCR3: Up until this point most of the register
  57. * definitions are consistent across all of the available parts. However,
  58. * the placement of the optional RYRAR and RCR3 (the RYRAR control
  59. * register used to control RYRCNT/RYRAR compare) varies considerably
  60. * across various parts, occasionally being mapped in to a completely
  61. * unrelated address space. For proper RYRAR support a separate resource
  62. * would have to be handed off, but as this is purely optional in
  63. * practice, we simply opt not to support it, thereby keeping the code
  64. * quite a bit more simplified.
  65. */
  66. /* ALARM Bits - or with BCD encoded value */
  67. #define AR_ENB 0x80 /* Enable for alarm cmp */
  68. /* Period Bits */
  69. #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
  70. #define PF_COUNT 0x200 /* Half periodic counter */
  71. #define PF_OXS 0x400 /* Periodic One x Second */
  72. #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
  73. #define PF_MASK 0xf00
  74. /* RCR1 Bits */
  75. #define RCR1_CF 0x80 /* Carry Flag */
  76. #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
  77. #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
  78. #define RCR1_AF 0x01 /* Alarm Flag */
  79. /* RCR2 Bits */
  80. #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
  81. #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
  82. #define RCR2_RTCEN 0x08 /* ENable RTC */
  83. #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
  84. #define RCR2_RESET 0x02 /* Reset bit */
  85. #define RCR2_START 0x01 /* Start bit */
  86. struct sh_rtc {
  87. void __iomem *regbase;
  88. unsigned long regsize;
  89. struct resource *res;
  90. int alarm_irq;
  91. int periodic_irq;
  92. int carry_irq;
  93. struct clk *clk;
  94. struct rtc_device *rtc_dev;
  95. spinlock_t lock;
  96. unsigned long capabilities; /* See asm/rtc.h for cap bits */
  97. unsigned short periodic_freq;
  98. };
  99. static int __sh_rtc_interrupt(struct sh_rtc *rtc)
  100. {
  101. unsigned int tmp, pending;
  102. tmp = readb(rtc->regbase + RCR1);
  103. pending = tmp & RCR1_CF;
  104. tmp &= ~RCR1_CF;
  105. writeb(tmp, rtc->regbase + RCR1);
  106. /* Users have requested One x Second IRQ */
  107. if (pending && rtc->periodic_freq & PF_OXS)
  108. rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
  109. return pending;
  110. }
  111. static int __sh_rtc_alarm(struct sh_rtc *rtc)
  112. {
  113. unsigned int tmp, pending;
  114. tmp = readb(rtc->regbase + RCR1);
  115. pending = tmp & RCR1_AF;
  116. tmp &= ~(RCR1_AF | RCR1_AIE);
  117. writeb(tmp, rtc->regbase + RCR1);
  118. if (pending)
  119. rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
  120. return pending;
  121. }
  122. static int __sh_rtc_periodic(struct sh_rtc *rtc)
  123. {
  124. unsigned int tmp, pending;
  125. tmp = readb(rtc->regbase + RCR2);
  126. pending = tmp & RCR2_PEF;
  127. tmp &= ~RCR2_PEF;
  128. writeb(tmp, rtc->regbase + RCR2);
  129. if (!pending)
  130. return 0;
  131. /* Half period enabled than one skipped and the next notified */
  132. if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
  133. rtc->periodic_freq &= ~PF_COUNT;
  134. else {
  135. if (rtc->periodic_freq & PF_HP)
  136. rtc->periodic_freq |= PF_COUNT;
  137. rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
  138. }
  139. return pending;
  140. }
  141. static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
  142. {
  143. struct sh_rtc *rtc = dev_id;
  144. int ret;
  145. spin_lock(&rtc->lock);
  146. ret = __sh_rtc_interrupt(rtc);
  147. spin_unlock(&rtc->lock);
  148. return IRQ_RETVAL(ret);
  149. }
  150. static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
  151. {
  152. struct sh_rtc *rtc = dev_id;
  153. int ret;
  154. spin_lock(&rtc->lock);
  155. ret = __sh_rtc_alarm(rtc);
  156. spin_unlock(&rtc->lock);
  157. return IRQ_RETVAL(ret);
  158. }
  159. static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
  160. {
  161. struct sh_rtc *rtc = dev_id;
  162. int ret;
  163. spin_lock(&rtc->lock);
  164. ret = __sh_rtc_periodic(rtc);
  165. spin_unlock(&rtc->lock);
  166. return IRQ_RETVAL(ret);
  167. }
  168. static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
  169. {
  170. struct sh_rtc *rtc = dev_id;
  171. int ret;
  172. spin_lock(&rtc->lock);
  173. ret = __sh_rtc_interrupt(rtc);
  174. ret |= __sh_rtc_alarm(rtc);
  175. ret |= __sh_rtc_periodic(rtc);
  176. spin_unlock(&rtc->lock);
  177. return IRQ_RETVAL(ret);
  178. }
  179. static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
  180. {
  181. struct sh_rtc *rtc = dev_get_drvdata(dev);
  182. unsigned int tmp;
  183. spin_lock_irq(&rtc->lock);
  184. tmp = readb(rtc->regbase + RCR1);
  185. if (enable)
  186. tmp |= RCR1_AIE;
  187. else
  188. tmp &= ~RCR1_AIE;
  189. writeb(tmp, rtc->regbase + RCR1);
  190. spin_unlock_irq(&rtc->lock);
  191. }
  192. static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
  193. {
  194. struct sh_rtc *rtc = dev_get_drvdata(dev);
  195. unsigned int tmp;
  196. tmp = readb(rtc->regbase + RCR1);
  197. seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
  198. tmp = readb(rtc->regbase + RCR2);
  199. seq_printf(seq, "periodic_IRQ\t: %s\n",
  200. (tmp & RCR2_PESMASK) ? "yes" : "no");
  201. return 0;
  202. }
  203. static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
  204. {
  205. struct sh_rtc *rtc = dev_get_drvdata(dev);
  206. unsigned int tmp;
  207. spin_lock_irq(&rtc->lock);
  208. tmp = readb(rtc->regbase + RCR1);
  209. if (!enable)
  210. tmp &= ~RCR1_CIE;
  211. else
  212. tmp |= RCR1_CIE;
  213. writeb(tmp, rtc->regbase + RCR1);
  214. spin_unlock_irq(&rtc->lock);
  215. }
  216. static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  217. {
  218. sh_rtc_setaie(dev, enabled);
  219. return 0;
  220. }
  221. static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
  222. {
  223. struct sh_rtc *rtc = dev_get_drvdata(dev);
  224. unsigned int sec128, sec2, yr, yr100, cf_bit;
  225. if (!(readb(rtc->regbase + RCR2) & RCR2_RTCEN))
  226. return -EINVAL;
  227. do {
  228. unsigned int tmp;
  229. spin_lock_irq(&rtc->lock);
  230. tmp = readb(rtc->regbase + RCR1);
  231. tmp &= ~RCR1_CF; /* Clear CF-bit */
  232. tmp |= RCR1_CIE;
  233. writeb(tmp, rtc->regbase + RCR1);
  234. sec128 = readb(rtc->regbase + R64CNT);
  235. tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
  236. tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
  237. tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
  238. tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
  239. tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
  240. tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
  241. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  242. yr = readw(rtc->regbase + RYRCNT);
  243. yr100 = bcd2bin(yr >> 8);
  244. yr &= 0xff;
  245. } else {
  246. yr = readb(rtc->regbase + RYRCNT);
  247. yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
  248. }
  249. tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
  250. sec2 = readb(rtc->regbase + R64CNT);
  251. cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
  252. spin_unlock_irq(&rtc->lock);
  253. } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
  254. #if RTC_BIT_INVERTED != 0
  255. if ((sec128 & RTC_BIT_INVERTED))
  256. tm->tm_sec--;
  257. #endif
  258. /* only keep the carry interrupt enabled if UIE is on */
  259. if (!(rtc->periodic_freq & PF_OXS))
  260. sh_rtc_setcie(dev, 0);
  261. dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
  262. "mday=%d, mon=%d, year=%d, wday=%d\n",
  263. __func__,
  264. tm->tm_sec, tm->tm_min, tm->tm_hour,
  265. tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
  266. return 0;
  267. }
  268. static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
  269. {
  270. struct sh_rtc *rtc = dev_get_drvdata(dev);
  271. unsigned int tmp;
  272. int year;
  273. spin_lock_irq(&rtc->lock);
  274. /* Reset pre-scaler & stop RTC */
  275. tmp = readb(rtc->regbase + RCR2);
  276. tmp |= RCR2_RESET;
  277. tmp &= ~RCR2_START;
  278. writeb(tmp, rtc->regbase + RCR2);
  279. writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
  280. writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
  281. writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
  282. writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
  283. writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
  284. writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
  285. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  286. year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
  287. bin2bcd(tm->tm_year % 100);
  288. writew(year, rtc->regbase + RYRCNT);
  289. } else {
  290. year = tm->tm_year % 100;
  291. writeb(bin2bcd(year), rtc->regbase + RYRCNT);
  292. }
  293. /* Start RTC */
  294. tmp = readb(rtc->regbase + RCR2);
  295. tmp &= ~RCR2_RESET;
  296. tmp |= RCR2_RTCEN | RCR2_START;
  297. writeb(tmp, rtc->regbase + RCR2);
  298. spin_unlock_irq(&rtc->lock);
  299. return 0;
  300. }
  301. static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
  302. {
  303. unsigned int byte;
  304. int value = -1; /* return -1 for ignored values */
  305. byte = readb(rtc->regbase + reg_off);
  306. if (byte & AR_ENB) {
  307. byte &= ~AR_ENB; /* strip the enable bit */
  308. value = bcd2bin(byte);
  309. }
  310. return value;
  311. }
  312. static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  313. {
  314. struct sh_rtc *rtc = dev_get_drvdata(dev);
  315. struct rtc_time *tm = &wkalrm->time;
  316. spin_lock_irq(&rtc->lock);
  317. tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
  318. tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
  319. tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
  320. tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
  321. tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
  322. tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
  323. if (tm->tm_mon > 0)
  324. tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
  325. wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
  326. spin_unlock_irq(&rtc->lock);
  327. return 0;
  328. }
  329. static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
  330. int value, int reg_off)
  331. {
  332. /* < 0 for a value that is ignored */
  333. if (value < 0)
  334. writeb(0, rtc->regbase + reg_off);
  335. else
  336. writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
  337. }
  338. static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  339. {
  340. struct sh_rtc *rtc = dev_get_drvdata(dev);
  341. unsigned int rcr1;
  342. struct rtc_time *tm = &wkalrm->time;
  343. int mon;
  344. spin_lock_irq(&rtc->lock);
  345. /* disable alarm interrupt and clear the alarm flag */
  346. rcr1 = readb(rtc->regbase + RCR1);
  347. rcr1 &= ~(RCR1_AF | RCR1_AIE);
  348. writeb(rcr1, rtc->regbase + RCR1);
  349. /* set alarm time */
  350. sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
  351. sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
  352. sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
  353. sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
  354. sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
  355. mon = tm->tm_mon;
  356. if (mon >= 0)
  357. mon += 1;
  358. sh_rtc_write_alarm_value(rtc, mon, RMONAR);
  359. if (wkalrm->enabled) {
  360. rcr1 |= RCR1_AIE;
  361. writeb(rcr1, rtc->regbase + RCR1);
  362. }
  363. spin_unlock_irq(&rtc->lock);
  364. return 0;
  365. }
  366. static const struct rtc_class_ops sh_rtc_ops = {
  367. .read_time = sh_rtc_read_time,
  368. .set_time = sh_rtc_set_time,
  369. .read_alarm = sh_rtc_read_alarm,
  370. .set_alarm = sh_rtc_set_alarm,
  371. .proc = sh_rtc_proc,
  372. .alarm_irq_enable = sh_rtc_alarm_irq_enable,
  373. };
  374. static int __init sh_rtc_probe(struct platform_device *pdev)
  375. {
  376. struct sh_rtc *rtc;
  377. struct resource *res;
  378. char clk_name[6];
  379. int clk_id, ret;
  380. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  381. if (unlikely(!rtc))
  382. return -ENOMEM;
  383. spin_lock_init(&rtc->lock);
  384. /* get periodic/carry/alarm irqs */
  385. ret = platform_get_irq(pdev, 0);
  386. if (unlikely(ret <= 0)) {
  387. dev_err(&pdev->dev, "No IRQ resource\n");
  388. return -ENOENT;
  389. }
  390. rtc->periodic_irq = ret;
  391. rtc->carry_irq = platform_get_irq(pdev, 1);
  392. rtc->alarm_irq = platform_get_irq(pdev, 2);
  393. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  394. if (!res)
  395. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  396. if (unlikely(res == NULL)) {
  397. dev_err(&pdev->dev, "No IO resource\n");
  398. return -ENOENT;
  399. }
  400. rtc->regsize = resource_size(res);
  401. rtc->res = devm_request_mem_region(&pdev->dev, res->start,
  402. rtc->regsize, pdev->name);
  403. if (unlikely(!rtc->res))
  404. return -EBUSY;
  405. rtc->regbase = devm_ioremap(&pdev->dev, rtc->res->start, rtc->regsize);
  406. if (unlikely(!rtc->regbase))
  407. return -EINVAL;
  408. if (!pdev->dev.of_node) {
  409. clk_id = pdev->id;
  410. /* With a single device, the clock id is still "rtc0" */
  411. if (clk_id < 0)
  412. clk_id = 0;
  413. snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
  414. } else
  415. snprintf(clk_name, sizeof(clk_name), "fck");
  416. rtc->clk = devm_clk_get(&pdev->dev, clk_name);
  417. if (IS_ERR(rtc->clk)) {
  418. /*
  419. * No error handling for rtc->clk intentionally, not all
  420. * platforms will have a unique clock for the RTC, and
  421. * the clk API can handle the struct clk pointer being
  422. * NULL.
  423. */
  424. rtc->clk = NULL;
  425. }
  426. rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
  427. if (IS_ERR(rtc->rtc_dev))
  428. return PTR_ERR(rtc->rtc_dev);
  429. clk_enable(rtc->clk);
  430. rtc->capabilities = RTC_DEF_CAPABILITIES;
  431. #ifdef CONFIG_SUPERH
  432. if (dev_get_platdata(&pdev->dev)) {
  433. struct sh_rtc_platform_info *pinfo =
  434. dev_get_platdata(&pdev->dev);
  435. /*
  436. * Some CPUs have special capabilities in addition to the
  437. * default set. Add those in here.
  438. */
  439. rtc->capabilities |= pinfo->capabilities;
  440. }
  441. #endif
  442. if (rtc->carry_irq <= 0) {
  443. /* register shared periodic/carry/alarm irq */
  444. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  445. sh_rtc_shared, 0, "sh-rtc", rtc);
  446. if (unlikely(ret)) {
  447. dev_err(&pdev->dev,
  448. "request IRQ failed with %d, IRQ %d\n", ret,
  449. rtc->periodic_irq);
  450. goto err_unmap;
  451. }
  452. } else {
  453. /* register periodic/carry/alarm irqs */
  454. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  455. sh_rtc_periodic, 0, "sh-rtc period", rtc);
  456. if (unlikely(ret)) {
  457. dev_err(&pdev->dev,
  458. "request period IRQ failed with %d, IRQ %d\n",
  459. ret, rtc->periodic_irq);
  460. goto err_unmap;
  461. }
  462. ret = devm_request_irq(&pdev->dev, rtc->carry_irq,
  463. sh_rtc_interrupt, 0, "sh-rtc carry", rtc);
  464. if (unlikely(ret)) {
  465. dev_err(&pdev->dev,
  466. "request carry IRQ failed with %d, IRQ %d\n",
  467. ret, rtc->carry_irq);
  468. goto err_unmap;
  469. }
  470. ret = devm_request_irq(&pdev->dev, rtc->alarm_irq,
  471. sh_rtc_alarm, 0, "sh-rtc alarm", rtc);
  472. if (unlikely(ret)) {
  473. dev_err(&pdev->dev,
  474. "request alarm IRQ failed with %d, IRQ %d\n",
  475. ret, rtc->alarm_irq);
  476. goto err_unmap;
  477. }
  478. }
  479. platform_set_drvdata(pdev, rtc);
  480. /* everything disabled by default */
  481. sh_rtc_setaie(&pdev->dev, 0);
  482. sh_rtc_setcie(&pdev->dev, 0);
  483. rtc->rtc_dev->ops = &sh_rtc_ops;
  484. rtc->rtc_dev->max_user_freq = 256;
  485. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  486. rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_1900;
  487. rtc->rtc_dev->range_max = RTC_TIMESTAMP_END_9999;
  488. } else {
  489. rtc->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0);
  490. rtc->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59);
  491. }
  492. ret = devm_rtc_register_device(rtc->rtc_dev);
  493. if (ret)
  494. goto err_unmap;
  495. device_init_wakeup(&pdev->dev, 1);
  496. return 0;
  497. err_unmap:
  498. clk_disable(rtc->clk);
  499. return ret;
  500. }
  501. static int __exit sh_rtc_remove(struct platform_device *pdev)
  502. {
  503. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  504. sh_rtc_setaie(&pdev->dev, 0);
  505. sh_rtc_setcie(&pdev->dev, 0);
  506. clk_disable(rtc->clk);
  507. return 0;
  508. }
  509. static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
  510. {
  511. struct sh_rtc *rtc = dev_get_drvdata(dev);
  512. irq_set_irq_wake(rtc->periodic_irq, enabled);
  513. if (rtc->carry_irq > 0) {
  514. irq_set_irq_wake(rtc->carry_irq, enabled);
  515. irq_set_irq_wake(rtc->alarm_irq, enabled);
  516. }
  517. }
  518. static int __maybe_unused sh_rtc_suspend(struct device *dev)
  519. {
  520. if (device_may_wakeup(dev))
  521. sh_rtc_set_irq_wake(dev, 1);
  522. return 0;
  523. }
  524. static int __maybe_unused sh_rtc_resume(struct device *dev)
  525. {
  526. if (device_may_wakeup(dev))
  527. sh_rtc_set_irq_wake(dev, 0);
  528. return 0;
  529. }
  530. static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume);
  531. static const struct of_device_id sh_rtc_of_match[] = {
  532. { .compatible = "renesas,sh-rtc", },
  533. { /* sentinel */ }
  534. };
  535. MODULE_DEVICE_TABLE(of, sh_rtc_of_match);
  536. static struct platform_driver sh_rtc_platform_driver = {
  537. .driver = {
  538. .name = DRV_NAME,
  539. .pm = &sh_rtc_pm_ops,
  540. .of_match_table = sh_rtc_of_match,
  541. },
  542. .remove = __exit_p(sh_rtc_remove),
  543. };
  544. module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
  545. MODULE_DESCRIPTION("SuperH on-chip RTC driver");
  546. MODULE_AUTHOR("Paul Mundt <[email protected]>, "
  547. "Jamie Lenehan <[email protected]>, "
  548. "Angelo Castello <[email protected]>");
  549. MODULE_LICENSE("GPL v2");
  550. MODULE_ALIAS("platform:" DRV_NAME);