qcom_glink_spss.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/io.h>
  7. #include <linux/of.h>
  8. #include <linux/of_address.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/sizes.h>
  12. #include <linux/soc/qcom/smem.h>
  13. #include <linux/rpmsg/qcom_glink.h>
  14. #include "qcom_glink_native.h"
  15. #define FIFO_FULL_RESERVE 8
  16. #define FIFO_ALIGNMENT 8
  17. #define TX_BLOCKED_CMD_RESERVE 8 /* size of struct read_notif_request */
  18. #define SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR 478
  19. #define SPSS_TX_FIFO_SIZE SZ_2K
  20. #define SPSS_RX_FIFO_SIZE SZ_2K
  21. struct glink_spss_cfg {
  22. __le32 tx_tail;
  23. __le32 tx_head;
  24. __le32 tx_fifo_size;
  25. __le32 rx_tail;
  26. __le32 rx_head;
  27. __le32 rx_fifo_size;
  28. };
  29. struct glink_spss_pipe {
  30. struct qcom_glink_pipe native;
  31. __le32 *tail;
  32. __le32 *head;
  33. void *fifo;
  34. int remote_pid;
  35. };
  36. #define to_spss_pipe(p) container_of(p, struct glink_spss_pipe, native)
  37. static void glink_spss_reset(struct qcom_glink_pipe *np)
  38. {
  39. struct glink_spss_pipe *pipe = to_spss_pipe(np);
  40. *pipe->head = cpu_to_le32(0);
  41. *pipe->tail = cpu_to_le32(0);
  42. }
  43. static size_t glink_spss_rx_avail(struct qcom_glink_pipe *np)
  44. {
  45. struct glink_spss_pipe *pipe = to_spss_pipe(np);
  46. u32 head;
  47. u32 tail;
  48. head = le32_to_cpu(*pipe->head);
  49. tail = le32_to_cpu(*pipe->tail);
  50. if (head < tail)
  51. return pipe->native.length - tail + head;
  52. else
  53. return head - tail;
  54. }
  55. static void glink_spss_rx_peak(struct qcom_glink_pipe *np,
  56. void *data, unsigned int offset, size_t count)
  57. {
  58. struct glink_spss_pipe *pipe = to_spss_pipe(np);
  59. size_t len;
  60. u32 tail;
  61. tail = le32_to_cpu(*pipe->tail);
  62. tail += offset;
  63. if (tail >= pipe->native.length)
  64. tail -= pipe->native.length;
  65. len = min_t(size_t, count, pipe->native.length - tail);
  66. if (len)
  67. memcpy_fromio(data, pipe->fifo + tail, len);
  68. if (len != count)
  69. memcpy_fromio(data + len, pipe->fifo, count - len);
  70. }
  71. static void glink_spss_rx_advance(struct qcom_glink_pipe *np,
  72. size_t count)
  73. {
  74. struct glink_spss_pipe *pipe = to_spss_pipe(np);
  75. u32 tail;
  76. tail = le32_to_cpu(*pipe->tail);
  77. tail += count;
  78. if (tail >= pipe->native.length)
  79. tail -= pipe->native.length;
  80. *pipe->tail = cpu_to_le32(tail);
  81. }
  82. static size_t glink_spss_tx_avail(struct qcom_glink_pipe *np)
  83. {
  84. struct glink_spss_pipe *pipe = to_spss_pipe(np);
  85. u32 head;
  86. u32 tail;
  87. u32 avail;
  88. head = le32_to_cpu(*pipe->head);
  89. tail = le32_to_cpu(*pipe->tail);
  90. if (tail <= head)
  91. avail = pipe->native.length - head + tail;
  92. else
  93. avail = tail - head;
  94. if (avail < (FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE))
  95. avail = 0;
  96. else
  97. avail -= FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE;
  98. return avail;
  99. }
  100. static unsigned int glink_spss_tx_write_one(struct glink_spss_pipe *pipe,
  101. unsigned int head,
  102. const void *data, size_t count)
  103. {
  104. size_t len;
  105. len = min_t(size_t, count, pipe->native.length - head);
  106. if (len)
  107. memcpy(pipe->fifo + head, data, len);
  108. if (len != count)
  109. memcpy(pipe->fifo, data + len, count - len);
  110. head += count;
  111. if (head >= pipe->native.length)
  112. head -= pipe->native.length;
  113. return head;
  114. }
  115. static void glink_spss_tx_write(struct qcom_glink_pipe *glink_pipe,
  116. const void *hdr, size_t hlen,
  117. const void *data, size_t dlen)
  118. {
  119. struct glink_spss_pipe *pipe = to_spss_pipe(glink_pipe);
  120. unsigned int head;
  121. head = le32_to_cpu(*pipe->head);
  122. head = glink_spss_tx_write_one(pipe, head, hdr, hlen);
  123. head = glink_spss_tx_write_one(pipe, head, data, dlen);
  124. /* Ensure head is always aligned to 8 bytes */
  125. head = ALIGN(head, 8);
  126. if (head >= pipe->native.length)
  127. head -= pipe->native.length;
  128. /* Ensure ordering of fifo and head update */
  129. wmb();
  130. *pipe->head = cpu_to_le32(head);
  131. }
  132. static void qcom_glink_spss_release(struct device *dev)
  133. {
  134. kfree(dev);
  135. }
  136. static int glink_spss_advertise_cfg(struct device *dev,
  137. u32 size, phys_addr_t addr)
  138. {
  139. struct device_node *np = dev->of_node;
  140. __le64 __iomem *spss_addr;
  141. __le32 __iomem *spss_size;
  142. struct resource addr_r;
  143. struct resource size_r;
  144. int addr_idx;
  145. int size_idx;
  146. addr_idx = of_property_match_string(np, "reg-names", "qcom,spss-addr");
  147. size_idx = of_property_match_string(np, "reg-names", "qcom,spss-size");
  148. if (addr_idx < 0 || size_idx < 0) {
  149. dev_err(dev, "failed to find location registers\n");
  150. return -EINVAL;
  151. }
  152. if (of_address_to_resource(np, addr_idx, &addr_r))
  153. return -ENOMEM;
  154. spss_addr = ioremap(addr_r.start, resource_size(&addr_r));
  155. if (IS_ERR_OR_NULL(spss_addr)) {
  156. dev_err(dev, "failed to map spss addr resource\n");
  157. return -ENOMEM;
  158. }
  159. if (of_address_to_resource(np, size_idx, &size_r)) {
  160. iounmap(spss_addr);
  161. return -ENOMEM;
  162. }
  163. spss_size = ioremap(size_r.start, resource_size(&size_r));
  164. if (IS_ERR_OR_NULL(spss_size)) {
  165. iounmap(spss_addr);
  166. dev_err(dev, "failed to map spss size resource\n");
  167. return -ENOMEM;
  168. }
  169. writeq_relaxed(addr, spss_addr);
  170. writel_relaxed(size, spss_size);
  171. iounmap(spss_addr);
  172. iounmap(spss_size);
  173. return 0;
  174. }
  175. struct qcom_glink *qcom_glink_spss_register(struct device *parent,
  176. struct device_node *node)
  177. {
  178. struct glink_spss_pipe *rx_pipe;
  179. struct glink_spss_pipe *tx_pipe;
  180. struct glink_spss_cfg *cfg;
  181. struct qcom_glink *glink;
  182. struct device *dev;
  183. u32 remote_pid;
  184. size_t tx_size;
  185. size_t rx_size;
  186. size_t size;
  187. int ret;
  188. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  189. if (!dev)
  190. return ERR_PTR(-ENOMEM);
  191. dev->parent = parent;
  192. dev->of_node = node;
  193. dev->release = qcom_glink_spss_release;
  194. dev_set_name(dev, "%s:%s", node->parent->name, node->name);
  195. ret = device_register(dev);
  196. if (ret) {
  197. pr_err("failed to register glink edge %s\n", node->name);
  198. return ERR_PTR(ret);
  199. }
  200. ret = of_property_read_u32(dev->of_node, "qcom,remote-pid",
  201. &remote_pid);
  202. if (ret) {
  203. dev_err(dev, "failed to parse qcom,remote-pid\n");
  204. goto err_put_dev;
  205. }
  206. rx_pipe = devm_kzalloc(dev, sizeof(*rx_pipe), GFP_KERNEL);
  207. tx_pipe = devm_kzalloc(dev, sizeof(*tx_pipe), GFP_KERNEL);
  208. if (!rx_pipe || !tx_pipe) {
  209. ret = -ENOMEM;
  210. goto err_put_dev;
  211. }
  212. tx_size = SPSS_TX_FIFO_SIZE;
  213. rx_size = SPSS_RX_FIFO_SIZE;
  214. size = tx_size + rx_size + sizeof(*cfg);
  215. ret = qcom_smem_alloc(remote_pid,
  216. SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, size);
  217. if (ret && ret != -EEXIST) {
  218. dev_err(dev, "failed to allocate glink descriptors\n");
  219. goto err_put_dev;
  220. }
  221. cfg = qcom_smem_get(remote_pid,
  222. SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, &size);
  223. if (IS_ERR(cfg)) {
  224. dev_err(dev, "failed to acquire xprt descriptor\n");
  225. ret = PTR_ERR(cfg);
  226. goto err_put_dev;
  227. }
  228. if (size != tx_size + rx_size + sizeof(*cfg)) {
  229. dev_err(dev, "glink descriptor of invalid size\n");
  230. ret = -EINVAL;
  231. goto err_put_dev;
  232. }
  233. cfg->tx_fifo_size = cpu_to_le32(tx_size);
  234. cfg->rx_fifo_size = cpu_to_le32(rx_size);
  235. tx_pipe->tail = &cfg->tx_tail;
  236. tx_pipe->head = &cfg->tx_head;
  237. tx_pipe->native.length = tx_size;
  238. tx_pipe->fifo = (u8 *)cfg + sizeof(*cfg);
  239. rx_pipe->tail = &cfg->rx_tail;
  240. rx_pipe->head = &cfg->rx_head;
  241. rx_pipe->native.length = rx_size;
  242. rx_pipe->fifo = (u8 *)cfg + sizeof(*cfg) + tx_size;
  243. rx_pipe->native.avail = glink_spss_rx_avail;
  244. rx_pipe->native.peak = glink_spss_rx_peak;
  245. rx_pipe->native.advance = glink_spss_rx_advance;
  246. rx_pipe->native.reset = glink_spss_reset;
  247. rx_pipe->remote_pid = remote_pid;
  248. tx_pipe->native.avail = glink_spss_tx_avail;
  249. tx_pipe->native.write = glink_spss_tx_write;
  250. tx_pipe->native.reset = glink_spss_reset;
  251. tx_pipe->remote_pid = remote_pid;
  252. *rx_pipe->tail = 0;
  253. *tx_pipe->head = 0;
  254. ret = glink_spss_advertise_cfg(dev, size, qcom_smem_virt_to_phys(cfg));
  255. if (ret)
  256. goto err_put_dev;
  257. glink = qcom_glink_native_probe(dev,
  258. GLINK_FEATURE_INTENT_REUSE,
  259. &rx_pipe->native, &tx_pipe->native,
  260. false);
  261. if (IS_ERR(glink)) {
  262. ret = PTR_ERR(glink);
  263. goto err_put_dev;
  264. }
  265. ret = qcom_glink_native_start(glink);
  266. if (ret)
  267. goto err_put_dev;
  268. return glink;
  269. err_put_dev:
  270. put_device(dev);
  271. return ERR_PTR(ret);
  272. }
  273. EXPORT_SYMBOL(qcom_glink_spss_register);
  274. void qcom_glink_spss_unregister(struct qcom_glink *glink)
  275. {
  276. if (!glink)
  277. return;
  278. qcom_glink_native_remove(glink);
  279. qcom_glink_native_unregister(glink);
  280. }
  281. EXPORT_SYMBOL(qcom_glink_spss_unregister);
  282. MODULE_DESCRIPTION("QTI GLINK SPSS driver");
  283. MODULE_LICENSE("GPL");