reset-npcm.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430
  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2019 Nuvoton Technology corporation.
  3. #include <linux/delay.h>
  4. #include <linux/err.h>
  5. #include <linux/io.h>
  6. #include <linux/init.h>
  7. #include <linux/of.h>
  8. #include <linux/of_device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/reboot.h>
  11. #include <linux/reset-controller.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/regmap.h>
  15. #include <linux/of_address.h>
  16. /* NPCM7xx GCR registers */
  17. #define NPCM_MDLR_OFFSET 0x7C
  18. #define NPCM7XX_MDLR_USBD0 BIT(9)
  19. #define NPCM7XX_MDLR_USBD1 BIT(8)
  20. #define NPCM7XX_MDLR_USBD2_4 BIT(21)
  21. #define NPCM7XX_MDLR_USBD5_9 BIT(22)
  22. /* NPCM8xx MDLR bits */
  23. #define NPCM8XX_MDLR_USBD0_3 BIT(9)
  24. #define NPCM8XX_MDLR_USBD4_7 BIT(22)
  25. #define NPCM8XX_MDLR_USBD8 BIT(24)
  26. #define NPCM8XX_MDLR_USBD9 BIT(21)
  27. #define NPCM_USB1PHYCTL_OFFSET 0x140
  28. #define NPCM_USB2PHYCTL_OFFSET 0x144
  29. #define NPCM_USB3PHYCTL_OFFSET 0x148
  30. #define NPCM_USBXPHYCTL_RS BIT(28)
  31. /* NPCM7xx Reset registers */
  32. #define NPCM_SWRSTR 0x14
  33. #define NPCM_SWRST BIT(2)
  34. #define NPCM_IPSRST1 0x20
  35. #define NPCM_IPSRST1_USBD1 BIT(5)
  36. #define NPCM_IPSRST1_USBD2 BIT(8)
  37. #define NPCM_IPSRST1_USBD3 BIT(25)
  38. #define NPCM_IPSRST1_USBD4 BIT(22)
  39. #define NPCM_IPSRST1_USBD5 BIT(23)
  40. #define NPCM_IPSRST1_USBD6 BIT(24)
  41. #define NPCM_IPSRST2 0x24
  42. #define NPCM_IPSRST2_USB_HOST BIT(26)
  43. #define NPCM_IPSRST3 0x34
  44. #define NPCM_IPSRST3_USBD0 BIT(4)
  45. #define NPCM_IPSRST3_USBD7 BIT(5)
  46. #define NPCM_IPSRST3_USBD8 BIT(6)
  47. #define NPCM_IPSRST3_USBD9 BIT(7)
  48. #define NPCM_IPSRST3_USBPHY1 BIT(24)
  49. #define NPCM_IPSRST3_USBPHY2 BIT(25)
  50. #define NPCM_IPSRST4 0x74
  51. #define NPCM_IPSRST4_USBPHY3 BIT(25)
  52. #define NPCM_IPSRST4_USB_HOST2 BIT(31)
  53. #define NPCM_RC_RESETS_PER_REG 32
  54. #define NPCM_MASK_RESETS GENMASK(4, 0)
  55. enum {
  56. BMC_NPCM7XX = 0,
  57. BMC_NPCM8XX,
  58. };
  59. static const u32 npxm7xx_ipsrst[] = {NPCM_IPSRST1, NPCM_IPSRST2, NPCM_IPSRST3};
  60. static const u32 npxm8xx_ipsrst[] = {NPCM_IPSRST1, NPCM_IPSRST2, NPCM_IPSRST3,
  61. NPCM_IPSRST4};
  62. struct npcm_reset_info {
  63. u32 bmc_id;
  64. u32 num_ipsrst;
  65. const u32 *ipsrst;
  66. };
  67. static const struct npcm_reset_info npxm7xx_reset_info[] = {
  68. {.bmc_id = BMC_NPCM7XX, .num_ipsrst = 3, .ipsrst = npxm7xx_ipsrst}};
  69. static const struct npcm_reset_info npxm8xx_reset_info[] = {
  70. {.bmc_id = BMC_NPCM8XX, .num_ipsrst = 4, .ipsrst = npxm8xx_ipsrst}};
  71. struct npcm_rc_data {
  72. struct reset_controller_dev rcdev;
  73. struct notifier_block restart_nb;
  74. const struct npcm_reset_info *info;
  75. struct regmap *gcr_regmap;
  76. u32 sw_reset_number;
  77. void __iomem *base;
  78. spinlock_t lock;
  79. };
  80. #define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)
  81. static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode,
  82. void *cmd)
  83. {
  84. struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data,
  85. restart_nb);
  86. writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
  87. mdelay(1000);
  88. pr_emerg("%s: unable to restart system\n", __func__);
  89. return NOTIFY_DONE;
  90. }
  91. static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,
  92. unsigned long id, bool set)
  93. {
  94. struct npcm_rc_data *rc = to_rc_data(rcdev);
  95. unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
  96. unsigned int ctrl_offset = id >> 8;
  97. unsigned long flags;
  98. u32 stat;
  99. spin_lock_irqsave(&rc->lock, flags);
  100. stat = readl(rc->base + ctrl_offset);
  101. if (set)
  102. writel(stat | rst_bit, rc->base + ctrl_offset);
  103. else
  104. writel(stat & ~rst_bit, rc->base + ctrl_offset);
  105. spin_unlock_irqrestore(&rc->lock, flags);
  106. return 0;
  107. }
  108. static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id)
  109. {
  110. return npcm_rc_setclear_reset(rcdev, id, true);
  111. }
  112. static int npcm_rc_deassert(struct reset_controller_dev *rcdev,
  113. unsigned long id)
  114. {
  115. return npcm_rc_setclear_reset(rcdev, id, false);
  116. }
  117. static int npcm_rc_status(struct reset_controller_dev *rcdev,
  118. unsigned long id)
  119. {
  120. struct npcm_rc_data *rc = to_rc_data(rcdev);
  121. unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
  122. unsigned int ctrl_offset = id >> 8;
  123. return (readl(rc->base + ctrl_offset) & rst_bit);
  124. }
  125. static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
  126. const struct of_phandle_args *reset_spec)
  127. {
  128. struct npcm_rc_data *rc = to_rc_data(rcdev);
  129. unsigned int offset, bit;
  130. bool offset_found = false;
  131. int off_num;
  132. offset = reset_spec->args[0];
  133. for (off_num = 0 ; off_num < rc->info->num_ipsrst ; off_num++) {
  134. if (offset == rc->info->ipsrst[off_num]) {
  135. offset_found = true;
  136. break;
  137. }
  138. }
  139. if (!offset_found) {
  140. dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset);
  141. return -EINVAL;
  142. }
  143. bit = reset_spec->args[1];
  144. if (bit >= NPCM_RC_RESETS_PER_REG) {
  145. dev_err(rcdev->dev, "Error reset number (%d)\n", bit);
  146. return -EINVAL;
  147. }
  148. return (offset << 8) | bit;
  149. }
  150. static const struct of_device_id npcm_rc_match[] = {
  151. { .compatible = "nuvoton,npcm750-reset", .data = &npxm7xx_reset_info},
  152. { .compatible = "nuvoton,npcm845-reset", .data = &npxm8xx_reset_info},
  153. { }
  154. };
  155. static void npcm_usb_reset_npcm7xx(struct npcm_rc_data *rc)
  156. {
  157. u32 mdlr, iprst1, iprst2, iprst3;
  158. u32 ipsrst1_bits = 0;
  159. u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
  160. u32 ipsrst3_bits = 0;
  161. /* checking which USB device is enabled */
  162. regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
  163. if (!(mdlr & NPCM7XX_MDLR_USBD0))
  164. ipsrst3_bits |= NPCM_IPSRST3_USBD0;
  165. if (!(mdlr & NPCM7XX_MDLR_USBD1))
  166. ipsrst1_bits |= NPCM_IPSRST1_USBD1;
  167. if (!(mdlr & NPCM7XX_MDLR_USBD2_4))
  168. ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
  169. NPCM_IPSRST1_USBD3 |
  170. NPCM_IPSRST1_USBD4);
  171. if (!(mdlr & NPCM7XX_MDLR_USBD0)) {
  172. ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
  173. NPCM_IPSRST1_USBD6);
  174. ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
  175. NPCM_IPSRST3_USBD8 |
  176. NPCM_IPSRST3_USBD9);
  177. }
  178. /* assert reset USB PHY and USB devices */
  179. iprst1 = readl(rc->base + NPCM_IPSRST1);
  180. iprst2 = readl(rc->base + NPCM_IPSRST2);
  181. iprst3 = readl(rc->base + NPCM_IPSRST3);
  182. iprst1 |= ipsrst1_bits;
  183. iprst2 |= ipsrst2_bits;
  184. iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
  185. NPCM_IPSRST3_USBPHY2);
  186. writel(iprst1, rc->base + NPCM_IPSRST1);
  187. writel(iprst2, rc->base + NPCM_IPSRST2);
  188. writel(iprst3, rc->base + NPCM_IPSRST3);
  189. /* clear USB PHY RS bit */
  190. regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
  191. NPCM_USBXPHYCTL_RS, 0);
  192. regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
  193. NPCM_USBXPHYCTL_RS, 0);
  194. /* deassert reset USB PHY */
  195. iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
  196. writel(iprst3, rc->base + NPCM_IPSRST3);
  197. udelay(50);
  198. /* set USB PHY RS bit */
  199. regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
  200. NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
  201. regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
  202. NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
  203. /* deassert reset USB devices*/
  204. iprst1 &= ~ipsrst1_bits;
  205. iprst2 &= ~ipsrst2_bits;
  206. iprst3 &= ~ipsrst3_bits;
  207. writel(iprst1, rc->base + NPCM_IPSRST1);
  208. writel(iprst2, rc->base + NPCM_IPSRST2);
  209. writel(iprst3, rc->base + NPCM_IPSRST3);
  210. }
  211. static void npcm_usb_reset_npcm8xx(struct npcm_rc_data *rc)
  212. {
  213. u32 mdlr, iprst1, iprst2, iprst3, iprst4;
  214. u32 ipsrst1_bits = 0;
  215. u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
  216. u32 ipsrst3_bits = 0;
  217. u32 ipsrst4_bits = NPCM_IPSRST4_USB_HOST2 | NPCM_IPSRST4_USBPHY3;
  218. /* checking which USB device is enabled */
  219. regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
  220. if (!(mdlr & NPCM8XX_MDLR_USBD0_3)) {
  221. ipsrst3_bits |= NPCM_IPSRST3_USBD0;
  222. ipsrst1_bits |= (NPCM_IPSRST1_USBD1 |
  223. NPCM_IPSRST1_USBD2 |
  224. NPCM_IPSRST1_USBD3);
  225. }
  226. if (!(mdlr & NPCM8XX_MDLR_USBD4_7)) {
  227. ipsrst1_bits |= (NPCM_IPSRST1_USBD4 |
  228. NPCM_IPSRST1_USBD5 |
  229. NPCM_IPSRST1_USBD6);
  230. ipsrst3_bits |= NPCM_IPSRST3_USBD7;
  231. }
  232. if (!(mdlr & NPCM8XX_MDLR_USBD8))
  233. ipsrst3_bits |= NPCM_IPSRST3_USBD8;
  234. if (!(mdlr & NPCM8XX_MDLR_USBD9))
  235. ipsrst3_bits |= NPCM_IPSRST3_USBD9;
  236. /* assert reset USB PHY and USB devices */
  237. iprst1 = readl(rc->base + NPCM_IPSRST1);
  238. iprst2 = readl(rc->base + NPCM_IPSRST2);
  239. iprst3 = readl(rc->base + NPCM_IPSRST3);
  240. iprst4 = readl(rc->base + NPCM_IPSRST4);
  241. iprst1 |= ipsrst1_bits;
  242. iprst2 |= ipsrst2_bits;
  243. iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
  244. NPCM_IPSRST3_USBPHY2);
  245. iprst4 |= ipsrst4_bits;
  246. writel(iprst1, rc->base + NPCM_IPSRST1);
  247. writel(iprst2, rc->base + NPCM_IPSRST2);
  248. writel(iprst3, rc->base + NPCM_IPSRST3);
  249. writel(iprst4, rc->base + NPCM_IPSRST4);
  250. /* clear USB PHY RS bit */
  251. regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
  252. NPCM_USBXPHYCTL_RS, 0);
  253. regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
  254. NPCM_USBXPHYCTL_RS, 0);
  255. regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
  256. NPCM_USBXPHYCTL_RS, 0);
  257. /* deassert reset USB PHY */
  258. iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
  259. writel(iprst3, rc->base + NPCM_IPSRST3);
  260. iprst4 &= ~NPCM_IPSRST4_USBPHY3;
  261. writel(iprst4, rc->base + NPCM_IPSRST4);
  262. /* set USB PHY RS bit */
  263. regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
  264. NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
  265. regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
  266. NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
  267. regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
  268. NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
  269. /* deassert reset USB devices*/
  270. iprst1 &= ~ipsrst1_bits;
  271. iprst2 &= ~ipsrst2_bits;
  272. iprst3 &= ~ipsrst3_bits;
  273. iprst4 &= ~ipsrst4_bits;
  274. writel(iprst1, rc->base + NPCM_IPSRST1);
  275. writel(iprst2, rc->base + NPCM_IPSRST2);
  276. writel(iprst3, rc->base + NPCM_IPSRST3);
  277. writel(iprst4, rc->base + NPCM_IPSRST4);
  278. }
  279. /*
  280. * The following procedure should be observed in USB PHY, USB device and
  281. * USB host initialization at BMC boot
  282. */
  283. static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
  284. {
  285. struct device *dev = &pdev->dev;
  286. rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr");
  287. if (IS_ERR(rc->gcr_regmap)) {
  288. dev_warn(&pdev->dev, "Failed to find nuvoton,sysgcr property, please update the device tree\n");
  289. dev_info(&pdev->dev, "Using nuvoton,npcm750-gcr for Poleg backward compatibility\n");
  290. rc->gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
  291. if (IS_ERR(rc->gcr_regmap)) {
  292. dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr");
  293. return PTR_ERR(rc->gcr_regmap);
  294. }
  295. }
  296. rc->info = (const struct npcm_reset_info *)
  297. of_match_device(dev->driver->of_match_table, dev)->data;
  298. switch (rc->info->bmc_id) {
  299. case BMC_NPCM7XX:
  300. npcm_usb_reset_npcm7xx(rc);
  301. break;
  302. case BMC_NPCM8XX:
  303. npcm_usb_reset_npcm8xx(rc);
  304. break;
  305. default:
  306. return -ENODEV;
  307. }
  308. return 0;
  309. }
  310. static const struct reset_control_ops npcm_rc_ops = {
  311. .assert = npcm_rc_assert,
  312. .deassert = npcm_rc_deassert,
  313. .status = npcm_rc_status,
  314. };
  315. static int npcm_rc_probe(struct platform_device *pdev)
  316. {
  317. struct npcm_rc_data *rc;
  318. int ret;
  319. rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
  320. if (!rc)
  321. return -ENOMEM;
  322. rc->base = devm_platform_ioremap_resource(pdev, 0);
  323. if (IS_ERR(rc->base))
  324. return PTR_ERR(rc->base);
  325. spin_lock_init(&rc->lock);
  326. rc->rcdev.owner = THIS_MODULE;
  327. rc->rcdev.ops = &npcm_rc_ops;
  328. rc->rcdev.of_node = pdev->dev.of_node;
  329. rc->rcdev.of_reset_n_cells = 2;
  330. rc->rcdev.of_xlate = npcm_reset_xlate;
  331. platform_set_drvdata(pdev, rc);
  332. ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
  333. if (ret) {
  334. dev_err(&pdev->dev, "unable to register device\n");
  335. return ret;
  336. }
  337. if (npcm_usb_reset(pdev, rc))
  338. dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n");
  339. if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number",
  340. &rc->sw_reset_number)) {
  341. if (rc->sw_reset_number && rc->sw_reset_number < 5) {
  342. rc->restart_nb.priority = 192,
  343. rc->restart_nb.notifier_call = npcm_rc_restart,
  344. ret = register_restart_handler(&rc->restart_nb);
  345. if (ret)
  346. dev_warn(&pdev->dev, "failed to register restart handler\n");
  347. }
  348. }
  349. return ret;
  350. }
  351. static struct platform_driver npcm_rc_driver = {
  352. .probe = npcm_rc_probe,
  353. .driver = {
  354. .name = "npcm-reset",
  355. .of_match_table = npcm_rc_match,
  356. .suppress_bind_attrs = true,
  357. },
  358. };
  359. builtin_platform_driver(npcm_rc_driver);