mt6358-regulator.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2019 MediaTek Inc.
  4. #include <linux/mfd/mt6358/registers.h>
  5. #include <linux/mfd/mt6397/core.h>
  6. #include <linux/module.h>
  7. #include <linux/of.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/regmap.h>
  10. #include <linux/regulator/driver.h>
  11. #include <linux/regulator/machine.h>
  12. #include <linux/regulator/mt6358-regulator.h>
  13. #include <linux/regulator/of_regulator.h>
  14. #define MT6358_BUCK_MODE_AUTO 0
  15. #define MT6358_BUCK_MODE_FORCE_PWM 1
  16. /*
  17. * MT6358 regulators' information
  18. *
  19. * @desc: standard fields of regulator description.
  20. * @qi: Mask for query enable signal status of regulators
  21. */
  22. struct mt6358_regulator_info {
  23. struct regulator_desc desc;
  24. u32 status_reg;
  25. u32 qi;
  26. const u32 *index_table;
  27. unsigned int n_table;
  28. u32 da_vsel_reg;
  29. u32 da_vsel_mask;
  30. u32 modeset_reg;
  31. u32 modeset_mask;
  32. };
  33. #define MT6358_BUCK(match, vreg, min, max, step, \
  34. vosel_mask, _da_vsel_reg, _da_vsel_mask, \
  35. _modeset_reg, _modeset_shift) \
  36. [MT6358_ID_##vreg] = { \
  37. .desc = { \
  38. .name = #vreg, \
  39. .of_match = of_match_ptr(match), \
  40. .ops = &mt6358_buck_ops, \
  41. .type = REGULATOR_VOLTAGE, \
  42. .id = MT6358_ID_##vreg, \
  43. .owner = THIS_MODULE, \
  44. .n_voltages = ((max) - (min)) / (step) + 1, \
  45. .min_uV = (min), \
  46. .uV_step = (step), \
  47. .vsel_reg = MT6358_BUCK_##vreg##_ELR0, \
  48. .vsel_mask = vosel_mask, \
  49. .enable_reg = MT6358_BUCK_##vreg##_CON0, \
  50. .enable_mask = BIT(0), \
  51. .of_map_mode = mt6358_map_mode, \
  52. }, \
  53. .status_reg = MT6358_BUCK_##vreg##_DBG1, \
  54. .qi = BIT(0), \
  55. .da_vsel_reg = _da_vsel_reg, \
  56. .da_vsel_mask = _da_vsel_mask, \
  57. .modeset_reg = _modeset_reg, \
  58. .modeset_mask = BIT(_modeset_shift), \
  59. }
  60. #define MT6358_LDO(match, vreg, ldo_volt_table, \
  61. ldo_index_table, enreg, enbit, vosel, \
  62. vosel_mask) \
  63. [MT6358_ID_##vreg] = { \
  64. .desc = { \
  65. .name = #vreg, \
  66. .of_match = of_match_ptr(match), \
  67. .ops = &mt6358_volt_table_ops, \
  68. .type = REGULATOR_VOLTAGE, \
  69. .id = MT6358_ID_##vreg, \
  70. .owner = THIS_MODULE, \
  71. .n_voltages = ARRAY_SIZE(ldo_volt_table), \
  72. .volt_table = ldo_volt_table, \
  73. .vsel_reg = vosel, \
  74. .vsel_mask = vosel_mask, \
  75. .enable_reg = enreg, \
  76. .enable_mask = BIT(enbit), \
  77. }, \
  78. .status_reg = MT6358_LDO_##vreg##_CON1, \
  79. .qi = BIT(15), \
  80. .index_table = ldo_index_table, \
  81. .n_table = ARRAY_SIZE(ldo_index_table), \
  82. }
  83. #define MT6358_LDO1(match, vreg, min, max, step, \
  84. _da_vsel_reg, _da_vsel_mask, \
  85. vosel, vosel_mask) \
  86. [MT6358_ID_##vreg] = { \
  87. .desc = { \
  88. .name = #vreg, \
  89. .of_match = of_match_ptr(match), \
  90. .ops = &mt6358_volt_range_ops, \
  91. .type = REGULATOR_VOLTAGE, \
  92. .id = MT6358_ID_##vreg, \
  93. .owner = THIS_MODULE, \
  94. .n_voltages = ((max) - (min)) / (step) + 1, \
  95. .min_uV = (min), \
  96. .uV_step = (step), \
  97. .vsel_reg = vosel, \
  98. .vsel_mask = vosel_mask, \
  99. .enable_reg = MT6358_LDO_##vreg##_CON0, \
  100. .enable_mask = BIT(0), \
  101. }, \
  102. .da_vsel_reg = _da_vsel_reg, \
  103. .da_vsel_mask = _da_vsel_mask, \
  104. .status_reg = MT6358_LDO_##vreg##_DBG1, \
  105. .qi = BIT(0), \
  106. }
  107. #define MT6358_REG_FIXED(match, vreg, \
  108. enreg, enbit, volt) \
  109. [MT6358_ID_##vreg] = { \
  110. .desc = { \
  111. .name = #vreg, \
  112. .of_match = of_match_ptr(match), \
  113. .ops = &mt6358_volt_fixed_ops, \
  114. .type = REGULATOR_VOLTAGE, \
  115. .id = MT6358_ID_##vreg, \
  116. .owner = THIS_MODULE, \
  117. .n_voltages = 1, \
  118. .enable_reg = enreg, \
  119. .enable_mask = BIT(enbit), \
  120. .min_uV = volt, \
  121. }, \
  122. .status_reg = MT6358_LDO_##vreg##_CON1, \
  123. .qi = BIT(15), \
  124. }
  125. #define MT6366_BUCK(match, vreg, min, max, step, \
  126. vosel_mask, _da_vsel_reg, _da_vsel_mask, \
  127. _modeset_reg, _modeset_shift) \
  128. [MT6366_ID_##vreg] = { \
  129. .desc = { \
  130. .name = #vreg, \
  131. .of_match = of_match_ptr(match), \
  132. .ops = &mt6358_buck_ops, \
  133. .type = REGULATOR_VOLTAGE, \
  134. .id = MT6366_ID_##vreg, \
  135. .owner = THIS_MODULE, \
  136. .n_voltages = ((max) - (min)) / (step) + 1, \
  137. .min_uV = (min), \
  138. .uV_step = (step), \
  139. .vsel_reg = MT6358_BUCK_##vreg##_ELR0, \
  140. .vsel_mask = vosel_mask, \
  141. .enable_reg = MT6358_BUCK_##vreg##_CON0, \
  142. .enable_mask = BIT(0), \
  143. .of_map_mode = mt6358_map_mode, \
  144. }, \
  145. .status_reg = MT6358_BUCK_##vreg##_DBG1, \
  146. .qi = BIT(0), \
  147. .da_vsel_reg = _da_vsel_reg, \
  148. .da_vsel_mask = _da_vsel_mask, \
  149. .modeset_reg = _modeset_reg, \
  150. .modeset_mask = BIT(_modeset_shift), \
  151. }
  152. #define MT6366_LDO(match, vreg, ldo_volt_table, \
  153. ldo_index_table, enreg, enbit, vosel, \
  154. vosel_mask) \
  155. [MT6366_ID_##vreg] = { \
  156. .desc = { \
  157. .name = #vreg, \
  158. .of_match = of_match_ptr(match), \
  159. .ops = &mt6358_volt_table_ops, \
  160. .type = REGULATOR_VOLTAGE, \
  161. .id = MT6366_ID_##vreg, \
  162. .owner = THIS_MODULE, \
  163. .n_voltages = ARRAY_SIZE(ldo_volt_table), \
  164. .volt_table = ldo_volt_table, \
  165. .vsel_reg = vosel, \
  166. .vsel_mask = vosel_mask, \
  167. .enable_reg = enreg, \
  168. .enable_mask = BIT(enbit), \
  169. }, \
  170. .status_reg = MT6358_LDO_##vreg##_CON1, \
  171. .qi = BIT(15), \
  172. .index_table = ldo_index_table, \
  173. .n_table = ARRAY_SIZE(ldo_index_table), \
  174. }
  175. #define MT6366_LDO1(match, vreg, min, max, step, \
  176. _da_vsel_reg, _da_vsel_mask, \
  177. vosel, vosel_mask) \
  178. [MT6366_ID_##vreg] = { \
  179. .desc = { \
  180. .name = #vreg, \
  181. .of_match = of_match_ptr(match), \
  182. .ops = &mt6358_volt_range_ops, \
  183. .type = REGULATOR_VOLTAGE, \
  184. .id = MT6366_ID_##vreg, \
  185. .owner = THIS_MODULE, \
  186. .n_voltages = ((max) - (min)) / (step) + 1, \
  187. .min_uV = (min), \
  188. .uV_step = (step), \
  189. .vsel_reg = vosel, \
  190. .vsel_mask = vosel_mask, \
  191. .enable_reg = MT6358_LDO_##vreg##_CON0, \
  192. .enable_mask = BIT(0), \
  193. }, \
  194. .da_vsel_reg = _da_vsel_reg, \
  195. .da_vsel_mask = _da_vsel_mask, \
  196. .status_reg = MT6358_LDO_##vreg##_DBG1, \
  197. .qi = BIT(0), \
  198. }
  199. #define MT6366_REG_FIXED(match, vreg, \
  200. enreg, enbit, volt) \
  201. [MT6366_ID_##vreg] = { \
  202. .desc = { \
  203. .name = #vreg, \
  204. .of_match = of_match_ptr(match), \
  205. .ops = &mt6358_volt_fixed_ops, \
  206. .type = REGULATOR_VOLTAGE, \
  207. .id = MT6366_ID_##vreg, \
  208. .owner = THIS_MODULE, \
  209. .n_voltages = 1, \
  210. .enable_reg = enreg, \
  211. .enable_mask = BIT(enbit), \
  212. .min_uV = volt, \
  213. }, \
  214. .status_reg = MT6358_LDO_##vreg##_CON1, \
  215. .qi = BIT(15), \
  216. }
  217. static const unsigned int vdram2_voltages[] = {
  218. 600000, 1800000,
  219. };
  220. static const unsigned int vsim_voltages[] = {
  221. 1700000, 1800000, 2700000, 3000000, 3100000,
  222. };
  223. static const unsigned int vibr_voltages[] = {
  224. 1200000, 1300000, 1500000, 1800000,
  225. 2000000, 2800000, 3000000, 3300000,
  226. };
  227. static const unsigned int vusb_voltages[] = {
  228. 3000000, 3100000,
  229. };
  230. static const unsigned int vcamd_voltages[] = {
  231. 900000, 1000000, 1100000, 1200000,
  232. 1300000, 1500000, 1800000,
  233. };
  234. static const unsigned int vefuse_voltages[] = {
  235. 1700000, 1800000, 1900000,
  236. };
  237. static const unsigned int vmch_vemc_voltages[] = {
  238. 2900000, 3000000, 3300000,
  239. };
  240. static const unsigned int vcama_voltages[] = {
  241. 1800000, 2500000, 2700000,
  242. 2800000, 2900000, 3000000,
  243. };
  244. static const unsigned int vcn33_bt_wifi_voltages[] = {
  245. 3300000, 3400000, 3500000,
  246. };
  247. static const unsigned int vmc_voltages[] = {
  248. 1800000, 2900000, 3000000, 3300000,
  249. };
  250. static const unsigned int vldo28_voltages[] = {
  251. 2800000, 3000000,
  252. };
  253. static const u32 vdram2_idx[] = {
  254. 0, 12,
  255. };
  256. static const u32 vsim_idx[] = {
  257. 3, 4, 8, 11, 12,
  258. };
  259. static const u32 vibr_idx[] = {
  260. 0, 1, 2, 4, 5, 9, 11, 13,
  261. };
  262. static const u32 vusb_idx[] = {
  263. 3, 4,
  264. };
  265. static const u32 vcamd_idx[] = {
  266. 3, 4, 5, 6, 7, 9, 12,
  267. };
  268. static const u32 vefuse_idx[] = {
  269. 11, 12, 13,
  270. };
  271. static const u32 vmch_vemc_idx[] = {
  272. 2, 3, 5,
  273. };
  274. static const u32 vcama_idx[] = {
  275. 0, 7, 9, 10, 11, 12,
  276. };
  277. static const u32 vcn33_bt_wifi_idx[] = {
  278. 1, 2, 3,
  279. };
  280. static const u32 vmc_idx[] = {
  281. 4, 10, 11, 13,
  282. };
  283. static const u32 vldo28_idx[] = {
  284. 1, 3,
  285. };
  286. static unsigned int mt6358_map_mode(unsigned int mode)
  287. {
  288. return mode == MT6358_BUCK_MODE_AUTO ?
  289. REGULATOR_MODE_NORMAL : REGULATOR_MODE_FAST;
  290. }
  291. static int mt6358_set_voltage_sel(struct regulator_dev *rdev,
  292. unsigned int selector)
  293. {
  294. int idx, ret;
  295. const u32 *pvol;
  296. struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
  297. pvol = info->index_table;
  298. idx = pvol[selector];
  299. idx <<= ffs(info->desc.vsel_mask) - 1;
  300. ret = regmap_update_bits(rdev->regmap, info->desc.vsel_reg,
  301. info->desc.vsel_mask, idx);
  302. return ret;
  303. }
  304. static int mt6358_get_voltage_sel(struct regulator_dev *rdev)
  305. {
  306. int idx, ret;
  307. u32 selector;
  308. struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
  309. const u32 *pvol;
  310. ret = regmap_read(rdev->regmap, info->desc.vsel_reg, &selector);
  311. if (ret != 0) {
  312. dev_info(&rdev->dev,
  313. "Failed to get mt6358 %s vsel reg: %d\n",
  314. info->desc.name, ret);
  315. return ret;
  316. }
  317. selector = (selector & info->desc.vsel_mask) >>
  318. (ffs(info->desc.vsel_mask) - 1);
  319. pvol = info->index_table;
  320. for (idx = 0; idx < info->desc.n_voltages; idx++) {
  321. if (pvol[idx] == selector)
  322. return idx;
  323. }
  324. return -EINVAL;
  325. }
  326. static int mt6358_get_buck_voltage_sel(struct regulator_dev *rdev)
  327. {
  328. int ret, regval;
  329. struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
  330. ret = regmap_read(rdev->regmap, info->da_vsel_reg, &regval);
  331. if (ret != 0) {
  332. dev_err(&rdev->dev,
  333. "Failed to get mt6358 Buck %s vsel reg: %d\n",
  334. info->desc.name, ret);
  335. return ret;
  336. }
  337. ret = (regval & info->da_vsel_mask) >> (ffs(info->da_vsel_mask) - 1);
  338. return ret;
  339. }
  340. static int mt6358_get_status(struct regulator_dev *rdev)
  341. {
  342. int ret;
  343. u32 regval;
  344. struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
  345. ret = regmap_read(rdev->regmap, info->status_reg, &regval);
  346. if (ret != 0) {
  347. dev_info(&rdev->dev, "Failed to get enable reg: %d\n", ret);
  348. return ret;
  349. }
  350. return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
  351. }
  352. static int mt6358_regulator_set_mode(struct regulator_dev *rdev,
  353. unsigned int mode)
  354. {
  355. struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
  356. int val;
  357. switch (mode) {
  358. case REGULATOR_MODE_FAST:
  359. val = MT6358_BUCK_MODE_FORCE_PWM;
  360. break;
  361. case REGULATOR_MODE_NORMAL:
  362. val = MT6358_BUCK_MODE_AUTO;
  363. break;
  364. default:
  365. return -EINVAL;
  366. }
  367. dev_dbg(&rdev->dev, "mt6358 buck set_mode %#x, %#x, %#x\n",
  368. info->modeset_reg, info->modeset_mask, val);
  369. val <<= ffs(info->modeset_mask) - 1;
  370. return regmap_update_bits(rdev->regmap, info->modeset_reg,
  371. info->modeset_mask, val);
  372. }
  373. static unsigned int mt6358_regulator_get_mode(struct regulator_dev *rdev)
  374. {
  375. struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
  376. int ret, regval;
  377. ret = regmap_read(rdev->regmap, info->modeset_reg, &regval);
  378. if (ret != 0) {
  379. dev_err(&rdev->dev,
  380. "Failed to get mt6358 buck mode: %d\n", ret);
  381. return ret;
  382. }
  383. switch ((regval & info->modeset_mask) >> (ffs(info->modeset_mask) - 1)) {
  384. case MT6358_BUCK_MODE_AUTO:
  385. return REGULATOR_MODE_NORMAL;
  386. case MT6358_BUCK_MODE_FORCE_PWM:
  387. return REGULATOR_MODE_FAST;
  388. default:
  389. return -EINVAL;
  390. }
  391. }
  392. static const struct regulator_ops mt6358_buck_ops = {
  393. .list_voltage = regulator_list_voltage_linear,
  394. .map_voltage = regulator_map_voltage_linear,
  395. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  396. .get_voltage_sel = mt6358_get_buck_voltage_sel,
  397. .set_voltage_time_sel = regulator_set_voltage_time_sel,
  398. .enable = regulator_enable_regmap,
  399. .disable = regulator_disable_regmap,
  400. .is_enabled = regulator_is_enabled_regmap,
  401. .get_status = mt6358_get_status,
  402. .set_mode = mt6358_regulator_set_mode,
  403. .get_mode = mt6358_regulator_get_mode,
  404. };
  405. static const struct regulator_ops mt6358_volt_range_ops = {
  406. .list_voltage = regulator_list_voltage_linear,
  407. .map_voltage = regulator_map_voltage_linear,
  408. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  409. .get_voltage_sel = mt6358_get_buck_voltage_sel,
  410. .set_voltage_time_sel = regulator_set_voltage_time_sel,
  411. .enable = regulator_enable_regmap,
  412. .disable = regulator_disable_regmap,
  413. .is_enabled = regulator_is_enabled_regmap,
  414. .get_status = mt6358_get_status,
  415. };
  416. static const struct regulator_ops mt6358_volt_table_ops = {
  417. .list_voltage = regulator_list_voltage_table,
  418. .map_voltage = regulator_map_voltage_iterate,
  419. .set_voltage_sel = mt6358_set_voltage_sel,
  420. .get_voltage_sel = mt6358_get_voltage_sel,
  421. .set_voltage_time_sel = regulator_set_voltage_time_sel,
  422. .enable = regulator_enable_regmap,
  423. .disable = regulator_disable_regmap,
  424. .is_enabled = regulator_is_enabled_regmap,
  425. .get_status = mt6358_get_status,
  426. };
  427. static const struct regulator_ops mt6358_volt_fixed_ops = {
  428. .list_voltage = regulator_list_voltage_linear,
  429. .enable = regulator_enable_regmap,
  430. .disable = regulator_disable_regmap,
  431. .is_enabled = regulator_is_enabled_regmap,
  432. .get_status = mt6358_get_status,
  433. };
  434. /* The array is indexed by id(MT6358_ID_XXX) */
  435. static struct mt6358_regulator_info mt6358_regulators[] = {
  436. MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
  437. 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, MT6358_VDRAM1_ANA_CON0, 8),
  438. MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
  439. 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 1),
  440. MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
  441. 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, MT6358_VPA_ANA_CON0, 3),
  442. MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
  443. 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 1),
  444. MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
  445. 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 2),
  446. MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
  447. 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 2),
  448. MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
  449. 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, MT6358_VS2_ANA_CON0, 8),
  450. MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
  451. 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8),
  452. MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
  453. 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8),
  454. MT6358_REG_FIXED("ldo_vrf12", VRF12,
  455. MT6358_LDO_VRF12_CON0, 0, 1200000),
  456. MT6358_REG_FIXED("ldo_vio18", VIO18,
  457. MT6358_LDO_VIO18_CON0, 0, 1800000),
  458. MT6358_REG_FIXED("ldo_vcamio", VCAMIO,
  459. MT6358_LDO_VCAMIO_CON0, 0, 1800000),
  460. MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
  461. MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
  462. MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
  463. MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
  464. MT6358_REG_FIXED("ldo_vaux18", VAUX18,
  465. MT6358_LDO_VAUX18_CON0, 0, 1800000),
  466. MT6358_REG_FIXED("ldo_vbif28", VBIF28,
  467. MT6358_LDO_VBIF28_CON0, 0, 2800000),
  468. MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
  469. MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
  470. MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
  471. MT6358_REG_FIXED("ldo_vaud28", VAUD28,
  472. MT6358_LDO_VAUD28_CON0, 0, 2800000),
  473. MT6358_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx,
  474. MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf),
  475. MT6358_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx,
  476. MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
  477. MT6358_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx,
  478. MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
  479. MT6358_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx,
  480. MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
  481. MT6358_LDO("ldo_vcamd", VCAMD, vcamd_voltages, vcamd_idx,
  482. MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00),
  483. MT6358_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx,
  484. MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
  485. MT6358_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx,
  486. MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
  487. MT6358_LDO("ldo_vcama1", VCAMA1, vcama_voltages, vcama_idx,
  488. MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00),
  489. MT6358_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx,
  490. MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
  491. MT6358_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages,
  492. vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0,
  493. 0, MT6358_VCN33_ANA_CON0, 0x300),
  494. MT6358_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages,
  495. vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1,
  496. 0, MT6358_VCN33_ANA_CON0, 0x300),
  497. MT6358_LDO("ldo_vcama2", VCAMA2, vcama_voltages, vcama_idx,
  498. MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00),
  499. MT6358_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx,
  500. MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
  501. MT6358_LDO("ldo_vldo28", VLDO28, vldo28_voltages, vldo28_idx,
  502. MT6358_LDO_VLDO28_CON0_0, 0,
  503. MT6358_VLDO28_ANA_CON0, 0x300),
  504. MT6358_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx,
  505. MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
  506. MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
  507. MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f),
  508. MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
  509. MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f),
  510. MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
  511. MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f),
  512. MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
  513. MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f),
  514. };
  515. /* The array is indexed by id(MT6366_ID_XXX) */
  516. static struct mt6358_regulator_info mt6366_regulators[] = {
  517. MT6366_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
  518. 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, MT6358_VDRAM1_ANA_CON0, 8),
  519. MT6366_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
  520. 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 1),
  521. MT6366_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
  522. 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, MT6358_VPA_ANA_CON0, 3),
  523. MT6366_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
  524. 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 1),
  525. MT6366_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
  526. 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 2),
  527. MT6366_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
  528. 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 2),
  529. MT6366_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
  530. 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, MT6358_VS2_ANA_CON0, 8),
  531. MT6366_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
  532. 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8),
  533. MT6366_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
  534. 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8),
  535. MT6366_REG_FIXED("ldo_vrf12", VRF12,
  536. MT6358_LDO_VRF12_CON0, 0, 1200000),
  537. MT6366_REG_FIXED("ldo_vio18", VIO18,
  538. MT6358_LDO_VIO18_CON0, 0, 1800000),
  539. MT6366_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
  540. MT6366_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
  541. MT6366_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
  542. MT6366_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
  543. MT6366_REG_FIXED("ldo_vaux18", VAUX18,
  544. MT6358_LDO_VAUX18_CON0, 0, 1800000),
  545. MT6366_REG_FIXED("ldo_vbif28", VBIF28,
  546. MT6358_LDO_VBIF28_CON0, 0, 2800000),
  547. MT6366_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
  548. MT6366_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
  549. MT6366_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
  550. MT6366_REG_FIXED("ldo_vaud28", VAUD28,
  551. MT6358_LDO_VAUD28_CON0, 0, 2800000),
  552. MT6366_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx,
  553. MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10),
  554. MT6366_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx,
  555. MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
  556. MT6366_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx,
  557. MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
  558. MT6366_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx,
  559. MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
  560. MT6366_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx,
  561. MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
  562. MT6366_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx,
  563. MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
  564. MT6366_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx,
  565. MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
  566. MT6366_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages,
  567. vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0,
  568. 0, MT6358_VCN33_ANA_CON0, 0x300),
  569. MT6366_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages,
  570. vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1,
  571. 0, MT6358_VCN33_ANA_CON0, 0x300),
  572. MT6366_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx,
  573. MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
  574. MT6366_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx,
  575. MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
  576. MT6366_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
  577. MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f),
  578. MT6366_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
  579. MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f),
  580. MT6366_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
  581. MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f),
  582. MT6366_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
  583. MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f),
  584. };
  585. static int mt6358_regulator_probe(struct platform_device *pdev)
  586. {
  587. struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
  588. struct regulator_config config = {};
  589. struct regulator_dev *rdev;
  590. struct mt6358_regulator_info *mt6358_info;
  591. int i, max_regulator;
  592. switch (mt6397->chip_id) {
  593. case MT6358_CHIP_ID:
  594. max_regulator = MT6358_MAX_REGULATOR;
  595. mt6358_info = mt6358_regulators;
  596. break;
  597. case MT6366_CHIP_ID:
  598. max_regulator = MT6366_MAX_REGULATOR;
  599. mt6358_info = mt6366_regulators;
  600. break;
  601. default:
  602. dev_err(&pdev->dev, "unsupported chip ID: %d\n", mt6397->chip_id);
  603. return -EINVAL;
  604. }
  605. for (i = 0; i < max_regulator; i++) {
  606. config.dev = &pdev->dev;
  607. config.driver_data = &mt6358_info[i];
  608. config.regmap = mt6397->regmap;
  609. rdev = devm_regulator_register(&pdev->dev,
  610. &mt6358_info[i].desc,
  611. &config);
  612. if (IS_ERR(rdev)) {
  613. dev_err(&pdev->dev, "failed to register %s\n",
  614. mt6358_info[i].desc.name);
  615. return PTR_ERR(rdev);
  616. }
  617. }
  618. return 0;
  619. }
  620. static const struct platform_device_id mt6358_platform_ids[] = {
  621. {"mt6358-regulator", 0},
  622. { /* sentinel */ },
  623. };
  624. MODULE_DEVICE_TABLE(platform, mt6358_platform_ids);
  625. static struct platform_driver mt6358_regulator_driver = {
  626. .driver = {
  627. .name = "mt6358-regulator",
  628. },
  629. .probe = mt6358_regulator_probe,
  630. .id_table = mt6358_platform_ids,
  631. };
  632. module_platform_driver(mt6358_regulator_driver);
  633. MODULE_AUTHOR("Hsin-Hsiung Wang <[email protected]>");
  634. MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6358 PMIC");
  635. MODULE_LICENSE("GPL");