ptp_idt82p33.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * PTP hardware clock driver for the IDT 82P33XXX family of clocks.
  4. *
  5. * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
  6. */
  7. #ifndef PTP_IDT82P33_H
  8. #define PTP_IDT82P33_H
  9. #include <linux/ktime.h>
  10. #include <linux/mfd/idt82p33_reg.h>
  11. #include <linux/regmap.h>
  12. #define FW_FILENAME "idt82p33xxx.bin"
  13. #define MAX_PHC_PLL (2)
  14. #define TOD_BYTE_COUNT (10)
  15. #define DCO_MAX_PPB (92000)
  16. #define MAX_MEASURMENT_COUNT (5)
  17. #define SNAP_THRESHOLD_NS (10000)
  18. #define IMMEDIATE_SNAP_THRESHOLD_NS (50000)
  19. #define DDCO_THRESHOLD_NS (5)
  20. #define IDT82P33_MAX_WRITE_COUNT (512)
  21. #define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef)
  22. #define PLLMASK_ADDR_HI 0xFF
  23. #define PLLMASK_ADDR_LO 0xA5
  24. #define PLL0_OUTMASK_ADDR_HI 0xFF
  25. #define PLL0_OUTMASK_ADDR_LO 0xB0
  26. #define PLL1_OUTMASK_ADDR_HI 0xFF
  27. #define PLL1_OUTMASK_ADDR_LO 0xB2
  28. #define PLL2_OUTMASK_ADDR_HI 0xFF
  29. #define PLL2_OUTMASK_ADDR_LO 0xB4
  30. #define PLL3_OUTMASK_ADDR_HI 0xFF
  31. #define PLL3_OUTMASK_ADDR_LO 0xB6
  32. #define DEFAULT_PLL_MASK (0x01)
  33. #define DEFAULT_OUTPUT_MASK_PLL0 (0xc0)
  34. #define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0
  35. /**
  36. * @brief Maximum absolute value for write phase offset in femtoseconds
  37. */
  38. #define WRITE_PHASE_OFFSET_LIMIT (20000052084ll)
  39. /** @brief Phase offset resolution
  40. *
  41. * DPLL phase offset = 10^15 fs / ( System Clock * 2^13)
  42. * = 10^15 fs / ( 1638400000 * 2^23)
  43. * = 74.5058059692382 fs
  44. */
  45. #define IDT_T0DPLL_PHASE_RESOL 74506
  46. /* PTP Hardware Clock interface */
  47. struct idt82p33_channel {
  48. struct ptp_clock_info caps;
  49. struct ptp_clock *ptp_clock;
  50. struct idt82p33 *idt82p33;
  51. enum pll_mode pll_mode;
  52. s32 current_freq_ppb;
  53. u8 output_mask;
  54. u16 dpll_tod_cnfg;
  55. u16 dpll_tod_trigger;
  56. u16 dpll_tod_sts;
  57. u16 dpll_mode_cnfg;
  58. u16 dpll_freq_cnfg;
  59. u16 dpll_phase_cnfg;
  60. u16 dpll_sync_cnfg;
  61. u16 dpll_input_mode_cnfg;
  62. };
  63. struct idt82p33 {
  64. struct idt82p33_channel channel[MAX_PHC_PLL];
  65. struct device *dev;
  66. u8 pll_mask;
  67. /* Mutex to protect operations from being interrupted */
  68. struct mutex *lock;
  69. struct regmap *regmap;
  70. struct device *mfd;
  71. /* Overhead calculation for adjtime */
  72. ktime_t start_time;
  73. int calculate_overhead_flag;
  74. s64 tod_write_overhead_ns;
  75. };
  76. /* firmware interface */
  77. struct idt82p33_fwrc {
  78. u8 hiaddr;
  79. u8 loaddr;
  80. u8 value;
  81. u8 reserved;
  82. } __packed;
  83. #endif /* PTP_IDT82P33_H */