intel_rapl_msr.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel Running Average Power Limit (RAPL) Driver via MSR interface
  4. * Copyright (c) 2019, Intel Corporation.
  5. */
  6. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/list.h>
  10. #include <linux/types.h>
  11. #include <linux/device.h>
  12. #include <linux/slab.h>
  13. #include <linux/log2.h>
  14. #include <linux/bitmap.h>
  15. #include <linux/delay.h>
  16. #include <linux/sysfs.h>
  17. #include <linux/cpu.h>
  18. #include <linux/powercap.h>
  19. #include <linux/suspend.h>
  20. #include <linux/intel_rapl.h>
  21. #include <linux/processor.h>
  22. #include <linux/platform_device.h>
  23. #include <asm/cpu_device_id.h>
  24. #include <asm/intel-family.h>
  25. /* Local defines */
  26. #define MSR_PLATFORM_POWER_LIMIT 0x0000065C
  27. #define MSR_VR_CURRENT_CONFIG 0x00000601
  28. /* private data for RAPL MSR Interface */
  29. static struct rapl_if_priv *rapl_msr_priv;
  30. static struct rapl_if_priv rapl_msr_priv_intel = {
  31. .reg_unit = MSR_RAPL_POWER_UNIT,
  32. .regs[RAPL_DOMAIN_PACKAGE] = {
  33. MSR_PKG_POWER_LIMIT, MSR_PKG_ENERGY_STATUS, MSR_PKG_PERF_STATUS, 0, MSR_PKG_POWER_INFO },
  34. .regs[RAPL_DOMAIN_PP0] = {
  35. MSR_PP0_POWER_LIMIT, MSR_PP0_ENERGY_STATUS, 0, MSR_PP0_POLICY, 0 },
  36. .regs[RAPL_DOMAIN_PP1] = {
  37. MSR_PP1_POWER_LIMIT, MSR_PP1_ENERGY_STATUS, 0, MSR_PP1_POLICY, 0 },
  38. .regs[RAPL_DOMAIN_DRAM] = {
  39. MSR_DRAM_POWER_LIMIT, MSR_DRAM_ENERGY_STATUS, MSR_DRAM_PERF_STATUS, 0, MSR_DRAM_POWER_INFO },
  40. .regs[RAPL_DOMAIN_PLATFORM] = {
  41. MSR_PLATFORM_POWER_LIMIT, MSR_PLATFORM_ENERGY_STATUS, 0, 0, 0},
  42. .limits[RAPL_DOMAIN_PACKAGE] = 2,
  43. .limits[RAPL_DOMAIN_PLATFORM] = 2,
  44. };
  45. static struct rapl_if_priv rapl_msr_priv_amd = {
  46. .reg_unit = MSR_AMD_RAPL_POWER_UNIT,
  47. .regs[RAPL_DOMAIN_PACKAGE] = {
  48. 0, MSR_AMD_PKG_ENERGY_STATUS, 0, 0, 0 },
  49. .regs[RAPL_DOMAIN_PP0] = {
  50. 0, MSR_AMD_CORE_ENERGY_STATUS, 0, 0, 0 },
  51. };
  52. /* Handles CPU hotplug on multi-socket systems.
  53. * If a CPU goes online as the first CPU of the physical package
  54. * we add the RAPL package to the system. Similarly, when the last
  55. * CPU of the package is removed, we remove the RAPL package and its
  56. * associated domains. Cooling devices are handled accordingly at
  57. * per-domain level.
  58. */
  59. static int rapl_cpu_online(unsigned int cpu)
  60. {
  61. struct rapl_package *rp;
  62. rp = rapl_find_package_domain(cpu, rapl_msr_priv);
  63. if (!rp) {
  64. rp = rapl_add_package(cpu, rapl_msr_priv);
  65. if (IS_ERR(rp))
  66. return PTR_ERR(rp);
  67. }
  68. cpumask_set_cpu(cpu, &rp->cpumask);
  69. return 0;
  70. }
  71. static int rapl_cpu_down_prep(unsigned int cpu)
  72. {
  73. struct rapl_package *rp;
  74. int lead_cpu;
  75. rp = rapl_find_package_domain(cpu, rapl_msr_priv);
  76. if (!rp)
  77. return 0;
  78. cpumask_clear_cpu(cpu, &rp->cpumask);
  79. lead_cpu = cpumask_first(&rp->cpumask);
  80. if (lead_cpu >= nr_cpu_ids)
  81. rapl_remove_package(rp);
  82. else if (rp->lead_cpu == cpu)
  83. rp->lead_cpu = lead_cpu;
  84. return 0;
  85. }
  86. static int rapl_msr_read_raw(int cpu, struct reg_action *ra)
  87. {
  88. u32 msr = (u32)ra->reg;
  89. if (rdmsrl_safe_on_cpu(cpu, msr, &ra->value)) {
  90. pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
  91. return -EIO;
  92. }
  93. ra->value &= ra->mask;
  94. return 0;
  95. }
  96. static void rapl_msr_update_func(void *info)
  97. {
  98. struct reg_action *ra = info;
  99. u32 msr = (u32)ra->reg;
  100. u64 val;
  101. ra->err = rdmsrl_safe(msr, &val);
  102. if (ra->err)
  103. return;
  104. val &= ~ra->mask;
  105. val |= ra->value;
  106. ra->err = wrmsrl_safe(msr, val);
  107. }
  108. static int rapl_msr_write_raw(int cpu, struct reg_action *ra)
  109. {
  110. int ret;
  111. ret = smp_call_function_single(cpu, rapl_msr_update_func, ra, 1);
  112. if (WARN_ON_ONCE(ret))
  113. return ret;
  114. return ra->err;
  115. }
  116. /* List of verified CPUs. */
  117. static const struct x86_cpu_id pl4_support_ids[] = {
  118. { X86_VENDOR_INTEL, 6, INTEL_FAM6_TIGERLAKE_L, X86_FEATURE_ANY },
  119. { X86_VENDOR_INTEL, 6, INTEL_FAM6_ALDERLAKE, X86_FEATURE_ANY },
  120. { X86_VENDOR_INTEL, 6, INTEL_FAM6_ALDERLAKE_L, X86_FEATURE_ANY },
  121. { X86_VENDOR_INTEL, 6, INTEL_FAM6_ALDERLAKE_N, X86_FEATURE_ANY },
  122. { X86_VENDOR_INTEL, 6, INTEL_FAM6_RAPTORLAKE, X86_FEATURE_ANY },
  123. { X86_VENDOR_INTEL, 6, INTEL_FAM6_RAPTORLAKE_P, X86_FEATURE_ANY },
  124. {}
  125. };
  126. static int rapl_msr_probe(struct platform_device *pdev)
  127. {
  128. const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids);
  129. int ret;
  130. switch (boot_cpu_data.x86_vendor) {
  131. case X86_VENDOR_INTEL:
  132. rapl_msr_priv = &rapl_msr_priv_intel;
  133. break;
  134. case X86_VENDOR_HYGON:
  135. case X86_VENDOR_AMD:
  136. rapl_msr_priv = &rapl_msr_priv_amd;
  137. break;
  138. default:
  139. pr_err("intel-rapl does not support CPU vendor %d\n", boot_cpu_data.x86_vendor);
  140. return -ENODEV;
  141. }
  142. rapl_msr_priv->read_raw = rapl_msr_read_raw;
  143. rapl_msr_priv->write_raw = rapl_msr_write_raw;
  144. if (id) {
  145. rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] = 3;
  146. rapl_msr_priv->regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4] =
  147. MSR_VR_CURRENT_CONFIG;
  148. pr_info("PL4 support detected.\n");
  149. }
  150. rapl_msr_priv->control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
  151. if (IS_ERR(rapl_msr_priv->control_type)) {
  152. pr_debug("failed to register powercap control_type.\n");
  153. return PTR_ERR(rapl_msr_priv->control_type);
  154. }
  155. ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powercap/rapl:online",
  156. rapl_cpu_online, rapl_cpu_down_prep);
  157. if (ret < 0)
  158. goto out;
  159. rapl_msr_priv->pcap_rapl_online = ret;
  160. return 0;
  161. out:
  162. if (ret)
  163. powercap_unregister_control_type(rapl_msr_priv->control_type);
  164. return ret;
  165. }
  166. static int rapl_msr_remove(struct platform_device *pdev)
  167. {
  168. cpuhp_remove_state(rapl_msr_priv->pcap_rapl_online);
  169. powercap_unregister_control_type(rapl_msr_priv->control_type);
  170. return 0;
  171. }
  172. static const struct platform_device_id rapl_msr_ids[] = {
  173. { .name = "intel_rapl_msr", },
  174. {}
  175. };
  176. MODULE_DEVICE_TABLE(platform, rapl_msr_ids);
  177. static struct platform_driver intel_rapl_msr_driver = {
  178. .probe = rapl_msr_probe,
  179. .remove = rapl_msr_remove,
  180. .id_table = rapl_msr_ids,
  181. .driver = {
  182. .name = "intel_rapl_msr",
  183. },
  184. };
  185. module_platform_driver(intel_rapl_msr_driver);
  186. MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit) control via MSR interface");
  187. MODULE_AUTHOR("Zhang Rui <[email protected]>");
  188. MODULE_LICENSE("GPL v2");