pfc-r8a77950.c 186 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A77950 processor support - PFC hardware block.
  4. *
  5. * Copyright (C) 2015-2017 Renesas Electronics Corporation
  6. */
  7. #include <linux/errno.h>
  8. #include <linux/kernel.h>
  9. #include "sh_pfc.h"
  10. #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
  11. #define CPU_ALL_GP(fn, sfx) \
  12. PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
  13. PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
  14. PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
  15. PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  16. PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
  17. PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
  18. PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
  19. PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
  20. PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  21. PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
  22. PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
  23. PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  24. #define CPU_ALL_NOGP(fn) \
  25. PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
  26. PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
  27. PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
  28. PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
  29. PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
  30. PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
  31. PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
  32. PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
  33. PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
  34. PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
  35. PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
  36. PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
  37. PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
  38. PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
  39. PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
  40. PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \
  41. PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
  42. PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
  43. PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
  44. PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
  45. PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
  46. PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
  47. PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
  48. PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
  49. PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
  50. PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
  51. PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
  52. PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
  53. PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
  54. PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
  55. PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
  56. PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
  57. PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
  58. PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
  59. PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
  60. PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
  61. PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
  62. PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
  63. PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
  64. PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
  65. PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
  66. PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
  67. PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
  68. PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
  69. /*
  70. * F_() : just information
  71. * FM() : macro for FN_xxx / xxx_MARK
  72. */
  73. /* GPSR0 */
  74. #define GPSR0_15 F_(D15, IP7_11_8)
  75. #define GPSR0_14 F_(D14, IP7_7_4)
  76. #define GPSR0_13 F_(D13, IP7_3_0)
  77. #define GPSR0_12 F_(D12, IP6_31_28)
  78. #define GPSR0_11 F_(D11, IP6_27_24)
  79. #define GPSR0_10 F_(D10, IP6_23_20)
  80. #define GPSR0_9 F_(D9, IP6_19_16)
  81. #define GPSR0_8 F_(D8, IP6_15_12)
  82. #define GPSR0_7 F_(D7, IP6_11_8)
  83. #define GPSR0_6 F_(D6, IP6_7_4)
  84. #define GPSR0_5 F_(D5, IP6_3_0)
  85. #define GPSR0_4 F_(D4, IP5_31_28)
  86. #define GPSR0_3 F_(D3, IP5_27_24)
  87. #define GPSR0_2 F_(D2, IP5_23_20)
  88. #define GPSR0_1 F_(D1, IP5_19_16)
  89. #define GPSR0_0 F_(D0, IP5_15_12)
  90. /* GPSR1 */
  91. #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
  92. #define GPSR1_26 F_(WE1_N, IP5_7_4)
  93. #define GPSR1_25 F_(WE0_N, IP5_3_0)
  94. #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
  95. #define GPSR1_23 F_(RD_N, IP4_27_24)
  96. #define GPSR1_22 F_(BS_N, IP4_23_20)
  97. #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
  98. #define GPSR1_20 F_(CS0_N, IP4_15_12)
  99. #define GPSR1_19 F_(A19, IP4_11_8)
  100. #define GPSR1_18 F_(A18, IP4_7_4)
  101. #define GPSR1_17 F_(A17, IP4_3_0)
  102. #define GPSR1_16 F_(A16, IP3_31_28)
  103. #define GPSR1_15 F_(A15, IP3_27_24)
  104. #define GPSR1_14 F_(A14, IP3_23_20)
  105. #define GPSR1_13 F_(A13, IP3_19_16)
  106. #define GPSR1_12 F_(A12, IP3_15_12)
  107. #define GPSR1_11 F_(A11, IP3_11_8)
  108. #define GPSR1_10 F_(A10, IP3_7_4)
  109. #define GPSR1_9 F_(A9, IP3_3_0)
  110. #define GPSR1_8 F_(A8, IP2_31_28)
  111. #define GPSR1_7 F_(A7, IP2_27_24)
  112. #define GPSR1_6 F_(A6, IP2_23_20)
  113. #define GPSR1_5 F_(A5, IP2_19_16)
  114. #define GPSR1_4 F_(A4, IP2_15_12)
  115. #define GPSR1_3 F_(A3, IP2_11_8)
  116. #define GPSR1_2 F_(A2, IP2_7_4)
  117. #define GPSR1_1 F_(A1, IP2_3_0)
  118. #define GPSR1_0 F_(A0, IP1_31_28)
  119. /* GPSR2 */
  120. #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
  121. #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
  122. #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
  123. #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
  124. #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
  125. #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
  126. #define GPSR2_8 F_(PWM2_A, IP1_27_24)
  127. #define GPSR2_7 F_(PWM1_A, IP1_23_20)
  128. #define GPSR2_6 F_(PWM0, IP1_19_16)
  129. #define GPSR2_5 F_(IRQ5, IP1_15_12)
  130. #define GPSR2_4 F_(IRQ4, IP1_11_8)
  131. #define GPSR2_3 F_(IRQ3, IP1_7_4)
  132. #define GPSR2_2 F_(IRQ2, IP1_3_0)
  133. #define GPSR2_1 F_(IRQ1, IP0_31_28)
  134. #define GPSR2_0 F_(IRQ0, IP0_27_24)
  135. /* GPSR3 */
  136. #define GPSR3_15 F_(SD1_WP, IP10_23_20)
  137. #define GPSR3_14 F_(SD1_CD, IP10_19_16)
  138. #define GPSR3_13 F_(SD0_WP, IP10_15_12)
  139. #define GPSR3_12 F_(SD0_CD, IP10_11_8)
  140. #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
  141. #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
  142. #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
  143. #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
  144. #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
  145. #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
  146. #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
  147. #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
  148. #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
  149. #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
  150. #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
  151. #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
  152. /* GPSR4 */
  153. #define GPSR4_17 FM(SD3_DS)
  154. #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
  155. #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
  156. #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
  157. #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
  158. #define GPSR4_12 FM(SD3_DAT3)
  159. #define GPSR4_11 FM(SD3_DAT2)
  160. #define GPSR4_10 FM(SD3_DAT1)
  161. #define GPSR4_9 FM(SD3_DAT0)
  162. #define GPSR4_8 FM(SD3_CMD)
  163. #define GPSR4_7 FM(SD3_CLK)
  164. #define GPSR4_6 F_(SD2_DS, IP9_23_20)
  165. #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
  166. #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
  167. #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
  168. #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
  169. #define GPSR4_1 FM(SD2_CMD)
  170. #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
  171. /* GPSR5 */
  172. #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
  173. #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
  174. #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
  175. #define GPSR5_22 FM(MSIOF0_RXD)
  176. #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
  177. #define GPSR5_20 FM(MSIOF0_TXD)
  178. #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
  179. #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
  180. #define GPSR5_17 FM(MSIOF0_SCK)
  181. #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
  182. #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
  183. #define GPSR5_14 F_(HTX0, IP12_19_16)
  184. #define GPSR5_13 F_(HRX0, IP12_15_12)
  185. #define GPSR5_12 F_(HSCK0, IP12_11_8)
  186. #define GPSR5_11 F_(RX2_A, IP12_7_4)
  187. #define GPSR5_10 F_(TX2_A, IP12_3_0)
  188. #define GPSR5_9 F_(SCK2, IP11_31_28)
  189. #define GPSR5_8 F_(RTS1_N, IP11_27_24)
  190. #define GPSR5_7 F_(CTS1_N, IP11_23_20)
  191. #define GPSR5_6 F_(TX1_A, IP11_19_16)
  192. #define GPSR5_5 F_(RX1_A, IP11_15_12)
  193. #define GPSR5_4 F_(RTS0_N, IP11_11_8)
  194. #define GPSR5_3 F_(CTS0_N, IP11_7_4)
  195. #define GPSR5_2 F_(TX0, IP11_3_0)
  196. #define GPSR5_1 F_(RX0, IP10_31_28)
  197. #define GPSR5_0 F_(SCK0, IP10_27_24)
  198. /* GPSR6 */
  199. #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
  200. #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
  201. #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
  202. #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
  203. #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
  204. #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
  205. #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
  206. #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
  207. #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
  208. #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
  209. #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
  210. #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
  211. #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
  212. #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
  213. #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
  214. #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
  215. #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
  216. #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
  217. #define GPSR6_13 FM(SSI_SDATA5)
  218. #define GPSR6_12 FM(SSI_WS5)
  219. #define GPSR6_11 FM(SSI_SCK5)
  220. #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
  221. #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
  222. #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
  223. #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
  224. #define GPSR6_6 F_(SSI_WS349, IP14_15_12)
  225. #define GPSR6_5 F_(SSI_SCK349, IP14_11_8)
  226. #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
  227. #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
  228. #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
  229. #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
  230. #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
  231. /* GPSR7 */
  232. #define GPSR7_3 FM(GP7_03)
  233. #define GPSR7_2 FM(GP7_02)
  234. #define GPSR7_1 FM(AVS2)
  235. #define GPSR7_0 FM(AVS1)
  236. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  237. #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  238. #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  239. #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  240. #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  241. #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  242. #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  243. #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  244. #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  245. #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  246. #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  247. #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  248. #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  249. #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  250. #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  251. #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  252. #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  253. #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  254. #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  255. #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  256. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  257. #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  258. #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  259. #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  260. #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  261. #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  262. #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  263. #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  264. #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  265. #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  266. #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  267. #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  268. #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  269. #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  270. #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  271. #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  272. #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  273. #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  274. #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  275. #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  276. #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  277. #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  278. #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  279. #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  280. #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  281. #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  282. #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  283. #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  284. #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  285. #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  286. #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  287. #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  288. #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  289. #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  290. #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  291. #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  292. #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  293. #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  294. #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  295. #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  296. #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  297. #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  298. #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  299. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  300. #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  301. #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  302. #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  303. #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  304. #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  305. #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  306. #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  307. #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  308. #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  309. #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  310. #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  311. #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  312. #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  313. #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  314. #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  315. #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  316. #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  317. #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  318. #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  319. #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  320. #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  321. #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  322. #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  323. #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  324. #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  325. #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  326. #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  327. #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  328. #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  329. #define IP11_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  330. #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  331. #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  332. #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  333. #define IP11_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  334. #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  335. #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  336. #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  337. #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  338. #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  339. #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  340. #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  341. #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  342. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  343. #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  344. #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  345. #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  346. #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  347. #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  348. #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  349. #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  350. #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  351. #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  352. #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  353. #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  354. #define IP14_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  355. #define IP14_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  356. #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  357. #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  358. #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  359. #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  360. #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  361. #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  362. #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  363. #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  364. #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  365. #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  366. #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  367. #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  368. #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  369. #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  370. #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  371. #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  372. #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  373. #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  374. #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  375. #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  376. #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  377. #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  378. #define PINMUX_GPSR \
  379. \
  380. GPSR6_31 \
  381. GPSR6_30 \
  382. GPSR6_29 \
  383. GPSR6_28 \
  384. GPSR1_27 GPSR6_27 \
  385. GPSR1_26 GPSR6_26 \
  386. GPSR1_25 GPSR5_25 GPSR6_25 \
  387. GPSR1_24 GPSR5_24 GPSR6_24 \
  388. GPSR1_23 GPSR5_23 GPSR6_23 \
  389. GPSR1_22 GPSR5_22 GPSR6_22 \
  390. GPSR1_21 GPSR5_21 GPSR6_21 \
  391. GPSR1_20 GPSR5_20 GPSR6_20 \
  392. GPSR1_19 GPSR5_19 GPSR6_19 \
  393. GPSR1_18 GPSR5_18 GPSR6_18 \
  394. GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
  395. GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
  396. GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
  397. GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
  398. GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
  399. GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
  400. GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
  401. GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
  402. GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
  403. GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
  404. GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
  405. GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
  406. GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
  407. GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
  408. GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
  409. GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
  410. GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
  411. GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
  412. #define PINMUX_IPSR \
  413. \
  414. FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
  415. FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
  416. FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
  417. FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
  418. FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
  419. FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
  420. FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
  421. FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
  422. \
  423. FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
  424. FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
  425. FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
  426. FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
  427. FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
  428. FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
  429. FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
  430. FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
  431. \
  432. FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
  433. FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
  434. FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
  435. FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
  436. FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
  437. FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
  438. FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
  439. FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
  440. \
  441. FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
  442. FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
  443. FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
  444. FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
  445. FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
  446. FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
  447. FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
  448. FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
  449. \
  450. FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
  451. FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
  452. FM(IP16_11_8) IP16_11_8 \
  453. FM(IP16_15_12) IP16_15_12 \
  454. FM(IP16_19_16) IP16_19_16 \
  455. FM(IP16_23_20) IP16_23_20 \
  456. FM(IP16_27_24) IP16_27_24 \
  457. FM(IP16_31_28) IP16_31_28
  458. /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  459. #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
  460. #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
  461. #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
  462. #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
  463. #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
  464. #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
  465. #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
  466. #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
  467. #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
  468. #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
  469. #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
  470. #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
  471. #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
  472. #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
  473. #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
  474. #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
  475. #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
  476. #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
  477. #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
  478. #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
  479. #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
  480. /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  481. #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
  482. #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
  483. #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
  484. #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
  485. #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
  486. #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
  487. #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
  488. #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
  489. #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
  490. #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
  491. #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
  492. #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
  493. #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
  494. #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
  495. #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
  496. #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
  497. #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
  498. #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
  499. #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
  500. #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
  501. #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
  502. #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
  503. /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
  504. #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
  505. #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
  506. #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
  507. #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
  508. #define PINMUX_MOD_SELS\
  509. \
  510. MOD_SEL1_31_30 MOD_SEL2_31 \
  511. MOD_SEL0_30_29 MOD_SEL2_30 \
  512. MOD_SEL1_29_28_27 MOD_SEL2_29 \
  513. MOD_SEL0_28_27 \
  514. \
  515. MOD_SEL0_26_25_24 MOD_SEL1_26 \
  516. MOD_SEL1_25_24 \
  517. \
  518. MOD_SEL0_23 MOD_SEL1_23_22_21 \
  519. MOD_SEL0_22 \
  520. MOD_SEL0_21_20 \
  521. MOD_SEL1_20 \
  522. MOD_SEL0_19 MOD_SEL1_19 \
  523. MOD_SEL0_18 MOD_SEL1_18_17 \
  524. MOD_SEL0_17 \
  525. MOD_SEL0_16_15 MOD_SEL1_16 \
  526. MOD_SEL1_15_14 \
  527. MOD_SEL0_14 \
  528. MOD_SEL0_13 MOD_SEL1_13 \
  529. MOD_SEL0_12 MOD_SEL1_12 \
  530. MOD_SEL0_11 MOD_SEL1_11 \
  531. MOD_SEL0_10 MOD_SEL1_10 \
  532. MOD_SEL0_9 MOD_SEL1_9 \
  533. MOD_SEL0_8 \
  534. MOD_SEL0_7_6 \
  535. MOD_SEL1_6 \
  536. MOD_SEL0_5_4 MOD_SEL1_5 \
  537. MOD_SEL1_4 \
  538. MOD_SEL0_3 MOD_SEL1_3 \
  539. MOD_SEL0_2_1 MOD_SEL1_2 \
  540. MOD_SEL1_1 \
  541. MOD_SEL1_0 MOD_SEL2_0
  542. /*
  543. * These pins are not able to be muxed but have other properties
  544. * that can be set, such as drive-strength or pull-up/pull-down enable.
  545. */
  546. #define PINMUX_STATIC \
  547. FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
  548. FM(QSPI0_IO2) FM(QSPI0_IO3) \
  549. FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
  550. FM(QSPI1_IO2) FM(QSPI1_IO3) \
  551. FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
  552. FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
  553. FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
  554. FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
  555. FM(CLKOUT) FM(PRESETOUT) \
  556. FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
  557. FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
  558. #define PINMUX_PHYS \
  559. FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
  560. enum {
  561. PINMUX_RESERVED = 0,
  562. PINMUX_DATA_BEGIN,
  563. GP_ALL(DATA),
  564. PINMUX_DATA_END,
  565. #define F_(x, y)
  566. #define FM(x) FN_##x,
  567. PINMUX_FUNCTION_BEGIN,
  568. GP_ALL(FN),
  569. PINMUX_GPSR
  570. PINMUX_IPSR
  571. PINMUX_MOD_SELS
  572. PINMUX_FUNCTION_END,
  573. #undef F_
  574. #undef FM
  575. #define F_(x, y)
  576. #define FM(x) x##_MARK,
  577. PINMUX_MARK_BEGIN,
  578. PINMUX_GPSR
  579. PINMUX_IPSR
  580. PINMUX_MOD_SELS
  581. PINMUX_STATIC
  582. PINMUX_PHYS
  583. PINMUX_MARK_END,
  584. #undef F_
  585. #undef FM
  586. };
  587. static const u16 pinmux_data[] = {
  588. PINMUX_DATA_GP_ALL(),
  589. PINMUX_SINGLE(AVS1),
  590. PINMUX_SINGLE(AVS2),
  591. PINMUX_SINGLE(GP7_02),
  592. PINMUX_SINGLE(GP7_03),
  593. PINMUX_SINGLE(MSIOF0_RXD),
  594. PINMUX_SINGLE(MSIOF0_SCK),
  595. PINMUX_SINGLE(MSIOF0_TXD),
  596. PINMUX_SINGLE(SD2_CMD),
  597. PINMUX_SINGLE(SD3_CLK),
  598. PINMUX_SINGLE(SD3_CMD),
  599. PINMUX_SINGLE(SD3_DAT0),
  600. PINMUX_SINGLE(SD3_DAT1),
  601. PINMUX_SINGLE(SD3_DAT2),
  602. PINMUX_SINGLE(SD3_DAT3),
  603. PINMUX_SINGLE(SD3_DS),
  604. PINMUX_SINGLE(SSI_SCK5),
  605. PINMUX_SINGLE(SSI_SDATA5),
  606. PINMUX_SINGLE(SSI_WS5),
  607. /* IPSR0 */
  608. PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
  609. PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
  610. PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
  611. PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
  612. PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
  613. PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
  614. PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
  615. PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
  616. PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
  617. PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
  618. PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
  619. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
  620. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
  621. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
  622. PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
  623. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
  624. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
  625. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
  626. PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
  627. PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
  628. PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
  629. PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
  630. PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
  631. PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
  632. PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
  633. PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
  634. PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
  635. PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
  636. PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
  637. PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
  638. PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
  639. /* IPSR1 */
  640. PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
  641. PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
  642. PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
  643. PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
  644. PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
  645. PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
  646. PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
  647. PINMUX_IPSR_GPSR(IP1_7_4, A25),
  648. PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
  649. PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
  650. PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
  651. PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
  652. PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
  653. PINMUX_IPSR_GPSR(IP1_11_8, A24),
  654. PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
  655. PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
  656. PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
  657. PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
  658. PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
  659. PINMUX_IPSR_GPSR(IP1_15_12, A23),
  660. PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
  661. PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
  662. PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
  663. PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
  664. PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
  665. PINMUX_IPSR_GPSR(IP1_19_16, A22),
  666. PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
  667. PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
  668. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
  669. PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0),
  670. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
  671. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
  672. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
  673. PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
  674. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
  675. PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0),
  676. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
  677. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
  678. PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
  679. PINMUX_IPSR_GPSR(IP1_31_28, A0),
  680. PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
  681. PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
  682. PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
  683. PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
  684. PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
  685. /* IPSR2 */
  686. PINMUX_IPSR_GPSR(IP2_3_0, A1),
  687. PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
  688. PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
  689. PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
  690. PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
  691. PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
  692. PINMUX_IPSR_GPSR(IP2_7_4, A2),
  693. PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
  694. PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
  695. PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
  696. PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
  697. PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
  698. PINMUX_IPSR_GPSR(IP2_11_8, A3),
  699. PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
  700. PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
  701. PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
  702. PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
  703. PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
  704. PINMUX_IPSR_GPSR(IP2_15_12, A4),
  705. PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
  706. PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
  707. PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
  708. PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
  709. PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
  710. PINMUX_IPSR_GPSR(IP2_19_16, A5),
  711. PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
  712. PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
  713. PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
  714. PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
  715. PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
  716. PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
  717. PINMUX_IPSR_GPSR(IP2_23_20, A6),
  718. PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
  719. PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
  720. PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
  721. PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
  722. PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
  723. PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
  724. PINMUX_IPSR_GPSR(IP2_27_24, A7),
  725. PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
  726. PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
  727. PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
  728. PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
  729. PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
  730. PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
  731. PINMUX_IPSR_GPSR(IP2_31_28, A8),
  732. PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
  733. PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
  734. PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
  735. PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
  736. PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
  737. PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
  738. /* IPSR3 */
  739. PINMUX_IPSR_GPSR(IP3_3_0, A9),
  740. PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
  741. PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
  742. PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
  743. PINMUX_IPSR_GPSR(IP3_7_4, A10),
  744. PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
  745. PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
  746. PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
  747. PINMUX_IPSR_GPSR(IP3_11_8, A11),
  748. PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
  749. PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
  750. PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
  751. PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
  752. PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
  753. PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
  754. PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
  755. PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
  756. PINMUX_IPSR_GPSR(IP3_15_12, A12),
  757. PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
  758. PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
  759. PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
  760. PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
  761. PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
  762. PINMUX_IPSR_GPSR(IP3_19_16, A13),
  763. PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
  764. PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
  765. PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
  766. PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
  767. PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
  768. PINMUX_IPSR_GPSR(IP3_23_20, A14),
  769. PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
  770. PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
  771. PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
  772. PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
  773. PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
  774. PINMUX_IPSR_GPSR(IP3_27_24, A15),
  775. PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
  776. PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
  777. PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
  778. PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
  779. PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
  780. PINMUX_IPSR_GPSR(IP3_31_28, A16),
  781. PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
  782. PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
  783. PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
  784. /* IPSR4 */
  785. PINMUX_IPSR_GPSR(IP4_3_0, A17),
  786. PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
  787. PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
  788. PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
  789. PINMUX_IPSR_GPSR(IP4_7_4, A18),
  790. PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
  791. PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
  792. PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
  793. PINMUX_IPSR_GPSR(IP4_11_8, A19),
  794. PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
  795. PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
  796. PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
  797. PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
  798. PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
  799. PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
  800. PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
  801. PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
  802. PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
  803. PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
  804. PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
  805. PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
  806. PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
  807. PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
  808. PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
  809. PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
  810. PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
  811. PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
  812. PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
  813. PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
  814. PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
  815. PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
  816. PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
  817. PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
  818. PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
  819. PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
  820. PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
  821. PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
  822. /* IPSR5 */
  823. PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
  824. PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
  825. PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
  826. PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
  827. PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
  828. PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
  829. PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
  830. PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
  831. PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
  832. PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
  833. PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
  834. PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
  835. PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
  836. PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
  837. PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
  838. PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
  839. PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
  840. PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
  841. PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
  842. PINMUX_IPSR_GPSR(IP5_15_12, D0),
  843. PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
  844. PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
  845. PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
  846. PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
  847. PINMUX_IPSR_GPSR(IP5_19_16, D1),
  848. PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
  849. PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
  850. PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
  851. PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
  852. PINMUX_IPSR_GPSR(IP5_23_20, D2),
  853. PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
  854. PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
  855. PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
  856. PINMUX_IPSR_GPSR(IP5_27_24, D3),
  857. PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
  858. PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
  859. PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
  860. PINMUX_IPSR_GPSR(IP5_31_28, D4),
  861. PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
  862. PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
  863. PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
  864. /* IPSR6 */
  865. PINMUX_IPSR_GPSR(IP6_3_0, D5),
  866. PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
  867. PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
  868. PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
  869. PINMUX_IPSR_GPSR(IP6_7_4, D6),
  870. PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
  871. PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
  872. PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
  873. PINMUX_IPSR_GPSR(IP6_11_8, D7),
  874. PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
  875. PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
  876. PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
  877. PINMUX_IPSR_GPSR(IP6_15_12, D8),
  878. PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
  879. PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
  880. PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
  881. PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
  882. PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
  883. PINMUX_IPSR_GPSR(IP6_19_16, D9),
  884. PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
  885. PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
  886. PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
  887. PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
  888. PINMUX_IPSR_GPSR(IP6_23_20, D10),
  889. PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
  890. PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
  891. PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
  892. PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
  893. PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
  894. PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
  895. PINMUX_IPSR_GPSR(IP6_27_24, D11),
  896. PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
  897. PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
  898. PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
  899. PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
  900. PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
  901. PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
  902. PINMUX_IPSR_GPSR(IP6_31_28, D12),
  903. PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
  904. PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
  905. PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
  906. PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
  907. PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
  908. /* IPSR7 */
  909. PINMUX_IPSR_GPSR(IP7_3_0, D13),
  910. PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
  911. PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
  912. PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
  913. PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
  914. PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
  915. PINMUX_IPSR_GPSR(IP7_7_4, D14),
  916. PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
  917. PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
  918. PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
  919. PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
  920. PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
  921. PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
  922. PINMUX_IPSR_GPSR(IP7_11_8, D15),
  923. PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
  924. PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
  925. PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
  926. PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
  927. PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
  928. PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
  929. PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
  930. PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
  931. PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
  932. PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
  933. PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
  934. PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
  935. PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
  936. PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
  937. PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
  938. PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
  939. PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
  940. PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
  941. PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
  942. PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
  943. PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
  944. /* IPSR8 */
  945. PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
  946. PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
  947. PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
  948. PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
  949. PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
  950. PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
  951. PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
  952. PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
  953. PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
  954. PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
  955. PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
  956. PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
  957. PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
  958. PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
  959. PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
  960. PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
  961. PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
  962. PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
  963. PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
  964. PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
  965. PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
  966. PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
  967. PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
  968. PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
  969. PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
  970. PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
  971. PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
  972. PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
  973. PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
  974. PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
  975. PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
  976. PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
  977. PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
  978. PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
  979. PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
  980. /* IPSR9 */
  981. PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
  982. PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
  983. PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
  984. PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
  985. PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
  986. PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
  987. PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
  988. PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
  989. PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
  990. PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
  991. PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
  992. /* IPSR10 */
  993. PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
  994. PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
  995. PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
  996. PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
  997. PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
  998. PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
  999. PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
  1000. PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
  1001. PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
  1002. PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0),
  1003. PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
  1004. PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1),
  1005. PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0),
  1006. PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
  1007. PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1),
  1008. PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
  1009. PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
  1010. PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
  1011. PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
  1012. PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
  1013. PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
  1014. PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
  1015. PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
  1016. PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
  1017. PINMUX_IPSR_GPSR(IP10_31_28, RX0),
  1018. PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
  1019. PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
  1020. PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
  1021. PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
  1022. /* IPSR11 */
  1023. PINMUX_IPSR_GPSR(IP11_3_0, TX0),
  1024. PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
  1025. PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
  1026. PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
  1027. PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
  1028. PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
  1029. PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
  1030. PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
  1031. PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
  1032. PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
  1033. PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
  1034. PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
  1035. PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
  1036. PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N),
  1037. PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
  1038. PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
  1039. PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
  1040. PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
  1041. PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
  1042. PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
  1043. PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
  1044. PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
  1045. PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
  1046. PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
  1047. PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
  1048. PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
  1049. PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
  1050. PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
  1051. PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
  1052. PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
  1053. PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
  1054. PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
  1055. PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
  1056. PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
  1057. PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
  1058. PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
  1059. PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
  1060. PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
  1061. PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
  1062. PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
  1063. PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
  1064. PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
  1065. PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
  1066. PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
  1067. PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
  1068. PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
  1069. PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
  1070. PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
  1071. PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
  1072. PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
  1073. PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
  1074. PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
  1075. /* IPSR12 */
  1076. PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
  1077. PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
  1078. PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
  1079. PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
  1080. PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
  1081. PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
  1082. PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
  1083. PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
  1084. PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
  1085. PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
  1086. PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
  1087. PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
  1088. PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
  1089. PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
  1090. PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
  1091. PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
  1092. PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
  1093. PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
  1094. PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
  1095. PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
  1096. PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
  1097. PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
  1098. PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
  1099. PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
  1100. PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
  1101. PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
  1102. PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
  1103. PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
  1104. PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
  1105. PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
  1106. PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
  1107. PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
  1108. PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
  1109. PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
  1110. PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
  1111. PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
  1112. PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
  1113. PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
  1114. PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
  1115. PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
  1116. PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
  1117. PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
  1118. PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
  1119. PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
  1120. PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
  1121. PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
  1122. PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
  1123. PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
  1124. /* IPSR13 */
  1125. PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
  1126. PINMUX_IPSR_GPSR(IP13_3_0, RX5),
  1127. PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
  1128. PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
  1129. PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
  1130. PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
  1131. PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
  1132. PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
  1133. PINMUX_IPSR_GPSR(IP13_7_4, TX5),
  1134. PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
  1135. PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
  1136. PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
  1137. PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
  1138. PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
  1139. PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
  1140. PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
  1141. PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
  1142. PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
  1143. PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
  1144. PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
  1145. PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
  1146. PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
  1147. PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
  1148. PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
  1149. PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
  1150. PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
  1151. PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
  1152. PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
  1153. PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
  1154. PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
  1155. PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
  1156. /* IPSR14 */
  1157. PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
  1158. PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
  1159. PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
  1160. PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK349),
  1161. PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
  1162. PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
  1163. PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS349),
  1164. PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
  1165. PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
  1166. PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
  1167. PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
  1168. PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
  1169. PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
  1170. PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
  1171. PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
  1172. PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
  1173. PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
  1174. PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
  1175. PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
  1176. PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
  1177. PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
  1178. PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
  1179. PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
  1180. PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
  1181. PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
  1182. PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
  1183. PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
  1184. PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
  1185. PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
  1186. PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
  1187. PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
  1188. PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
  1189. PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
  1190. PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
  1191. PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
  1192. PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
  1193. PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
  1194. PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
  1195. /* IPSR15 */
  1196. PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
  1197. PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
  1198. PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
  1199. PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
  1200. PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
  1201. PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
  1202. PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
  1203. PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
  1204. PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
  1205. PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
  1206. PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
  1207. PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
  1208. PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
  1209. PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
  1210. PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
  1211. PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
  1212. PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
  1213. PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
  1214. PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
  1215. PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
  1216. PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
  1217. PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
  1218. PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
  1219. PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
  1220. PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
  1221. PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
  1222. PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
  1223. PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
  1224. PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
  1225. PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
  1226. PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
  1227. PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
  1228. PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
  1229. PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
  1230. PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
  1231. PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
  1232. PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
  1233. PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
  1234. PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
  1235. PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
  1236. PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
  1237. PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
  1238. PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
  1239. PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
  1240. PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
  1241. PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
  1242. /* IPSR16 */
  1243. PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
  1244. PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
  1245. PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
  1246. PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
  1247. PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
  1248. PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
  1249. PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
  1250. PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
  1251. PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
  1252. PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
  1253. PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
  1254. PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
  1255. PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
  1256. PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
  1257. PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
  1258. PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
  1259. PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
  1260. PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
  1261. PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
  1262. PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
  1263. PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
  1264. PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
  1265. PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
  1266. PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
  1267. PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
  1268. PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
  1269. PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
  1270. PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
  1271. PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
  1272. PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
  1273. PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
  1274. PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
  1275. PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
  1276. PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
  1277. PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
  1278. PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
  1279. PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
  1280. PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
  1281. PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
  1282. PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
  1283. PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
  1284. PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
  1285. PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
  1286. PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
  1287. PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
  1288. PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
  1289. PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
  1290. PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
  1291. PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
  1292. PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
  1293. PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
  1294. /* IPSR17 */
  1295. PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
  1296. PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
  1297. PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
  1298. PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
  1299. PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
  1300. PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
  1301. PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
  1302. PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
  1303. PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
  1304. PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
  1305. PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
  1306. PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
  1307. PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
  1308. PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
  1309. /*
  1310. * Static pins can not be muxed between different functions but
  1311. * still need mark entries in the pinmux list. Add each static
  1312. * pin to the list without an associated function. The sh-pfc
  1313. * core will do the right thing and skip trying to mux the pin
  1314. * while still applying configuration to it.
  1315. */
  1316. #define FM(x) PINMUX_DATA(x##_MARK, 0),
  1317. PINMUX_STATIC
  1318. #undef FM
  1319. };
  1320. /*
  1321. * Pins not associated with a GPIO port.
  1322. */
  1323. enum {
  1324. GP_ASSIGN_LAST(),
  1325. NOGP_ALL(),
  1326. };
  1327. static const struct sh_pfc_pin pinmux_pins[] = {
  1328. PINMUX_GPIO_GP_ALL(),
  1329. PINMUX_NOGP_ALL(),
  1330. };
  1331. /* - AUDIO CLOCK ------------------------------------------------------------ */
  1332. static const unsigned int audio_clk_a_a_pins[] = {
  1333. /* CLK A */
  1334. RCAR_GP_PIN(6, 22),
  1335. };
  1336. static const unsigned int audio_clk_a_a_mux[] = {
  1337. AUDIO_CLKA_A_MARK,
  1338. };
  1339. static const unsigned int audio_clk_a_b_pins[] = {
  1340. /* CLK A */
  1341. RCAR_GP_PIN(5, 4),
  1342. };
  1343. static const unsigned int audio_clk_a_b_mux[] = {
  1344. AUDIO_CLKA_B_MARK,
  1345. };
  1346. static const unsigned int audio_clk_a_c_pins[] = {
  1347. /* CLK A */
  1348. RCAR_GP_PIN(5, 19),
  1349. };
  1350. static const unsigned int audio_clk_a_c_mux[] = {
  1351. AUDIO_CLKA_C_MARK,
  1352. };
  1353. static const unsigned int audio_clk_b_a_pins[] = {
  1354. /* CLK B */
  1355. RCAR_GP_PIN(5, 12),
  1356. };
  1357. static const unsigned int audio_clk_b_a_mux[] = {
  1358. AUDIO_CLKB_A_MARK,
  1359. };
  1360. static const unsigned int audio_clk_b_b_pins[] = {
  1361. /* CLK B */
  1362. RCAR_GP_PIN(6, 23),
  1363. };
  1364. static const unsigned int audio_clk_b_b_mux[] = {
  1365. AUDIO_CLKB_B_MARK,
  1366. };
  1367. static const unsigned int audio_clk_c_a_pins[] = {
  1368. /* CLK C */
  1369. RCAR_GP_PIN(5, 21),
  1370. };
  1371. static const unsigned int audio_clk_c_a_mux[] = {
  1372. AUDIO_CLKC_A_MARK,
  1373. };
  1374. static const unsigned int audio_clk_c_b_pins[] = {
  1375. /* CLK C */
  1376. RCAR_GP_PIN(5, 0),
  1377. };
  1378. static const unsigned int audio_clk_c_b_mux[] = {
  1379. AUDIO_CLKC_B_MARK,
  1380. };
  1381. static const unsigned int audio_clkout_a_pins[] = {
  1382. /* CLKOUT */
  1383. RCAR_GP_PIN(5, 18),
  1384. };
  1385. static const unsigned int audio_clkout_a_mux[] = {
  1386. AUDIO_CLKOUT_A_MARK,
  1387. };
  1388. static const unsigned int audio_clkout_b_pins[] = {
  1389. /* CLKOUT */
  1390. RCAR_GP_PIN(6, 28),
  1391. };
  1392. static const unsigned int audio_clkout_b_mux[] = {
  1393. AUDIO_CLKOUT_B_MARK,
  1394. };
  1395. static const unsigned int audio_clkout_c_pins[] = {
  1396. /* CLKOUT */
  1397. RCAR_GP_PIN(5, 3),
  1398. };
  1399. static const unsigned int audio_clkout_c_mux[] = {
  1400. AUDIO_CLKOUT_C_MARK,
  1401. };
  1402. static const unsigned int audio_clkout_d_pins[] = {
  1403. /* CLKOUT */
  1404. RCAR_GP_PIN(5, 21),
  1405. };
  1406. static const unsigned int audio_clkout_d_mux[] = {
  1407. AUDIO_CLKOUT_D_MARK,
  1408. };
  1409. static const unsigned int audio_clkout1_a_pins[] = {
  1410. /* CLKOUT1 */
  1411. RCAR_GP_PIN(5, 15),
  1412. };
  1413. static const unsigned int audio_clkout1_a_mux[] = {
  1414. AUDIO_CLKOUT1_A_MARK,
  1415. };
  1416. static const unsigned int audio_clkout1_b_pins[] = {
  1417. /* CLKOUT1 */
  1418. RCAR_GP_PIN(6, 29),
  1419. };
  1420. static const unsigned int audio_clkout1_b_mux[] = {
  1421. AUDIO_CLKOUT1_B_MARK,
  1422. };
  1423. static const unsigned int audio_clkout2_a_pins[] = {
  1424. /* CLKOUT2 */
  1425. RCAR_GP_PIN(5, 16),
  1426. };
  1427. static const unsigned int audio_clkout2_a_mux[] = {
  1428. AUDIO_CLKOUT2_A_MARK,
  1429. };
  1430. static const unsigned int audio_clkout2_b_pins[] = {
  1431. /* CLKOUT2 */
  1432. RCAR_GP_PIN(6, 30),
  1433. };
  1434. static const unsigned int audio_clkout2_b_mux[] = {
  1435. AUDIO_CLKOUT2_B_MARK,
  1436. };
  1437. static const unsigned int audio_clkout3_a_pins[] = {
  1438. /* CLKOUT3 */
  1439. RCAR_GP_PIN(5, 19),
  1440. };
  1441. static const unsigned int audio_clkout3_a_mux[] = {
  1442. AUDIO_CLKOUT3_A_MARK,
  1443. };
  1444. static const unsigned int audio_clkout3_b_pins[] = {
  1445. /* CLKOUT3 */
  1446. RCAR_GP_PIN(6, 31),
  1447. };
  1448. static const unsigned int audio_clkout3_b_mux[] = {
  1449. AUDIO_CLKOUT3_B_MARK,
  1450. };
  1451. /* - EtherAVB --------------------------------------------------------------- */
  1452. static const unsigned int avb_link_pins[] = {
  1453. /* AVB_LINK */
  1454. RCAR_GP_PIN(2, 12),
  1455. };
  1456. static const unsigned int avb_link_mux[] = {
  1457. AVB_LINK_MARK,
  1458. };
  1459. static const unsigned int avb_magic_pins[] = {
  1460. /* AVB_MAGIC_ */
  1461. RCAR_GP_PIN(2, 10),
  1462. };
  1463. static const unsigned int avb_magic_mux[] = {
  1464. AVB_MAGIC_MARK,
  1465. };
  1466. static const unsigned int avb_phy_int_pins[] = {
  1467. /* AVB_PHY_INT */
  1468. RCAR_GP_PIN(2, 11),
  1469. };
  1470. static const unsigned int avb_phy_int_mux[] = {
  1471. AVB_PHY_INT_MARK,
  1472. };
  1473. static const unsigned int avb_mdio_pins[] = {
  1474. /* AVB_MDC, AVB_MDIO */
  1475. RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
  1476. };
  1477. static const unsigned int avb_mdio_mux[] = {
  1478. AVB_MDC_MARK, AVB_MDIO_MARK,
  1479. };
  1480. static const unsigned int avb_mii_pins[] = {
  1481. /*
  1482. * AVB_TX_CTL, AVB_TXC, AVB_TD0,
  1483. * AVB_TD1, AVB_TD2, AVB_TD3,
  1484. * AVB_RX_CTL, AVB_RXC, AVB_RD0,
  1485. * AVB_RD1, AVB_RD2, AVB_RD3,
  1486. * AVB_TXCREFCLK
  1487. */
  1488. PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
  1489. PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
  1490. PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
  1491. PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
  1492. PIN_AVB_TXCREFCLK,
  1493. };
  1494. static const unsigned int avb_mii_mux[] = {
  1495. AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
  1496. AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
  1497. AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
  1498. AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
  1499. AVB_TXCREFCLK_MARK,
  1500. };
  1501. static const unsigned int avb_avtp_pps_pins[] = {
  1502. /* AVB_AVTP_PPS */
  1503. RCAR_GP_PIN(2, 6),
  1504. };
  1505. static const unsigned int avb_avtp_pps_mux[] = {
  1506. AVB_AVTP_PPS_MARK,
  1507. };
  1508. static const unsigned int avb_avtp_match_a_pins[] = {
  1509. /* AVB_AVTP_MATCH_A */
  1510. RCAR_GP_PIN(2, 13),
  1511. };
  1512. static const unsigned int avb_avtp_match_a_mux[] = {
  1513. AVB_AVTP_MATCH_A_MARK,
  1514. };
  1515. static const unsigned int avb_avtp_capture_a_pins[] = {
  1516. /* AVB_AVTP_CAPTURE_A */
  1517. RCAR_GP_PIN(2, 14),
  1518. };
  1519. static const unsigned int avb_avtp_capture_a_mux[] = {
  1520. AVB_AVTP_CAPTURE_A_MARK,
  1521. };
  1522. static const unsigned int avb_avtp_match_b_pins[] = {
  1523. /* AVB_AVTP_MATCH_B */
  1524. RCAR_GP_PIN(1, 8),
  1525. };
  1526. static const unsigned int avb_avtp_match_b_mux[] = {
  1527. AVB_AVTP_MATCH_B_MARK,
  1528. };
  1529. static const unsigned int avb_avtp_capture_b_pins[] = {
  1530. /* AVB_AVTP_CAPTURE_B */
  1531. RCAR_GP_PIN(1, 11),
  1532. };
  1533. static const unsigned int avb_avtp_capture_b_mux[] = {
  1534. AVB_AVTP_CAPTURE_B_MARK,
  1535. };
  1536. /* - CAN ------------------------------------------------------------------ */
  1537. static const unsigned int can0_data_a_pins[] = {
  1538. /* TX, RX */
  1539. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  1540. };
  1541. static const unsigned int can0_data_a_mux[] = {
  1542. CAN0_TX_A_MARK, CAN0_RX_A_MARK,
  1543. };
  1544. static const unsigned int can0_data_b_pins[] = {
  1545. /* TX, RX */
  1546. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1547. };
  1548. static const unsigned int can0_data_b_mux[] = {
  1549. CAN0_TX_B_MARK, CAN0_RX_B_MARK,
  1550. };
  1551. static const unsigned int can1_data_pins[] = {
  1552. /* TX, RX */
  1553. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
  1554. };
  1555. static const unsigned int can1_data_mux[] = {
  1556. CAN1_TX_MARK, CAN1_RX_MARK,
  1557. };
  1558. /* - CAN Clock -------------------------------------------------------------- */
  1559. static const unsigned int can_clk_pins[] = {
  1560. /* CLK */
  1561. RCAR_GP_PIN(1, 25),
  1562. };
  1563. static const unsigned int can_clk_mux[] = {
  1564. CAN_CLK_MARK,
  1565. };
  1566. /* - CAN FD --------------------------------------------------------------- */
  1567. static const unsigned int canfd0_data_a_pins[] = {
  1568. /* TX, RX */
  1569. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  1570. };
  1571. static const unsigned int canfd0_data_a_mux[] = {
  1572. CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
  1573. };
  1574. static const unsigned int canfd0_data_b_pins[] = {
  1575. /* TX, RX */
  1576. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1577. };
  1578. static const unsigned int canfd0_data_b_mux[] = {
  1579. CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
  1580. };
  1581. static const unsigned int canfd1_data_pins[] = {
  1582. /* TX, RX */
  1583. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
  1584. };
  1585. static const unsigned int canfd1_data_mux[] = {
  1586. CANFD1_TX_MARK, CANFD1_RX_MARK,
  1587. };
  1588. /* - DRIF0 --------------------------------------------------------------- */
  1589. static const unsigned int drif0_ctrl_a_pins[] = {
  1590. /* CLK, SYNC */
  1591. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  1592. };
  1593. static const unsigned int drif0_ctrl_a_mux[] = {
  1594. RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
  1595. };
  1596. static const unsigned int drif0_data0_a_pins[] = {
  1597. /* D0 */
  1598. RCAR_GP_PIN(6, 10),
  1599. };
  1600. static const unsigned int drif0_data0_a_mux[] = {
  1601. RIF0_D0_A_MARK,
  1602. };
  1603. static const unsigned int drif0_data1_a_pins[] = {
  1604. /* D1 */
  1605. RCAR_GP_PIN(6, 7),
  1606. };
  1607. static const unsigned int drif0_data1_a_mux[] = {
  1608. RIF0_D1_A_MARK,
  1609. };
  1610. static const unsigned int drif0_ctrl_b_pins[] = {
  1611. /* CLK, SYNC */
  1612. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
  1613. };
  1614. static const unsigned int drif0_ctrl_b_mux[] = {
  1615. RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
  1616. };
  1617. static const unsigned int drif0_data0_b_pins[] = {
  1618. /* D0 */
  1619. RCAR_GP_PIN(5, 1),
  1620. };
  1621. static const unsigned int drif0_data0_b_mux[] = {
  1622. RIF0_D0_B_MARK,
  1623. };
  1624. static const unsigned int drif0_data1_b_pins[] = {
  1625. /* D1 */
  1626. RCAR_GP_PIN(5, 2),
  1627. };
  1628. static const unsigned int drif0_data1_b_mux[] = {
  1629. RIF0_D1_B_MARK,
  1630. };
  1631. static const unsigned int drif0_ctrl_c_pins[] = {
  1632. /* CLK, SYNC */
  1633. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
  1634. };
  1635. static const unsigned int drif0_ctrl_c_mux[] = {
  1636. RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
  1637. };
  1638. static const unsigned int drif0_data0_c_pins[] = {
  1639. /* D0 */
  1640. RCAR_GP_PIN(5, 13),
  1641. };
  1642. static const unsigned int drif0_data0_c_mux[] = {
  1643. RIF0_D0_C_MARK,
  1644. };
  1645. static const unsigned int drif0_data1_c_pins[] = {
  1646. /* D1 */
  1647. RCAR_GP_PIN(5, 14),
  1648. };
  1649. static const unsigned int drif0_data1_c_mux[] = {
  1650. RIF0_D1_C_MARK,
  1651. };
  1652. /* - DRIF1 --------------------------------------------------------------- */
  1653. static const unsigned int drif1_ctrl_a_pins[] = {
  1654. /* CLK, SYNC */
  1655. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  1656. };
  1657. static const unsigned int drif1_ctrl_a_mux[] = {
  1658. RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
  1659. };
  1660. static const unsigned int drif1_data0_a_pins[] = {
  1661. /* D0 */
  1662. RCAR_GP_PIN(6, 19),
  1663. };
  1664. static const unsigned int drif1_data0_a_mux[] = {
  1665. RIF1_D0_A_MARK,
  1666. };
  1667. static const unsigned int drif1_data1_a_pins[] = {
  1668. /* D1 */
  1669. RCAR_GP_PIN(6, 20),
  1670. };
  1671. static const unsigned int drif1_data1_a_mux[] = {
  1672. RIF1_D1_A_MARK,
  1673. };
  1674. static const unsigned int drif1_ctrl_b_pins[] = {
  1675. /* CLK, SYNC */
  1676. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
  1677. };
  1678. static const unsigned int drif1_ctrl_b_mux[] = {
  1679. RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
  1680. };
  1681. static const unsigned int drif1_data0_b_pins[] = {
  1682. /* D0 */
  1683. RCAR_GP_PIN(5, 7),
  1684. };
  1685. static const unsigned int drif1_data0_b_mux[] = {
  1686. RIF1_D0_B_MARK,
  1687. };
  1688. static const unsigned int drif1_data1_b_pins[] = {
  1689. /* D1 */
  1690. RCAR_GP_PIN(5, 8),
  1691. };
  1692. static const unsigned int drif1_data1_b_mux[] = {
  1693. RIF1_D1_B_MARK,
  1694. };
  1695. static const unsigned int drif1_ctrl_c_pins[] = {
  1696. /* CLK, SYNC */
  1697. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
  1698. };
  1699. static const unsigned int drif1_ctrl_c_mux[] = {
  1700. RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
  1701. };
  1702. static const unsigned int drif1_data0_c_pins[] = {
  1703. /* D0 */
  1704. RCAR_GP_PIN(5, 6),
  1705. };
  1706. static const unsigned int drif1_data0_c_mux[] = {
  1707. RIF1_D0_C_MARK,
  1708. };
  1709. static const unsigned int drif1_data1_c_pins[] = {
  1710. /* D1 */
  1711. RCAR_GP_PIN(5, 10),
  1712. };
  1713. static const unsigned int drif1_data1_c_mux[] = {
  1714. RIF1_D1_C_MARK,
  1715. };
  1716. /* - DRIF2 --------------------------------------------------------------- */
  1717. static const unsigned int drif2_ctrl_a_pins[] = {
  1718. /* CLK, SYNC */
  1719. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  1720. };
  1721. static const unsigned int drif2_ctrl_a_mux[] = {
  1722. RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
  1723. };
  1724. static const unsigned int drif2_data0_a_pins[] = {
  1725. /* D0 */
  1726. RCAR_GP_PIN(6, 7),
  1727. };
  1728. static const unsigned int drif2_data0_a_mux[] = {
  1729. RIF2_D0_A_MARK,
  1730. };
  1731. static const unsigned int drif2_data1_a_pins[] = {
  1732. /* D1 */
  1733. RCAR_GP_PIN(6, 10),
  1734. };
  1735. static const unsigned int drif2_data1_a_mux[] = {
  1736. RIF2_D1_A_MARK,
  1737. };
  1738. static const unsigned int drif2_ctrl_b_pins[] = {
  1739. /* CLK, SYNC */
  1740. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  1741. };
  1742. static const unsigned int drif2_ctrl_b_mux[] = {
  1743. RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
  1744. };
  1745. static const unsigned int drif2_data0_b_pins[] = {
  1746. /* D0 */
  1747. RCAR_GP_PIN(6, 30),
  1748. };
  1749. static const unsigned int drif2_data0_b_mux[] = {
  1750. RIF2_D0_B_MARK,
  1751. };
  1752. static const unsigned int drif2_data1_b_pins[] = {
  1753. /* D1 */
  1754. RCAR_GP_PIN(6, 31),
  1755. };
  1756. static const unsigned int drif2_data1_b_mux[] = {
  1757. RIF2_D1_B_MARK,
  1758. };
  1759. /* - DRIF3 --------------------------------------------------------------- */
  1760. static const unsigned int drif3_ctrl_a_pins[] = {
  1761. /* CLK, SYNC */
  1762. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  1763. };
  1764. static const unsigned int drif3_ctrl_a_mux[] = {
  1765. RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
  1766. };
  1767. static const unsigned int drif3_data0_a_pins[] = {
  1768. /* D0 */
  1769. RCAR_GP_PIN(6, 19),
  1770. };
  1771. static const unsigned int drif3_data0_a_mux[] = {
  1772. RIF3_D0_A_MARK,
  1773. };
  1774. static const unsigned int drif3_data1_a_pins[] = {
  1775. /* D1 */
  1776. RCAR_GP_PIN(6, 20),
  1777. };
  1778. static const unsigned int drif3_data1_a_mux[] = {
  1779. RIF3_D1_A_MARK,
  1780. };
  1781. static const unsigned int drif3_ctrl_b_pins[] = {
  1782. /* CLK, SYNC */
  1783. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  1784. };
  1785. static const unsigned int drif3_ctrl_b_mux[] = {
  1786. RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
  1787. };
  1788. static const unsigned int drif3_data0_b_pins[] = {
  1789. /* D0 */
  1790. RCAR_GP_PIN(6, 28),
  1791. };
  1792. static const unsigned int drif3_data0_b_mux[] = {
  1793. RIF3_D0_B_MARK,
  1794. };
  1795. static const unsigned int drif3_data1_b_pins[] = {
  1796. /* D1 */
  1797. RCAR_GP_PIN(6, 29),
  1798. };
  1799. static const unsigned int drif3_data1_b_mux[] = {
  1800. RIF3_D1_B_MARK,
  1801. };
  1802. /* - DU --------------------------------------------------------------------- */
  1803. static const unsigned int du_rgb666_pins[] = {
  1804. /* R[7:2], G[7:2], B[7:2] */
  1805. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
  1806. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  1807. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  1808. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
  1809. RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
  1810. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
  1811. };
  1812. static const unsigned int du_rgb666_mux[] = {
  1813. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
  1814. DU_DR3_MARK, DU_DR2_MARK,
  1815. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
  1816. DU_DG3_MARK, DU_DG2_MARK,
  1817. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
  1818. DU_DB3_MARK, DU_DB2_MARK,
  1819. };
  1820. static const unsigned int du_rgb888_pins[] = {
  1821. /* R[7:0], G[7:0], B[7:0] */
  1822. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
  1823. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  1824. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
  1825. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  1826. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
  1827. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
  1828. RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
  1829. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
  1830. RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
  1831. };
  1832. static const unsigned int du_rgb888_mux[] = {
  1833. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
  1834. DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
  1835. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
  1836. DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
  1837. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
  1838. DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
  1839. };
  1840. static const unsigned int du_clk_out_0_pins[] = {
  1841. /* CLKOUT */
  1842. RCAR_GP_PIN(1, 27),
  1843. };
  1844. static const unsigned int du_clk_out_0_mux[] = {
  1845. DU_DOTCLKOUT0_MARK
  1846. };
  1847. static const unsigned int du_clk_out_1_pins[] = {
  1848. /* CLKOUT */
  1849. RCAR_GP_PIN(2, 3),
  1850. };
  1851. static const unsigned int du_clk_out_1_mux[] = {
  1852. DU_DOTCLKOUT1_MARK
  1853. };
  1854. static const unsigned int du_sync_pins[] = {
  1855. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  1856. RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
  1857. };
  1858. static const unsigned int du_sync_mux[] = {
  1859. DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
  1860. };
  1861. static const unsigned int du_oddf_pins[] = {
  1862. /* EXDISP/EXODDF/EXCDE */
  1863. RCAR_GP_PIN(2, 2),
  1864. };
  1865. static const unsigned int du_oddf_mux[] = {
  1866. DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
  1867. };
  1868. static const unsigned int du_cde_pins[] = {
  1869. /* CDE */
  1870. RCAR_GP_PIN(2, 0),
  1871. };
  1872. static const unsigned int du_cde_mux[] = {
  1873. DU_CDE_MARK,
  1874. };
  1875. static const unsigned int du_disp_pins[] = {
  1876. /* DISP */
  1877. RCAR_GP_PIN(2, 1),
  1878. };
  1879. static const unsigned int du_disp_mux[] = {
  1880. DU_DISP_MARK,
  1881. };
  1882. /* - HSCIF0 ----------------------------------------------------------------- */
  1883. static const unsigned int hscif0_data_pins[] = {
  1884. /* RX, TX */
  1885. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
  1886. };
  1887. static const unsigned int hscif0_data_mux[] = {
  1888. HRX0_MARK, HTX0_MARK,
  1889. };
  1890. static const unsigned int hscif0_clk_pins[] = {
  1891. /* SCK */
  1892. RCAR_GP_PIN(5, 12),
  1893. };
  1894. static const unsigned int hscif0_clk_mux[] = {
  1895. HSCK0_MARK,
  1896. };
  1897. static const unsigned int hscif0_ctrl_pins[] = {
  1898. /* RTS, CTS */
  1899. RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
  1900. };
  1901. static const unsigned int hscif0_ctrl_mux[] = {
  1902. HRTS0_N_MARK, HCTS0_N_MARK,
  1903. };
  1904. /* - HSCIF1 ----------------------------------------------------------------- */
  1905. static const unsigned int hscif1_data_a_pins[] = {
  1906. /* RX, TX */
  1907. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  1908. };
  1909. static const unsigned int hscif1_data_a_mux[] = {
  1910. HRX1_A_MARK, HTX1_A_MARK,
  1911. };
  1912. static const unsigned int hscif1_clk_a_pins[] = {
  1913. /* SCK */
  1914. RCAR_GP_PIN(6, 21),
  1915. };
  1916. static const unsigned int hscif1_clk_a_mux[] = {
  1917. HSCK1_A_MARK,
  1918. };
  1919. static const unsigned int hscif1_ctrl_a_pins[] = {
  1920. /* RTS, CTS */
  1921. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
  1922. };
  1923. static const unsigned int hscif1_ctrl_a_mux[] = {
  1924. HRTS1_N_A_MARK, HCTS1_N_A_MARK,
  1925. };
  1926. static const unsigned int hscif1_data_b_pins[] = {
  1927. /* RX, TX */
  1928. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1929. };
  1930. static const unsigned int hscif1_data_b_mux[] = {
  1931. HRX1_B_MARK, HTX1_B_MARK,
  1932. };
  1933. static const unsigned int hscif1_clk_b_pins[] = {
  1934. /* SCK */
  1935. RCAR_GP_PIN(5, 0),
  1936. };
  1937. static const unsigned int hscif1_clk_b_mux[] = {
  1938. HSCK1_B_MARK,
  1939. };
  1940. static const unsigned int hscif1_ctrl_b_pins[] = {
  1941. /* RTS, CTS */
  1942. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
  1943. };
  1944. static const unsigned int hscif1_ctrl_b_mux[] = {
  1945. HRTS1_N_B_MARK, HCTS1_N_B_MARK,
  1946. };
  1947. /* - HSCIF2 ----------------------------------------------------------------- */
  1948. static const unsigned int hscif2_data_a_pins[] = {
  1949. /* RX, TX */
  1950. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  1951. };
  1952. static const unsigned int hscif2_data_a_mux[] = {
  1953. HRX2_A_MARK, HTX2_A_MARK,
  1954. };
  1955. static const unsigned int hscif2_clk_a_pins[] = {
  1956. /* SCK */
  1957. RCAR_GP_PIN(6, 10),
  1958. };
  1959. static const unsigned int hscif2_clk_a_mux[] = {
  1960. HSCK2_A_MARK,
  1961. };
  1962. static const unsigned int hscif2_ctrl_a_pins[] = {
  1963. /* RTS, CTS */
  1964. RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
  1965. };
  1966. static const unsigned int hscif2_ctrl_a_mux[] = {
  1967. HRTS2_N_A_MARK, HCTS2_N_A_MARK,
  1968. };
  1969. static const unsigned int hscif2_data_b_pins[] = {
  1970. /* RX, TX */
  1971. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  1972. };
  1973. static const unsigned int hscif2_data_b_mux[] = {
  1974. HRX2_B_MARK, HTX2_B_MARK,
  1975. };
  1976. static const unsigned int hscif2_clk_b_pins[] = {
  1977. /* SCK */
  1978. RCAR_GP_PIN(6, 21),
  1979. };
  1980. static const unsigned int hscif2_clk_b_mux[] = {
  1981. HSCK2_B_MARK,
  1982. };
  1983. static const unsigned int hscif2_ctrl_b_pins[] = {
  1984. /* RTS, CTS */
  1985. RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
  1986. };
  1987. static const unsigned int hscif2_ctrl_b_mux[] = {
  1988. HRTS2_N_B_MARK, HCTS2_N_B_MARK,
  1989. };
  1990. /* - HSCIF3 ----------------------------------------------------------------- */
  1991. static const unsigned int hscif3_data_a_pins[] = {
  1992. /* RX, TX */
  1993. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  1994. };
  1995. static const unsigned int hscif3_data_a_mux[] = {
  1996. HRX3_A_MARK, HTX3_A_MARK,
  1997. };
  1998. static const unsigned int hscif3_clk_pins[] = {
  1999. /* SCK */
  2000. RCAR_GP_PIN(1, 22),
  2001. };
  2002. static const unsigned int hscif3_clk_mux[] = {
  2003. HSCK3_MARK,
  2004. };
  2005. static const unsigned int hscif3_ctrl_pins[] = {
  2006. /* RTS, CTS */
  2007. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  2008. };
  2009. static const unsigned int hscif3_ctrl_mux[] = {
  2010. HRTS3_N_MARK, HCTS3_N_MARK,
  2011. };
  2012. static const unsigned int hscif3_data_b_pins[] = {
  2013. /* RX, TX */
  2014. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  2015. };
  2016. static const unsigned int hscif3_data_b_mux[] = {
  2017. HRX3_B_MARK, HTX3_B_MARK,
  2018. };
  2019. static const unsigned int hscif3_data_c_pins[] = {
  2020. /* RX, TX */
  2021. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  2022. };
  2023. static const unsigned int hscif3_data_c_mux[] = {
  2024. HRX3_C_MARK, HTX3_C_MARK,
  2025. };
  2026. static const unsigned int hscif3_data_d_pins[] = {
  2027. /* RX, TX */
  2028. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  2029. };
  2030. static const unsigned int hscif3_data_d_mux[] = {
  2031. HRX3_D_MARK, HTX3_D_MARK,
  2032. };
  2033. /* - HSCIF4 ----------------------------------------------------------------- */
  2034. static const unsigned int hscif4_data_a_pins[] = {
  2035. /* RX, TX */
  2036. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
  2037. };
  2038. static const unsigned int hscif4_data_a_mux[] = {
  2039. HRX4_A_MARK, HTX4_A_MARK,
  2040. };
  2041. static const unsigned int hscif4_clk_pins[] = {
  2042. /* SCK */
  2043. RCAR_GP_PIN(1, 11),
  2044. };
  2045. static const unsigned int hscif4_clk_mux[] = {
  2046. HSCK4_MARK,
  2047. };
  2048. static const unsigned int hscif4_ctrl_pins[] = {
  2049. /* RTS, CTS */
  2050. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
  2051. };
  2052. static const unsigned int hscif4_ctrl_mux[] = {
  2053. HRTS4_N_MARK, HCTS4_N_MARK,
  2054. };
  2055. static const unsigned int hscif4_data_b_pins[] = {
  2056. /* RX, TX */
  2057. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  2058. };
  2059. static const unsigned int hscif4_data_b_mux[] = {
  2060. HRX4_B_MARK, HTX4_B_MARK,
  2061. };
  2062. /* - I2C -------------------------------------------------------------------- */
  2063. static const unsigned int i2c0_pins[] = {
  2064. /* SCL, SDA */
  2065. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  2066. };
  2067. static const unsigned int i2c0_mux[] = {
  2068. SCL0_MARK, SDA0_MARK,
  2069. };
  2070. static const unsigned int i2c1_a_pins[] = {
  2071. /* SDA, SCL */
  2072. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
  2073. };
  2074. static const unsigned int i2c1_a_mux[] = {
  2075. SDA1_A_MARK, SCL1_A_MARK,
  2076. };
  2077. static const unsigned int i2c1_b_pins[] = {
  2078. /* SDA, SCL */
  2079. RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
  2080. };
  2081. static const unsigned int i2c1_b_mux[] = {
  2082. SDA1_B_MARK, SCL1_B_MARK,
  2083. };
  2084. static const unsigned int i2c2_a_pins[] = {
  2085. /* SDA, SCL */
  2086. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
  2087. };
  2088. static const unsigned int i2c2_a_mux[] = {
  2089. SDA2_A_MARK, SCL2_A_MARK,
  2090. };
  2091. static const unsigned int i2c2_b_pins[] = {
  2092. /* SDA, SCL */
  2093. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
  2094. };
  2095. static const unsigned int i2c2_b_mux[] = {
  2096. SDA2_B_MARK, SCL2_B_MARK,
  2097. };
  2098. static const unsigned int i2c3_pins[] = {
  2099. /* SCL, SDA */
  2100. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  2101. };
  2102. static const unsigned int i2c3_mux[] = {
  2103. SCL3_MARK, SDA3_MARK,
  2104. };
  2105. static const unsigned int i2c5_pins[] = {
  2106. /* SCL, SDA */
  2107. RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
  2108. };
  2109. static const unsigned int i2c5_mux[] = {
  2110. SCL5_MARK, SDA5_MARK,
  2111. };
  2112. static const unsigned int i2c6_a_pins[] = {
  2113. /* SDA, SCL */
  2114. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  2115. };
  2116. static const unsigned int i2c6_a_mux[] = {
  2117. SDA6_A_MARK, SCL6_A_MARK,
  2118. };
  2119. static const unsigned int i2c6_b_pins[] = {
  2120. /* SDA, SCL */
  2121. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  2122. };
  2123. static const unsigned int i2c6_b_mux[] = {
  2124. SDA6_B_MARK, SCL6_B_MARK,
  2125. };
  2126. static const unsigned int i2c6_c_pins[] = {
  2127. /* SDA, SCL */
  2128. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
  2129. };
  2130. static const unsigned int i2c6_c_mux[] = {
  2131. SDA6_C_MARK, SCL6_C_MARK,
  2132. };
  2133. /* - INTC-EX ---------------------------------------------------------------- */
  2134. static const unsigned int intc_ex_irq0_pins[] = {
  2135. /* IRQ0 */
  2136. RCAR_GP_PIN(2, 0),
  2137. };
  2138. static const unsigned int intc_ex_irq0_mux[] = {
  2139. IRQ0_MARK,
  2140. };
  2141. static const unsigned int intc_ex_irq1_pins[] = {
  2142. /* IRQ1 */
  2143. RCAR_GP_PIN(2, 1),
  2144. };
  2145. static const unsigned int intc_ex_irq1_mux[] = {
  2146. IRQ1_MARK,
  2147. };
  2148. static const unsigned int intc_ex_irq2_pins[] = {
  2149. /* IRQ2 */
  2150. RCAR_GP_PIN(2, 2),
  2151. };
  2152. static const unsigned int intc_ex_irq2_mux[] = {
  2153. IRQ2_MARK,
  2154. };
  2155. static const unsigned int intc_ex_irq3_pins[] = {
  2156. /* IRQ3 */
  2157. RCAR_GP_PIN(2, 3),
  2158. };
  2159. static const unsigned int intc_ex_irq3_mux[] = {
  2160. IRQ3_MARK,
  2161. };
  2162. static const unsigned int intc_ex_irq4_pins[] = {
  2163. /* IRQ4 */
  2164. RCAR_GP_PIN(2, 4),
  2165. };
  2166. static const unsigned int intc_ex_irq4_mux[] = {
  2167. IRQ4_MARK,
  2168. };
  2169. static const unsigned int intc_ex_irq5_pins[] = {
  2170. /* IRQ5 */
  2171. RCAR_GP_PIN(2, 5),
  2172. };
  2173. static const unsigned int intc_ex_irq5_mux[] = {
  2174. IRQ5_MARK,
  2175. };
  2176. /* - MLB+ ------------------------------------------------------------------- */
  2177. static const unsigned int mlb_3pin_pins[] = {
  2178. RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
  2179. };
  2180. static const unsigned int mlb_3pin_mux[] = {
  2181. MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
  2182. };
  2183. /* - MSIOF0 ----------------------------------------------------------------- */
  2184. static const unsigned int msiof0_clk_pins[] = {
  2185. /* SCK */
  2186. RCAR_GP_PIN(5, 17),
  2187. };
  2188. static const unsigned int msiof0_clk_mux[] = {
  2189. MSIOF0_SCK_MARK,
  2190. };
  2191. static const unsigned int msiof0_sync_pins[] = {
  2192. /* SYNC */
  2193. RCAR_GP_PIN(5, 18),
  2194. };
  2195. static const unsigned int msiof0_sync_mux[] = {
  2196. MSIOF0_SYNC_MARK,
  2197. };
  2198. static const unsigned int msiof0_ss1_pins[] = {
  2199. /* SS1 */
  2200. RCAR_GP_PIN(5, 19),
  2201. };
  2202. static const unsigned int msiof0_ss1_mux[] = {
  2203. MSIOF0_SS1_MARK,
  2204. };
  2205. static const unsigned int msiof0_ss2_pins[] = {
  2206. /* SS2 */
  2207. RCAR_GP_PIN(5, 21),
  2208. };
  2209. static const unsigned int msiof0_ss2_mux[] = {
  2210. MSIOF0_SS2_MARK,
  2211. };
  2212. static const unsigned int msiof0_txd_pins[] = {
  2213. /* TXD */
  2214. RCAR_GP_PIN(5, 20),
  2215. };
  2216. static const unsigned int msiof0_txd_mux[] = {
  2217. MSIOF0_TXD_MARK,
  2218. };
  2219. static const unsigned int msiof0_rxd_pins[] = {
  2220. /* RXD */
  2221. RCAR_GP_PIN(5, 22),
  2222. };
  2223. static const unsigned int msiof0_rxd_mux[] = {
  2224. MSIOF0_RXD_MARK,
  2225. };
  2226. /* - MSIOF1 ----------------------------------------------------------------- */
  2227. static const unsigned int msiof1_clk_a_pins[] = {
  2228. /* SCK */
  2229. RCAR_GP_PIN(6, 8),
  2230. };
  2231. static const unsigned int msiof1_clk_a_mux[] = {
  2232. MSIOF1_SCK_A_MARK,
  2233. };
  2234. static const unsigned int msiof1_sync_a_pins[] = {
  2235. /* SYNC */
  2236. RCAR_GP_PIN(6, 9),
  2237. };
  2238. static const unsigned int msiof1_sync_a_mux[] = {
  2239. MSIOF1_SYNC_A_MARK,
  2240. };
  2241. static const unsigned int msiof1_ss1_a_pins[] = {
  2242. /* SS1 */
  2243. RCAR_GP_PIN(6, 5),
  2244. };
  2245. static const unsigned int msiof1_ss1_a_mux[] = {
  2246. MSIOF1_SS1_A_MARK,
  2247. };
  2248. static const unsigned int msiof1_ss2_a_pins[] = {
  2249. /* SS2 */
  2250. RCAR_GP_PIN(6, 6),
  2251. };
  2252. static const unsigned int msiof1_ss2_a_mux[] = {
  2253. MSIOF1_SS2_A_MARK,
  2254. };
  2255. static const unsigned int msiof1_txd_a_pins[] = {
  2256. /* TXD */
  2257. RCAR_GP_PIN(6, 7),
  2258. };
  2259. static const unsigned int msiof1_txd_a_mux[] = {
  2260. MSIOF1_TXD_A_MARK,
  2261. };
  2262. static const unsigned int msiof1_rxd_a_pins[] = {
  2263. /* RXD */
  2264. RCAR_GP_PIN(6, 10),
  2265. };
  2266. static const unsigned int msiof1_rxd_a_mux[] = {
  2267. MSIOF1_RXD_A_MARK,
  2268. };
  2269. static const unsigned int msiof1_clk_b_pins[] = {
  2270. /* SCK */
  2271. RCAR_GP_PIN(5, 9),
  2272. };
  2273. static const unsigned int msiof1_clk_b_mux[] = {
  2274. MSIOF1_SCK_B_MARK,
  2275. };
  2276. static const unsigned int msiof1_sync_b_pins[] = {
  2277. /* SYNC */
  2278. RCAR_GP_PIN(5, 3),
  2279. };
  2280. static const unsigned int msiof1_sync_b_mux[] = {
  2281. MSIOF1_SYNC_B_MARK,
  2282. };
  2283. static const unsigned int msiof1_ss1_b_pins[] = {
  2284. /* SS1 */
  2285. RCAR_GP_PIN(5, 4),
  2286. };
  2287. static const unsigned int msiof1_ss1_b_mux[] = {
  2288. MSIOF1_SS1_B_MARK,
  2289. };
  2290. static const unsigned int msiof1_ss2_b_pins[] = {
  2291. /* SS2 */
  2292. RCAR_GP_PIN(5, 0),
  2293. };
  2294. static const unsigned int msiof1_ss2_b_mux[] = {
  2295. MSIOF1_SS2_B_MARK,
  2296. };
  2297. static const unsigned int msiof1_txd_b_pins[] = {
  2298. /* TXD */
  2299. RCAR_GP_PIN(5, 8),
  2300. };
  2301. static const unsigned int msiof1_txd_b_mux[] = {
  2302. MSIOF1_TXD_B_MARK,
  2303. };
  2304. static const unsigned int msiof1_rxd_b_pins[] = {
  2305. /* RXD */
  2306. RCAR_GP_PIN(5, 7),
  2307. };
  2308. static const unsigned int msiof1_rxd_b_mux[] = {
  2309. MSIOF1_RXD_B_MARK,
  2310. };
  2311. static const unsigned int msiof1_clk_c_pins[] = {
  2312. /* SCK */
  2313. RCAR_GP_PIN(6, 17),
  2314. };
  2315. static const unsigned int msiof1_clk_c_mux[] = {
  2316. MSIOF1_SCK_C_MARK,
  2317. };
  2318. static const unsigned int msiof1_sync_c_pins[] = {
  2319. /* SYNC */
  2320. RCAR_GP_PIN(6, 18),
  2321. };
  2322. static const unsigned int msiof1_sync_c_mux[] = {
  2323. MSIOF1_SYNC_C_MARK,
  2324. };
  2325. static const unsigned int msiof1_ss1_c_pins[] = {
  2326. /* SS1 */
  2327. RCAR_GP_PIN(6, 21),
  2328. };
  2329. static const unsigned int msiof1_ss1_c_mux[] = {
  2330. MSIOF1_SS1_C_MARK,
  2331. };
  2332. static const unsigned int msiof1_ss2_c_pins[] = {
  2333. /* SS2 */
  2334. RCAR_GP_PIN(6, 27),
  2335. };
  2336. static const unsigned int msiof1_ss2_c_mux[] = {
  2337. MSIOF1_SS2_C_MARK,
  2338. };
  2339. static const unsigned int msiof1_txd_c_pins[] = {
  2340. /* TXD */
  2341. RCAR_GP_PIN(6, 20),
  2342. };
  2343. static const unsigned int msiof1_txd_c_mux[] = {
  2344. MSIOF1_TXD_C_MARK,
  2345. };
  2346. static const unsigned int msiof1_rxd_c_pins[] = {
  2347. /* RXD */
  2348. RCAR_GP_PIN(6, 19),
  2349. };
  2350. static const unsigned int msiof1_rxd_c_mux[] = {
  2351. MSIOF1_RXD_C_MARK,
  2352. };
  2353. static const unsigned int msiof1_clk_d_pins[] = {
  2354. /* SCK */
  2355. RCAR_GP_PIN(5, 12),
  2356. };
  2357. static const unsigned int msiof1_clk_d_mux[] = {
  2358. MSIOF1_SCK_D_MARK,
  2359. };
  2360. static const unsigned int msiof1_sync_d_pins[] = {
  2361. /* SYNC */
  2362. RCAR_GP_PIN(5, 15),
  2363. };
  2364. static const unsigned int msiof1_sync_d_mux[] = {
  2365. MSIOF1_SYNC_D_MARK,
  2366. };
  2367. static const unsigned int msiof1_ss1_d_pins[] = {
  2368. /* SS1 */
  2369. RCAR_GP_PIN(5, 16),
  2370. };
  2371. static const unsigned int msiof1_ss1_d_mux[] = {
  2372. MSIOF1_SS1_D_MARK,
  2373. };
  2374. static const unsigned int msiof1_ss2_d_pins[] = {
  2375. /* SS2 */
  2376. RCAR_GP_PIN(5, 21),
  2377. };
  2378. static const unsigned int msiof1_ss2_d_mux[] = {
  2379. MSIOF1_SS2_D_MARK,
  2380. };
  2381. static const unsigned int msiof1_txd_d_pins[] = {
  2382. /* TXD */
  2383. RCAR_GP_PIN(5, 14),
  2384. };
  2385. static const unsigned int msiof1_txd_d_mux[] = {
  2386. MSIOF1_TXD_D_MARK,
  2387. };
  2388. static const unsigned int msiof1_rxd_d_pins[] = {
  2389. /* RXD */
  2390. RCAR_GP_PIN(5, 13),
  2391. };
  2392. static const unsigned int msiof1_rxd_d_mux[] = {
  2393. MSIOF1_RXD_D_MARK,
  2394. };
  2395. static const unsigned int msiof1_clk_e_pins[] = {
  2396. /* SCK */
  2397. RCAR_GP_PIN(3, 0),
  2398. };
  2399. static const unsigned int msiof1_clk_e_mux[] = {
  2400. MSIOF1_SCK_E_MARK,
  2401. };
  2402. static const unsigned int msiof1_sync_e_pins[] = {
  2403. /* SYNC */
  2404. RCAR_GP_PIN(3, 1),
  2405. };
  2406. static const unsigned int msiof1_sync_e_mux[] = {
  2407. MSIOF1_SYNC_E_MARK,
  2408. };
  2409. static const unsigned int msiof1_ss1_e_pins[] = {
  2410. /* SS1 */
  2411. RCAR_GP_PIN(3, 4),
  2412. };
  2413. static const unsigned int msiof1_ss1_e_mux[] = {
  2414. MSIOF1_SS1_E_MARK,
  2415. };
  2416. static const unsigned int msiof1_ss2_e_pins[] = {
  2417. /* SS2 */
  2418. RCAR_GP_PIN(3, 5),
  2419. };
  2420. static const unsigned int msiof1_ss2_e_mux[] = {
  2421. MSIOF1_SS2_E_MARK,
  2422. };
  2423. static const unsigned int msiof1_txd_e_pins[] = {
  2424. /* TXD */
  2425. RCAR_GP_PIN(3, 3),
  2426. };
  2427. static const unsigned int msiof1_txd_e_mux[] = {
  2428. MSIOF1_TXD_E_MARK,
  2429. };
  2430. static const unsigned int msiof1_rxd_e_pins[] = {
  2431. /* RXD */
  2432. RCAR_GP_PIN(3, 2),
  2433. };
  2434. static const unsigned int msiof1_rxd_e_mux[] = {
  2435. MSIOF1_RXD_E_MARK,
  2436. };
  2437. static const unsigned int msiof1_clk_f_pins[] = {
  2438. /* SCK */
  2439. RCAR_GP_PIN(5, 23),
  2440. };
  2441. static const unsigned int msiof1_clk_f_mux[] = {
  2442. MSIOF1_SCK_F_MARK,
  2443. };
  2444. static const unsigned int msiof1_sync_f_pins[] = {
  2445. /* SYNC */
  2446. RCAR_GP_PIN(5, 24),
  2447. };
  2448. static const unsigned int msiof1_sync_f_mux[] = {
  2449. MSIOF1_SYNC_F_MARK,
  2450. };
  2451. static const unsigned int msiof1_ss1_f_pins[] = {
  2452. /* SS1 */
  2453. RCAR_GP_PIN(6, 1),
  2454. };
  2455. static const unsigned int msiof1_ss1_f_mux[] = {
  2456. MSIOF1_SS1_F_MARK,
  2457. };
  2458. static const unsigned int msiof1_ss2_f_pins[] = {
  2459. /* SS2 */
  2460. RCAR_GP_PIN(6, 2),
  2461. };
  2462. static const unsigned int msiof1_ss2_f_mux[] = {
  2463. MSIOF1_SS2_F_MARK,
  2464. };
  2465. static const unsigned int msiof1_txd_f_pins[] = {
  2466. /* TXD */
  2467. RCAR_GP_PIN(6, 0),
  2468. };
  2469. static const unsigned int msiof1_txd_f_mux[] = {
  2470. MSIOF1_TXD_F_MARK,
  2471. };
  2472. static const unsigned int msiof1_rxd_f_pins[] = {
  2473. /* RXD */
  2474. RCAR_GP_PIN(5, 25),
  2475. };
  2476. static const unsigned int msiof1_rxd_f_mux[] = {
  2477. MSIOF1_RXD_F_MARK,
  2478. };
  2479. static const unsigned int msiof1_clk_g_pins[] = {
  2480. /* SCK */
  2481. RCAR_GP_PIN(3, 6),
  2482. };
  2483. static const unsigned int msiof1_clk_g_mux[] = {
  2484. MSIOF1_SCK_G_MARK,
  2485. };
  2486. static const unsigned int msiof1_sync_g_pins[] = {
  2487. /* SYNC */
  2488. RCAR_GP_PIN(3, 7),
  2489. };
  2490. static const unsigned int msiof1_sync_g_mux[] = {
  2491. MSIOF1_SYNC_G_MARK,
  2492. };
  2493. static const unsigned int msiof1_ss1_g_pins[] = {
  2494. /* SS1 */
  2495. RCAR_GP_PIN(3, 10),
  2496. };
  2497. static const unsigned int msiof1_ss1_g_mux[] = {
  2498. MSIOF1_SS1_G_MARK,
  2499. };
  2500. static const unsigned int msiof1_ss2_g_pins[] = {
  2501. /* SS2 */
  2502. RCAR_GP_PIN(3, 11),
  2503. };
  2504. static const unsigned int msiof1_ss2_g_mux[] = {
  2505. MSIOF1_SS2_G_MARK,
  2506. };
  2507. static const unsigned int msiof1_txd_g_pins[] = {
  2508. /* TXD */
  2509. RCAR_GP_PIN(3, 9),
  2510. };
  2511. static const unsigned int msiof1_txd_g_mux[] = {
  2512. MSIOF1_TXD_G_MARK,
  2513. };
  2514. static const unsigned int msiof1_rxd_g_pins[] = {
  2515. /* RXD */
  2516. RCAR_GP_PIN(3, 8),
  2517. };
  2518. static const unsigned int msiof1_rxd_g_mux[] = {
  2519. MSIOF1_RXD_G_MARK,
  2520. };
  2521. /* - MSIOF2 ----------------------------------------------------------------- */
  2522. static const unsigned int msiof2_clk_a_pins[] = {
  2523. /* SCK */
  2524. RCAR_GP_PIN(1, 9),
  2525. };
  2526. static const unsigned int msiof2_clk_a_mux[] = {
  2527. MSIOF2_SCK_A_MARK,
  2528. };
  2529. static const unsigned int msiof2_sync_a_pins[] = {
  2530. /* SYNC */
  2531. RCAR_GP_PIN(1, 8),
  2532. };
  2533. static const unsigned int msiof2_sync_a_mux[] = {
  2534. MSIOF2_SYNC_A_MARK,
  2535. };
  2536. static const unsigned int msiof2_ss1_a_pins[] = {
  2537. /* SS1 */
  2538. RCAR_GP_PIN(1, 6),
  2539. };
  2540. static const unsigned int msiof2_ss1_a_mux[] = {
  2541. MSIOF2_SS1_A_MARK,
  2542. };
  2543. static const unsigned int msiof2_ss2_a_pins[] = {
  2544. /* SS2 */
  2545. RCAR_GP_PIN(1, 7),
  2546. };
  2547. static const unsigned int msiof2_ss2_a_mux[] = {
  2548. MSIOF2_SS2_A_MARK,
  2549. };
  2550. static const unsigned int msiof2_txd_a_pins[] = {
  2551. /* TXD */
  2552. RCAR_GP_PIN(1, 11),
  2553. };
  2554. static const unsigned int msiof2_txd_a_mux[] = {
  2555. MSIOF2_TXD_A_MARK,
  2556. };
  2557. static const unsigned int msiof2_rxd_a_pins[] = {
  2558. /* RXD */
  2559. RCAR_GP_PIN(1, 10),
  2560. };
  2561. static const unsigned int msiof2_rxd_a_mux[] = {
  2562. MSIOF2_RXD_A_MARK,
  2563. };
  2564. static const unsigned int msiof2_clk_b_pins[] = {
  2565. /* SCK */
  2566. RCAR_GP_PIN(0, 4),
  2567. };
  2568. static const unsigned int msiof2_clk_b_mux[] = {
  2569. MSIOF2_SCK_B_MARK,
  2570. };
  2571. static const unsigned int msiof2_sync_b_pins[] = {
  2572. /* SYNC */
  2573. RCAR_GP_PIN(0, 5),
  2574. };
  2575. static const unsigned int msiof2_sync_b_mux[] = {
  2576. MSIOF2_SYNC_B_MARK,
  2577. };
  2578. static const unsigned int msiof2_ss1_b_pins[] = {
  2579. /* SS1 */
  2580. RCAR_GP_PIN(0, 0),
  2581. };
  2582. static const unsigned int msiof2_ss1_b_mux[] = {
  2583. MSIOF2_SS1_B_MARK,
  2584. };
  2585. static const unsigned int msiof2_ss2_b_pins[] = {
  2586. /* SS2 */
  2587. RCAR_GP_PIN(0, 1),
  2588. };
  2589. static const unsigned int msiof2_ss2_b_mux[] = {
  2590. MSIOF2_SS2_B_MARK,
  2591. };
  2592. static const unsigned int msiof2_txd_b_pins[] = {
  2593. /* TXD */
  2594. RCAR_GP_PIN(0, 7),
  2595. };
  2596. static const unsigned int msiof2_txd_b_mux[] = {
  2597. MSIOF2_TXD_B_MARK,
  2598. };
  2599. static const unsigned int msiof2_rxd_b_pins[] = {
  2600. /* RXD */
  2601. RCAR_GP_PIN(0, 6),
  2602. };
  2603. static const unsigned int msiof2_rxd_b_mux[] = {
  2604. MSIOF2_RXD_B_MARK,
  2605. };
  2606. static const unsigned int msiof2_clk_c_pins[] = {
  2607. /* SCK */
  2608. RCAR_GP_PIN(2, 12),
  2609. };
  2610. static const unsigned int msiof2_clk_c_mux[] = {
  2611. MSIOF2_SCK_C_MARK,
  2612. };
  2613. static const unsigned int msiof2_sync_c_pins[] = {
  2614. /* SYNC */
  2615. RCAR_GP_PIN(2, 11),
  2616. };
  2617. static const unsigned int msiof2_sync_c_mux[] = {
  2618. MSIOF2_SYNC_C_MARK,
  2619. };
  2620. static const unsigned int msiof2_ss1_c_pins[] = {
  2621. /* SS1 */
  2622. RCAR_GP_PIN(2, 10),
  2623. };
  2624. static const unsigned int msiof2_ss1_c_mux[] = {
  2625. MSIOF2_SS1_C_MARK,
  2626. };
  2627. static const unsigned int msiof2_ss2_c_pins[] = {
  2628. /* SS2 */
  2629. RCAR_GP_PIN(2, 9),
  2630. };
  2631. static const unsigned int msiof2_ss2_c_mux[] = {
  2632. MSIOF2_SS2_C_MARK,
  2633. };
  2634. static const unsigned int msiof2_txd_c_pins[] = {
  2635. /* TXD */
  2636. RCAR_GP_PIN(2, 14),
  2637. };
  2638. static const unsigned int msiof2_txd_c_mux[] = {
  2639. MSIOF2_TXD_C_MARK,
  2640. };
  2641. static const unsigned int msiof2_rxd_c_pins[] = {
  2642. /* RXD */
  2643. RCAR_GP_PIN(2, 13),
  2644. };
  2645. static const unsigned int msiof2_rxd_c_mux[] = {
  2646. MSIOF2_RXD_C_MARK,
  2647. };
  2648. static const unsigned int msiof2_clk_d_pins[] = {
  2649. /* SCK */
  2650. RCAR_GP_PIN(0, 8),
  2651. };
  2652. static const unsigned int msiof2_clk_d_mux[] = {
  2653. MSIOF2_SCK_D_MARK,
  2654. };
  2655. static const unsigned int msiof2_sync_d_pins[] = {
  2656. /* SYNC */
  2657. RCAR_GP_PIN(0, 9),
  2658. };
  2659. static const unsigned int msiof2_sync_d_mux[] = {
  2660. MSIOF2_SYNC_D_MARK,
  2661. };
  2662. static const unsigned int msiof2_ss1_d_pins[] = {
  2663. /* SS1 */
  2664. RCAR_GP_PIN(0, 12),
  2665. };
  2666. static const unsigned int msiof2_ss1_d_mux[] = {
  2667. MSIOF2_SS1_D_MARK,
  2668. };
  2669. static const unsigned int msiof2_ss2_d_pins[] = {
  2670. /* SS2 */
  2671. RCAR_GP_PIN(0, 13),
  2672. };
  2673. static const unsigned int msiof2_ss2_d_mux[] = {
  2674. MSIOF2_SS2_D_MARK,
  2675. };
  2676. static const unsigned int msiof2_txd_d_pins[] = {
  2677. /* TXD */
  2678. RCAR_GP_PIN(0, 11),
  2679. };
  2680. static const unsigned int msiof2_txd_d_mux[] = {
  2681. MSIOF2_TXD_D_MARK,
  2682. };
  2683. static const unsigned int msiof2_rxd_d_pins[] = {
  2684. /* RXD */
  2685. RCAR_GP_PIN(0, 10),
  2686. };
  2687. static const unsigned int msiof2_rxd_d_mux[] = {
  2688. MSIOF2_RXD_D_MARK,
  2689. };
  2690. /* - MSIOF3 ----------------------------------------------------------------- */
  2691. static const unsigned int msiof3_clk_a_pins[] = {
  2692. /* SCK */
  2693. RCAR_GP_PIN(0, 0),
  2694. };
  2695. static const unsigned int msiof3_clk_a_mux[] = {
  2696. MSIOF3_SCK_A_MARK,
  2697. };
  2698. static const unsigned int msiof3_sync_a_pins[] = {
  2699. /* SYNC */
  2700. RCAR_GP_PIN(0, 1),
  2701. };
  2702. static const unsigned int msiof3_sync_a_mux[] = {
  2703. MSIOF3_SYNC_A_MARK,
  2704. };
  2705. static const unsigned int msiof3_ss1_a_pins[] = {
  2706. /* SS1 */
  2707. RCAR_GP_PIN(0, 14),
  2708. };
  2709. static const unsigned int msiof3_ss1_a_mux[] = {
  2710. MSIOF3_SS1_A_MARK,
  2711. };
  2712. static const unsigned int msiof3_ss2_a_pins[] = {
  2713. /* SS2 */
  2714. RCAR_GP_PIN(0, 15),
  2715. };
  2716. static const unsigned int msiof3_ss2_a_mux[] = {
  2717. MSIOF3_SS2_A_MARK,
  2718. };
  2719. static const unsigned int msiof3_txd_a_pins[] = {
  2720. /* TXD */
  2721. RCAR_GP_PIN(0, 3),
  2722. };
  2723. static const unsigned int msiof3_txd_a_mux[] = {
  2724. MSIOF3_TXD_A_MARK,
  2725. };
  2726. static const unsigned int msiof3_rxd_a_pins[] = {
  2727. /* RXD */
  2728. RCAR_GP_PIN(0, 2),
  2729. };
  2730. static const unsigned int msiof3_rxd_a_mux[] = {
  2731. MSIOF3_RXD_A_MARK,
  2732. };
  2733. static const unsigned int msiof3_clk_b_pins[] = {
  2734. /* SCK */
  2735. RCAR_GP_PIN(1, 2),
  2736. };
  2737. static const unsigned int msiof3_clk_b_mux[] = {
  2738. MSIOF3_SCK_B_MARK,
  2739. };
  2740. static const unsigned int msiof3_sync_b_pins[] = {
  2741. /* SYNC */
  2742. RCAR_GP_PIN(1, 0),
  2743. };
  2744. static const unsigned int msiof3_sync_b_mux[] = {
  2745. MSIOF3_SYNC_B_MARK,
  2746. };
  2747. static const unsigned int msiof3_ss1_b_pins[] = {
  2748. /* SS1 */
  2749. RCAR_GP_PIN(1, 4),
  2750. };
  2751. static const unsigned int msiof3_ss1_b_mux[] = {
  2752. MSIOF3_SS1_B_MARK,
  2753. };
  2754. static const unsigned int msiof3_ss2_b_pins[] = {
  2755. /* SS2 */
  2756. RCAR_GP_PIN(1, 5),
  2757. };
  2758. static const unsigned int msiof3_ss2_b_mux[] = {
  2759. MSIOF3_SS2_B_MARK,
  2760. };
  2761. static const unsigned int msiof3_txd_b_pins[] = {
  2762. /* TXD */
  2763. RCAR_GP_PIN(1, 1),
  2764. };
  2765. static const unsigned int msiof3_txd_b_mux[] = {
  2766. MSIOF3_TXD_B_MARK,
  2767. };
  2768. static const unsigned int msiof3_rxd_b_pins[] = {
  2769. /* RXD */
  2770. RCAR_GP_PIN(1, 3),
  2771. };
  2772. static const unsigned int msiof3_rxd_b_mux[] = {
  2773. MSIOF3_RXD_B_MARK,
  2774. };
  2775. static const unsigned int msiof3_clk_c_pins[] = {
  2776. /* SCK */
  2777. RCAR_GP_PIN(1, 12),
  2778. };
  2779. static const unsigned int msiof3_clk_c_mux[] = {
  2780. MSIOF3_SCK_C_MARK,
  2781. };
  2782. static const unsigned int msiof3_sync_c_pins[] = {
  2783. /* SYNC */
  2784. RCAR_GP_PIN(1, 13),
  2785. };
  2786. static const unsigned int msiof3_sync_c_mux[] = {
  2787. MSIOF3_SYNC_C_MARK,
  2788. };
  2789. static const unsigned int msiof3_txd_c_pins[] = {
  2790. /* TXD */
  2791. RCAR_GP_PIN(1, 15),
  2792. };
  2793. static const unsigned int msiof3_txd_c_mux[] = {
  2794. MSIOF3_TXD_C_MARK,
  2795. };
  2796. static const unsigned int msiof3_rxd_c_pins[] = {
  2797. /* RXD */
  2798. RCAR_GP_PIN(1, 14),
  2799. };
  2800. static const unsigned int msiof3_rxd_c_mux[] = {
  2801. MSIOF3_RXD_C_MARK,
  2802. };
  2803. static const unsigned int msiof3_clk_d_pins[] = {
  2804. /* SCK */
  2805. RCAR_GP_PIN(1, 22),
  2806. };
  2807. static const unsigned int msiof3_clk_d_mux[] = {
  2808. MSIOF3_SCK_D_MARK,
  2809. };
  2810. static const unsigned int msiof3_sync_d_pins[] = {
  2811. /* SYNC */
  2812. RCAR_GP_PIN(1, 23),
  2813. };
  2814. static const unsigned int msiof3_sync_d_mux[] = {
  2815. MSIOF3_SYNC_D_MARK,
  2816. };
  2817. static const unsigned int msiof3_ss1_d_pins[] = {
  2818. /* SS1 */
  2819. RCAR_GP_PIN(1, 26),
  2820. };
  2821. static const unsigned int msiof3_ss1_d_mux[] = {
  2822. MSIOF3_SS1_D_MARK,
  2823. };
  2824. static const unsigned int msiof3_txd_d_pins[] = {
  2825. /* TXD */
  2826. RCAR_GP_PIN(1, 25),
  2827. };
  2828. static const unsigned int msiof3_txd_d_mux[] = {
  2829. MSIOF3_TXD_D_MARK,
  2830. };
  2831. static const unsigned int msiof3_rxd_d_pins[] = {
  2832. /* RXD */
  2833. RCAR_GP_PIN(1, 24),
  2834. };
  2835. static const unsigned int msiof3_rxd_d_mux[] = {
  2836. MSIOF3_RXD_D_MARK,
  2837. };
  2838. /* - PWM0 --------------------------------------------------------------------*/
  2839. static const unsigned int pwm0_pins[] = {
  2840. /* PWM */
  2841. RCAR_GP_PIN(2, 6),
  2842. };
  2843. static const unsigned int pwm0_mux[] = {
  2844. PWM0_MARK,
  2845. };
  2846. /* - PWM1 --------------------------------------------------------------------*/
  2847. static const unsigned int pwm1_a_pins[] = {
  2848. /* PWM */
  2849. RCAR_GP_PIN(2, 7),
  2850. };
  2851. static const unsigned int pwm1_a_mux[] = {
  2852. PWM1_A_MARK,
  2853. };
  2854. static const unsigned int pwm1_b_pins[] = {
  2855. /* PWM */
  2856. RCAR_GP_PIN(1, 8),
  2857. };
  2858. static const unsigned int pwm1_b_mux[] = {
  2859. PWM1_B_MARK,
  2860. };
  2861. /* - PWM2 --------------------------------------------------------------------*/
  2862. static const unsigned int pwm2_a_pins[] = {
  2863. /* PWM */
  2864. RCAR_GP_PIN(2, 8),
  2865. };
  2866. static const unsigned int pwm2_a_mux[] = {
  2867. PWM2_A_MARK,
  2868. };
  2869. static const unsigned int pwm2_b_pins[] = {
  2870. /* PWM */
  2871. RCAR_GP_PIN(1, 11),
  2872. };
  2873. static const unsigned int pwm2_b_mux[] = {
  2874. PWM2_B_MARK,
  2875. };
  2876. /* - PWM3 --------------------------------------------------------------------*/
  2877. static const unsigned int pwm3_a_pins[] = {
  2878. /* PWM */
  2879. RCAR_GP_PIN(1, 0),
  2880. };
  2881. static const unsigned int pwm3_a_mux[] = {
  2882. PWM3_A_MARK,
  2883. };
  2884. static const unsigned int pwm3_b_pins[] = {
  2885. /* PWM */
  2886. RCAR_GP_PIN(2, 2),
  2887. };
  2888. static const unsigned int pwm3_b_mux[] = {
  2889. PWM3_B_MARK,
  2890. };
  2891. /* - PWM4 --------------------------------------------------------------------*/
  2892. static const unsigned int pwm4_a_pins[] = {
  2893. /* PWM */
  2894. RCAR_GP_PIN(1, 1),
  2895. };
  2896. static const unsigned int pwm4_a_mux[] = {
  2897. PWM4_A_MARK,
  2898. };
  2899. static const unsigned int pwm4_b_pins[] = {
  2900. /* PWM */
  2901. RCAR_GP_PIN(2, 3),
  2902. };
  2903. static const unsigned int pwm4_b_mux[] = {
  2904. PWM4_B_MARK,
  2905. };
  2906. /* - PWM5 --------------------------------------------------------------------*/
  2907. static const unsigned int pwm5_a_pins[] = {
  2908. /* PWM */
  2909. RCAR_GP_PIN(1, 2),
  2910. };
  2911. static const unsigned int pwm5_a_mux[] = {
  2912. PWM5_A_MARK,
  2913. };
  2914. static const unsigned int pwm5_b_pins[] = {
  2915. /* PWM */
  2916. RCAR_GP_PIN(2, 4),
  2917. };
  2918. static const unsigned int pwm5_b_mux[] = {
  2919. PWM5_B_MARK,
  2920. };
  2921. /* - PWM6 --------------------------------------------------------------------*/
  2922. static const unsigned int pwm6_a_pins[] = {
  2923. /* PWM */
  2924. RCAR_GP_PIN(1, 3),
  2925. };
  2926. static const unsigned int pwm6_a_mux[] = {
  2927. PWM6_A_MARK,
  2928. };
  2929. static const unsigned int pwm6_b_pins[] = {
  2930. /* PWM */
  2931. RCAR_GP_PIN(2, 5),
  2932. };
  2933. static const unsigned int pwm6_b_mux[] = {
  2934. PWM6_B_MARK,
  2935. };
  2936. /* - QSPI0 ------------------------------------------------------------------ */
  2937. static const unsigned int qspi0_ctrl_pins[] = {
  2938. /* QSPI0_SPCLK, QSPI0_SSL */
  2939. PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
  2940. };
  2941. static const unsigned int qspi0_ctrl_mux[] = {
  2942. QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
  2943. };
  2944. static const unsigned int qspi0_data_pins[] = {
  2945. /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
  2946. PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
  2947. };
  2948. static const unsigned int qspi0_data_mux[] = {
  2949. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  2950. QSPI0_IO2_MARK, QSPI0_IO3_MARK,
  2951. };
  2952. /* - QSPI1 ------------------------------------------------------------------ */
  2953. static const unsigned int qspi1_ctrl_pins[] = {
  2954. /* QSPI1_SPCLK, QSPI1_SSL */
  2955. PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
  2956. };
  2957. static const unsigned int qspi1_ctrl_mux[] = {
  2958. QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
  2959. };
  2960. static const unsigned int qspi1_data_pins[] = {
  2961. /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
  2962. PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
  2963. };
  2964. static const unsigned int qspi1_data_mux[] = {
  2965. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  2966. QSPI1_IO2_MARK, QSPI1_IO3_MARK,
  2967. };
  2968. /* - SATA --------------------------------------------------------------------*/
  2969. static const unsigned int sata0_devslp_a_pins[] = {
  2970. /* DEVSLP */
  2971. RCAR_GP_PIN(6, 16),
  2972. };
  2973. static const unsigned int sata0_devslp_a_mux[] = {
  2974. SATA_DEVSLP_A_MARK,
  2975. };
  2976. static const unsigned int sata0_devslp_b_pins[] = {
  2977. /* DEVSLP */
  2978. RCAR_GP_PIN(4, 6),
  2979. };
  2980. static const unsigned int sata0_devslp_b_mux[] = {
  2981. SATA_DEVSLP_B_MARK,
  2982. };
  2983. /* - SCIF0 ------------------------------------------------------------------ */
  2984. static const unsigned int scif0_data_pins[] = {
  2985. /* RX, TX */
  2986. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  2987. };
  2988. static const unsigned int scif0_data_mux[] = {
  2989. RX0_MARK, TX0_MARK,
  2990. };
  2991. static const unsigned int scif0_clk_pins[] = {
  2992. /* SCK */
  2993. RCAR_GP_PIN(5, 0),
  2994. };
  2995. static const unsigned int scif0_clk_mux[] = {
  2996. SCK0_MARK,
  2997. };
  2998. static const unsigned int scif0_ctrl_pins[] = {
  2999. /* RTS, CTS */
  3000. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
  3001. };
  3002. static const unsigned int scif0_ctrl_mux[] = {
  3003. RTS0_N_MARK, CTS0_N_MARK,
  3004. };
  3005. /* - SCIF1 ------------------------------------------------------------------ */
  3006. static const unsigned int scif1_data_a_pins[] = {
  3007. /* RX, TX */
  3008. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  3009. };
  3010. static const unsigned int scif1_data_a_mux[] = {
  3011. RX1_A_MARK, TX1_A_MARK,
  3012. };
  3013. static const unsigned int scif1_clk_pins[] = {
  3014. /* SCK */
  3015. RCAR_GP_PIN(6, 21),
  3016. };
  3017. static const unsigned int scif1_clk_mux[] = {
  3018. SCK1_MARK,
  3019. };
  3020. static const unsigned int scif1_ctrl_pins[] = {
  3021. /* RTS, CTS */
  3022. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
  3023. };
  3024. static const unsigned int scif1_ctrl_mux[] = {
  3025. RTS1_N_MARK, CTS1_N_MARK,
  3026. };
  3027. static const unsigned int scif1_data_b_pins[] = {
  3028. /* RX, TX */
  3029. RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
  3030. };
  3031. static const unsigned int scif1_data_b_mux[] = {
  3032. RX1_B_MARK, TX1_B_MARK,
  3033. };
  3034. /* - SCIF2 ------------------------------------------------------------------ */
  3035. static const unsigned int scif2_data_a_pins[] = {
  3036. /* RX, TX */
  3037. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
  3038. };
  3039. static const unsigned int scif2_data_a_mux[] = {
  3040. RX2_A_MARK, TX2_A_MARK,
  3041. };
  3042. static const unsigned int scif2_clk_pins[] = {
  3043. /* SCK */
  3044. RCAR_GP_PIN(5, 9),
  3045. };
  3046. static const unsigned int scif2_clk_mux[] = {
  3047. SCK2_MARK,
  3048. };
  3049. static const unsigned int scif2_data_b_pins[] = {
  3050. /* RX, TX */
  3051. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  3052. };
  3053. static const unsigned int scif2_data_b_mux[] = {
  3054. RX2_B_MARK, TX2_B_MARK,
  3055. };
  3056. /* - SCIF3 ------------------------------------------------------------------ */
  3057. static const unsigned int scif3_data_a_pins[] = {
  3058. /* RX, TX */
  3059. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  3060. };
  3061. static const unsigned int scif3_data_a_mux[] = {
  3062. RX3_A_MARK, TX3_A_MARK,
  3063. };
  3064. static const unsigned int scif3_clk_pins[] = {
  3065. /* SCK */
  3066. RCAR_GP_PIN(1, 22),
  3067. };
  3068. static const unsigned int scif3_clk_mux[] = {
  3069. SCK3_MARK,
  3070. };
  3071. static const unsigned int scif3_ctrl_pins[] = {
  3072. /* RTS, CTS */
  3073. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  3074. };
  3075. static const unsigned int scif3_ctrl_mux[] = {
  3076. RTS3_N_MARK, CTS3_N_MARK,
  3077. };
  3078. static const unsigned int scif3_data_b_pins[] = {
  3079. /* RX, TX */
  3080. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  3081. };
  3082. static const unsigned int scif3_data_b_mux[] = {
  3083. RX3_B_MARK, TX3_B_MARK,
  3084. };
  3085. /* - SCIF4 ------------------------------------------------------------------ */
  3086. static const unsigned int scif4_data_a_pins[] = {
  3087. /* RX, TX */
  3088. RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
  3089. };
  3090. static const unsigned int scif4_data_a_mux[] = {
  3091. RX4_A_MARK, TX4_A_MARK,
  3092. };
  3093. static const unsigned int scif4_clk_a_pins[] = {
  3094. /* SCK */
  3095. RCAR_GP_PIN(2, 10),
  3096. };
  3097. static const unsigned int scif4_clk_a_mux[] = {
  3098. SCK4_A_MARK,
  3099. };
  3100. static const unsigned int scif4_ctrl_a_pins[] = {
  3101. /* RTS, CTS */
  3102. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  3103. };
  3104. static const unsigned int scif4_ctrl_a_mux[] = {
  3105. RTS4_N_A_MARK, CTS4_N_A_MARK,
  3106. };
  3107. static const unsigned int scif4_data_b_pins[] = {
  3108. /* RX, TX */
  3109. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3110. };
  3111. static const unsigned int scif4_data_b_mux[] = {
  3112. RX4_B_MARK, TX4_B_MARK,
  3113. };
  3114. static const unsigned int scif4_clk_b_pins[] = {
  3115. /* SCK */
  3116. RCAR_GP_PIN(1, 5),
  3117. };
  3118. static const unsigned int scif4_clk_b_mux[] = {
  3119. SCK4_B_MARK,
  3120. };
  3121. static const unsigned int scif4_ctrl_b_pins[] = {
  3122. /* RTS, CTS */
  3123. RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
  3124. };
  3125. static const unsigned int scif4_ctrl_b_mux[] = {
  3126. RTS4_N_B_MARK, CTS4_N_B_MARK,
  3127. };
  3128. static const unsigned int scif4_data_c_pins[] = {
  3129. /* RX, TX */
  3130. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3131. };
  3132. static const unsigned int scif4_data_c_mux[] = {
  3133. RX4_C_MARK, TX4_C_MARK,
  3134. };
  3135. static const unsigned int scif4_clk_c_pins[] = {
  3136. /* SCK */
  3137. RCAR_GP_PIN(0, 8),
  3138. };
  3139. static const unsigned int scif4_clk_c_mux[] = {
  3140. SCK4_C_MARK,
  3141. };
  3142. static const unsigned int scif4_ctrl_c_pins[] = {
  3143. /* RTS, CTS */
  3144. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  3145. };
  3146. static const unsigned int scif4_ctrl_c_mux[] = {
  3147. RTS4_N_C_MARK, CTS4_N_C_MARK,
  3148. };
  3149. /* - SCIF5 ------------------------------------------------------------------ */
  3150. static const unsigned int scif5_data_pins[] = {
  3151. /* RX, TX */
  3152. RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
  3153. };
  3154. static const unsigned int scif5_data_mux[] = {
  3155. RX5_MARK, TX5_MARK,
  3156. };
  3157. static const unsigned int scif5_clk_pins[] = {
  3158. /* SCK */
  3159. RCAR_GP_PIN(6, 21),
  3160. };
  3161. static const unsigned int scif5_clk_mux[] = {
  3162. SCK5_MARK,
  3163. };
  3164. /* - SCIF Clock ------------------------------------------------------------- */
  3165. static const unsigned int scif_clk_a_pins[] = {
  3166. /* SCIF_CLK */
  3167. RCAR_GP_PIN(6, 23),
  3168. };
  3169. static const unsigned int scif_clk_a_mux[] = {
  3170. SCIF_CLK_A_MARK,
  3171. };
  3172. static const unsigned int scif_clk_b_pins[] = {
  3173. /* SCIF_CLK */
  3174. RCAR_GP_PIN(5, 9),
  3175. };
  3176. static const unsigned int scif_clk_b_mux[] = {
  3177. SCIF_CLK_B_MARK,
  3178. };
  3179. /* - SDHI0 ------------------------------------------------------------------ */
  3180. static const unsigned int sdhi0_data_pins[] = {
  3181. /* D[0:3] */
  3182. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
  3183. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
  3184. };
  3185. static const unsigned int sdhi0_data_mux[] = {
  3186. SD0_DAT0_MARK, SD0_DAT1_MARK,
  3187. SD0_DAT2_MARK, SD0_DAT3_MARK,
  3188. };
  3189. static const unsigned int sdhi0_ctrl_pins[] = {
  3190. /* CLK, CMD */
  3191. RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
  3192. };
  3193. static const unsigned int sdhi0_ctrl_mux[] = {
  3194. SD0_CLK_MARK, SD0_CMD_MARK,
  3195. };
  3196. static const unsigned int sdhi0_cd_pins[] = {
  3197. /* CD */
  3198. RCAR_GP_PIN(3, 12),
  3199. };
  3200. static const unsigned int sdhi0_cd_mux[] = {
  3201. SD0_CD_MARK,
  3202. };
  3203. static const unsigned int sdhi0_wp_pins[] = {
  3204. /* WP */
  3205. RCAR_GP_PIN(3, 13),
  3206. };
  3207. static const unsigned int sdhi0_wp_mux[] = {
  3208. SD0_WP_MARK,
  3209. };
  3210. /* - SDHI1 ------------------------------------------------------------------ */
  3211. static const unsigned int sdhi1_data_pins[] = {
  3212. /* D[0:3] */
  3213. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  3214. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  3215. };
  3216. static const unsigned int sdhi1_data_mux[] = {
  3217. SD1_DAT0_MARK, SD1_DAT1_MARK,
  3218. SD1_DAT2_MARK, SD1_DAT3_MARK,
  3219. };
  3220. static const unsigned int sdhi1_ctrl_pins[] = {
  3221. /* CLK, CMD */
  3222. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  3223. };
  3224. static const unsigned int sdhi1_ctrl_mux[] = {
  3225. SD1_CLK_MARK, SD1_CMD_MARK,
  3226. };
  3227. static const unsigned int sdhi1_cd_pins[] = {
  3228. /* CD */
  3229. RCAR_GP_PIN(3, 14),
  3230. };
  3231. static const unsigned int sdhi1_cd_mux[] = {
  3232. SD1_CD_MARK,
  3233. };
  3234. static const unsigned int sdhi1_wp_pins[] = {
  3235. /* WP */
  3236. RCAR_GP_PIN(3, 15),
  3237. };
  3238. static const unsigned int sdhi1_wp_mux[] = {
  3239. SD1_WP_MARK,
  3240. };
  3241. /* - SDHI2 ------------------------------------------------------------------ */
  3242. static const unsigned int sdhi2_data_pins[] = {
  3243. /* D[0:7] */
  3244. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  3245. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  3246. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  3247. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  3248. };
  3249. static const unsigned int sdhi2_data_mux[] = {
  3250. SD2_DAT0_MARK, SD2_DAT1_MARK,
  3251. SD2_DAT2_MARK, SD2_DAT3_MARK,
  3252. SD2_DAT4_MARK, SD2_DAT5_MARK,
  3253. SD2_DAT6_MARK, SD2_DAT7_MARK,
  3254. };
  3255. static const unsigned int sdhi2_ctrl_pins[] = {
  3256. /* CLK, CMD */
  3257. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  3258. };
  3259. static const unsigned int sdhi2_ctrl_mux[] = {
  3260. SD2_CLK_MARK, SD2_CMD_MARK,
  3261. };
  3262. static const unsigned int sdhi2_cd_a_pins[] = {
  3263. /* CD */
  3264. RCAR_GP_PIN(4, 13),
  3265. };
  3266. static const unsigned int sdhi2_cd_a_mux[] = {
  3267. SD2_CD_A_MARK,
  3268. };
  3269. static const unsigned int sdhi2_cd_b_pins[] = {
  3270. /* CD */
  3271. RCAR_GP_PIN(5, 10),
  3272. };
  3273. static const unsigned int sdhi2_cd_b_mux[] = {
  3274. SD2_CD_B_MARK,
  3275. };
  3276. static const unsigned int sdhi2_wp_a_pins[] = {
  3277. /* WP */
  3278. RCAR_GP_PIN(4, 14),
  3279. };
  3280. static const unsigned int sdhi2_wp_a_mux[] = {
  3281. SD2_WP_A_MARK,
  3282. };
  3283. static const unsigned int sdhi2_wp_b_pins[] = {
  3284. /* WP */
  3285. RCAR_GP_PIN(5, 11),
  3286. };
  3287. static const unsigned int sdhi2_wp_b_mux[] = {
  3288. SD2_WP_B_MARK,
  3289. };
  3290. static const unsigned int sdhi2_ds_pins[] = {
  3291. /* DS */
  3292. RCAR_GP_PIN(4, 6),
  3293. };
  3294. static const unsigned int sdhi2_ds_mux[] = {
  3295. SD2_DS_MARK,
  3296. };
  3297. /* - SDHI3 ------------------------------------------------------------------ */
  3298. static const unsigned int sdhi3_data_pins[] = {
  3299. /* D[0:7] */
  3300. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
  3301. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3302. RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
  3303. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
  3304. };
  3305. static const unsigned int sdhi3_data_mux[] = {
  3306. SD3_DAT0_MARK, SD3_DAT1_MARK,
  3307. SD3_DAT2_MARK, SD3_DAT3_MARK,
  3308. SD3_DAT4_MARK, SD3_DAT5_MARK,
  3309. SD3_DAT6_MARK, SD3_DAT7_MARK,
  3310. };
  3311. static const unsigned int sdhi3_ctrl_pins[] = {
  3312. /* CLK, CMD */
  3313. RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
  3314. };
  3315. static const unsigned int sdhi3_ctrl_mux[] = {
  3316. SD3_CLK_MARK, SD3_CMD_MARK,
  3317. };
  3318. static const unsigned int sdhi3_cd_pins[] = {
  3319. /* CD */
  3320. RCAR_GP_PIN(4, 15),
  3321. };
  3322. static const unsigned int sdhi3_cd_mux[] = {
  3323. SD3_CD_MARK,
  3324. };
  3325. static const unsigned int sdhi3_wp_pins[] = {
  3326. /* WP */
  3327. RCAR_GP_PIN(4, 16),
  3328. };
  3329. static const unsigned int sdhi3_wp_mux[] = {
  3330. SD3_WP_MARK,
  3331. };
  3332. static const unsigned int sdhi3_ds_pins[] = {
  3333. /* DS */
  3334. RCAR_GP_PIN(4, 17),
  3335. };
  3336. static const unsigned int sdhi3_ds_mux[] = {
  3337. SD3_DS_MARK,
  3338. };
  3339. /* - SSI -------------------------------------------------------------------- */
  3340. static const unsigned int ssi0_data_pins[] = {
  3341. /* SDATA */
  3342. RCAR_GP_PIN(6, 2),
  3343. };
  3344. static const unsigned int ssi0_data_mux[] = {
  3345. SSI_SDATA0_MARK,
  3346. };
  3347. static const unsigned int ssi01239_ctrl_pins[] = {
  3348. /* SCK, WS */
  3349. RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
  3350. };
  3351. static const unsigned int ssi01239_ctrl_mux[] = {
  3352. SSI_SCK01239_MARK, SSI_WS01239_MARK,
  3353. };
  3354. static const unsigned int ssi1_data_a_pins[] = {
  3355. /* SDATA */
  3356. RCAR_GP_PIN(6, 3),
  3357. };
  3358. static const unsigned int ssi1_data_a_mux[] = {
  3359. SSI_SDATA1_A_MARK,
  3360. };
  3361. static const unsigned int ssi1_data_b_pins[] = {
  3362. /* SDATA */
  3363. RCAR_GP_PIN(5, 12),
  3364. };
  3365. static const unsigned int ssi1_data_b_mux[] = {
  3366. SSI_SDATA1_B_MARK,
  3367. };
  3368. static const unsigned int ssi1_ctrl_a_pins[] = {
  3369. /* SCK, WS */
  3370. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  3371. };
  3372. static const unsigned int ssi1_ctrl_a_mux[] = {
  3373. SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
  3374. };
  3375. static const unsigned int ssi1_ctrl_b_pins[] = {
  3376. /* SCK, WS */
  3377. RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
  3378. };
  3379. static const unsigned int ssi1_ctrl_b_mux[] = {
  3380. SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
  3381. };
  3382. static const unsigned int ssi2_data_a_pins[] = {
  3383. /* SDATA */
  3384. RCAR_GP_PIN(6, 4),
  3385. };
  3386. static const unsigned int ssi2_data_a_mux[] = {
  3387. SSI_SDATA2_A_MARK,
  3388. };
  3389. static const unsigned int ssi2_data_b_pins[] = {
  3390. /* SDATA */
  3391. RCAR_GP_PIN(5, 13),
  3392. };
  3393. static const unsigned int ssi2_data_b_mux[] = {
  3394. SSI_SDATA2_B_MARK,
  3395. };
  3396. static const unsigned int ssi2_ctrl_a_pins[] = {
  3397. /* SCK, WS */
  3398. RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
  3399. };
  3400. static const unsigned int ssi2_ctrl_a_mux[] = {
  3401. SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
  3402. };
  3403. static const unsigned int ssi2_ctrl_b_pins[] = {
  3404. /* SCK, WS */
  3405. RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
  3406. };
  3407. static const unsigned int ssi2_ctrl_b_mux[] = {
  3408. SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
  3409. };
  3410. static const unsigned int ssi3_data_pins[] = {
  3411. /* SDATA */
  3412. RCAR_GP_PIN(6, 7),
  3413. };
  3414. static const unsigned int ssi3_data_mux[] = {
  3415. SSI_SDATA3_MARK,
  3416. };
  3417. static const unsigned int ssi349_ctrl_pins[] = {
  3418. /* SCK, WS */
  3419. RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
  3420. };
  3421. static const unsigned int ssi349_ctrl_mux[] = {
  3422. SSI_SCK349_MARK, SSI_WS349_MARK,
  3423. };
  3424. static const unsigned int ssi4_data_pins[] = {
  3425. /* SDATA */
  3426. RCAR_GP_PIN(6, 10),
  3427. };
  3428. static const unsigned int ssi4_data_mux[] = {
  3429. SSI_SDATA4_MARK,
  3430. };
  3431. static const unsigned int ssi4_ctrl_pins[] = {
  3432. /* SCK, WS */
  3433. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  3434. };
  3435. static const unsigned int ssi4_ctrl_mux[] = {
  3436. SSI_SCK4_MARK, SSI_WS4_MARK,
  3437. };
  3438. static const unsigned int ssi5_data_pins[] = {
  3439. /* SDATA */
  3440. RCAR_GP_PIN(6, 13),
  3441. };
  3442. static const unsigned int ssi5_data_mux[] = {
  3443. SSI_SDATA5_MARK,
  3444. };
  3445. static const unsigned int ssi5_ctrl_pins[] = {
  3446. /* SCK, WS */
  3447. RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
  3448. };
  3449. static const unsigned int ssi5_ctrl_mux[] = {
  3450. SSI_SCK5_MARK, SSI_WS5_MARK,
  3451. };
  3452. static const unsigned int ssi6_data_pins[] = {
  3453. /* SDATA */
  3454. RCAR_GP_PIN(6, 16),
  3455. };
  3456. static const unsigned int ssi6_data_mux[] = {
  3457. SSI_SDATA6_MARK,
  3458. };
  3459. static const unsigned int ssi6_ctrl_pins[] = {
  3460. /* SCK, WS */
  3461. RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
  3462. };
  3463. static const unsigned int ssi6_ctrl_mux[] = {
  3464. SSI_SCK6_MARK, SSI_WS6_MARK,
  3465. };
  3466. static const unsigned int ssi7_data_pins[] = {
  3467. /* SDATA */
  3468. RCAR_GP_PIN(6, 19),
  3469. };
  3470. static const unsigned int ssi7_data_mux[] = {
  3471. SSI_SDATA7_MARK,
  3472. };
  3473. static const unsigned int ssi78_ctrl_pins[] = {
  3474. /* SCK, WS */
  3475. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  3476. };
  3477. static const unsigned int ssi78_ctrl_mux[] = {
  3478. SSI_SCK78_MARK, SSI_WS78_MARK,
  3479. };
  3480. static const unsigned int ssi8_data_pins[] = {
  3481. /* SDATA */
  3482. RCAR_GP_PIN(6, 20),
  3483. };
  3484. static const unsigned int ssi8_data_mux[] = {
  3485. SSI_SDATA8_MARK,
  3486. };
  3487. static const unsigned int ssi9_data_a_pins[] = {
  3488. /* SDATA */
  3489. RCAR_GP_PIN(6, 21),
  3490. };
  3491. static const unsigned int ssi9_data_a_mux[] = {
  3492. SSI_SDATA9_A_MARK,
  3493. };
  3494. static const unsigned int ssi9_data_b_pins[] = {
  3495. /* SDATA */
  3496. RCAR_GP_PIN(5, 14),
  3497. };
  3498. static const unsigned int ssi9_data_b_mux[] = {
  3499. SSI_SDATA9_B_MARK,
  3500. };
  3501. static const unsigned int ssi9_ctrl_a_pins[] = {
  3502. /* SCK, WS */
  3503. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  3504. };
  3505. static const unsigned int ssi9_ctrl_a_mux[] = {
  3506. SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
  3507. };
  3508. static const unsigned int ssi9_ctrl_b_pins[] = {
  3509. /* SCK, WS */
  3510. RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
  3511. };
  3512. static const unsigned int ssi9_ctrl_b_mux[] = {
  3513. SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
  3514. };
  3515. /* - TMU -------------------------------------------------------------------- */
  3516. static const unsigned int tmu_tclk1_a_pins[] = {
  3517. /* TCLK */
  3518. RCAR_GP_PIN(6, 23),
  3519. };
  3520. static const unsigned int tmu_tclk1_a_mux[] = {
  3521. TCLK1_A_MARK,
  3522. };
  3523. static const unsigned int tmu_tclk1_b_pins[] = {
  3524. /* TCLK */
  3525. RCAR_GP_PIN(5, 19),
  3526. };
  3527. static const unsigned int tmu_tclk1_b_mux[] = {
  3528. TCLK1_B_MARK,
  3529. };
  3530. static const unsigned int tmu_tclk2_a_pins[] = {
  3531. /* TCLK */
  3532. RCAR_GP_PIN(6, 19),
  3533. };
  3534. static const unsigned int tmu_tclk2_a_mux[] = {
  3535. TCLK2_A_MARK,
  3536. };
  3537. static const unsigned int tmu_tclk2_b_pins[] = {
  3538. /* TCLK */
  3539. RCAR_GP_PIN(6, 28),
  3540. };
  3541. static const unsigned int tmu_tclk2_b_mux[] = {
  3542. TCLK2_B_MARK,
  3543. };
  3544. /* - TPU ------------------------------------------------------------------- */
  3545. static const unsigned int tpu_to0_pins[] = {
  3546. /* TPU0TO0 */
  3547. RCAR_GP_PIN(6, 28),
  3548. };
  3549. static const unsigned int tpu_to0_mux[] = {
  3550. TPU0TO0_MARK,
  3551. };
  3552. static const unsigned int tpu_to1_pins[] = {
  3553. /* TPU0TO1 */
  3554. RCAR_GP_PIN(6, 29),
  3555. };
  3556. static const unsigned int tpu_to1_mux[] = {
  3557. TPU0TO1_MARK,
  3558. };
  3559. static const unsigned int tpu_to2_pins[] = {
  3560. /* TPU0TO2 */
  3561. RCAR_GP_PIN(6, 30),
  3562. };
  3563. static const unsigned int tpu_to2_mux[] = {
  3564. TPU0TO2_MARK,
  3565. };
  3566. static const unsigned int tpu_to3_pins[] = {
  3567. /* TPU0TO3 */
  3568. RCAR_GP_PIN(6, 31),
  3569. };
  3570. static const unsigned int tpu_to3_mux[] = {
  3571. TPU0TO3_MARK,
  3572. };
  3573. /* - USB0 ------------------------------------------------------------------- */
  3574. static const unsigned int usb0_pins[] = {
  3575. /* PWEN, OVC */
  3576. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  3577. };
  3578. static const unsigned int usb0_mux[] = {
  3579. USB0_PWEN_MARK, USB0_OVC_MARK,
  3580. };
  3581. /* - USB1 ------------------------------------------------------------------- */
  3582. static const unsigned int usb1_pins[] = {
  3583. /* PWEN, OVC */
  3584. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  3585. };
  3586. static const unsigned int usb1_mux[] = {
  3587. USB1_PWEN_MARK, USB1_OVC_MARK,
  3588. };
  3589. /* - USB2 ------------------------------------------------------------------- */
  3590. static const unsigned int usb2_pins[] = {
  3591. /* PWEN, OVC */
  3592. RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
  3593. };
  3594. static const unsigned int usb2_mux[] = {
  3595. USB2_PWEN_MARK, USB2_OVC_MARK,
  3596. };
  3597. /* - USB30 ------------------------------------------------------------------ */
  3598. static const unsigned int usb30_pins[] = {
  3599. /* PWEN, OVC */
  3600. RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
  3601. };
  3602. static const unsigned int usb30_mux[] = {
  3603. USB30_PWEN_MARK, USB30_OVC_MARK,
  3604. };
  3605. /* - USB31 ------------------------------------------------------------------ */
  3606. static const unsigned int usb31_pins[] = {
  3607. /* PWEN, OVC */
  3608. RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
  3609. };
  3610. static const unsigned int usb31_mux[] = {
  3611. USB31_PWEN_MARK, USB31_OVC_MARK,
  3612. };
  3613. static const struct sh_pfc_pin_group pinmux_groups[] = {
  3614. SH_PFC_PIN_GROUP(audio_clk_a_a),
  3615. SH_PFC_PIN_GROUP(audio_clk_a_b),
  3616. SH_PFC_PIN_GROUP(audio_clk_a_c),
  3617. SH_PFC_PIN_GROUP(audio_clk_b_a),
  3618. SH_PFC_PIN_GROUP(audio_clk_b_b),
  3619. SH_PFC_PIN_GROUP(audio_clk_c_a),
  3620. SH_PFC_PIN_GROUP(audio_clk_c_b),
  3621. SH_PFC_PIN_GROUP(audio_clkout_a),
  3622. SH_PFC_PIN_GROUP(audio_clkout_b),
  3623. SH_PFC_PIN_GROUP(audio_clkout_c),
  3624. SH_PFC_PIN_GROUP(audio_clkout_d),
  3625. SH_PFC_PIN_GROUP(audio_clkout1_a),
  3626. SH_PFC_PIN_GROUP(audio_clkout1_b),
  3627. SH_PFC_PIN_GROUP(audio_clkout2_a),
  3628. SH_PFC_PIN_GROUP(audio_clkout2_b),
  3629. SH_PFC_PIN_GROUP(audio_clkout3_a),
  3630. SH_PFC_PIN_GROUP(audio_clkout3_b),
  3631. SH_PFC_PIN_GROUP(avb_link),
  3632. SH_PFC_PIN_GROUP(avb_magic),
  3633. SH_PFC_PIN_GROUP(avb_phy_int),
  3634. SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
  3635. SH_PFC_PIN_GROUP(avb_mdio),
  3636. SH_PFC_PIN_GROUP(avb_mii),
  3637. SH_PFC_PIN_GROUP(avb_avtp_pps),
  3638. SH_PFC_PIN_GROUP(avb_avtp_match_a),
  3639. SH_PFC_PIN_GROUP(avb_avtp_capture_a),
  3640. SH_PFC_PIN_GROUP(avb_avtp_match_b),
  3641. SH_PFC_PIN_GROUP(avb_avtp_capture_b),
  3642. SH_PFC_PIN_GROUP(can0_data_a),
  3643. SH_PFC_PIN_GROUP(can0_data_b),
  3644. SH_PFC_PIN_GROUP(can1_data),
  3645. SH_PFC_PIN_GROUP(can_clk),
  3646. SH_PFC_PIN_GROUP(canfd0_data_a),
  3647. SH_PFC_PIN_GROUP(canfd0_data_b),
  3648. SH_PFC_PIN_GROUP(canfd1_data),
  3649. SH_PFC_PIN_GROUP(drif0_ctrl_a),
  3650. SH_PFC_PIN_GROUP(drif0_data0_a),
  3651. SH_PFC_PIN_GROUP(drif0_data1_a),
  3652. SH_PFC_PIN_GROUP(drif0_ctrl_b),
  3653. SH_PFC_PIN_GROUP(drif0_data0_b),
  3654. SH_PFC_PIN_GROUP(drif0_data1_b),
  3655. SH_PFC_PIN_GROUP(drif0_ctrl_c),
  3656. SH_PFC_PIN_GROUP(drif0_data0_c),
  3657. SH_PFC_PIN_GROUP(drif0_data1_c),
  3658. SH_PFC_PIN_GROUP(drif1_ctrl_a),
  3659. SH_PFC_PIN_GROUP(drif1_data0_a),
  3660. SH_PFC_PIN_GROUP(drif1_data1_a),
  3661. SH_PFC_PIN_GROUP(drif1_ctrl_b),
  3662. SH_PFC_PIN_GROUP(drif1_data0_b),
  3663. SH_PFC_PIN_GROUP(drif1_data1_b),
  3664. SH_PFC_PIN_GROUP(drif1_ctrl_c),
  3665. SH_PFC_PIN_GROUP(drif1_data0_c),
  3666. SH_PFC_PIN_GROUP(drif1_data1_c),
  3667. SH_PFC_PIN_GROUP(drif2_ctrl_a),
  3668. SH_PFC_PIN_GROUP(drif2_data0_a),
  3669. SH_PFC_PIN_GROUP(drif2_data1_a),
  3670. SH_PFC_PIN_GROUP(drif2_ctrl_b),
  3671. SH_PFC_PIN_GROUP(drif2_data0_b),
  3672. SH_PFC_PIN_GROUP(drif2_data1_b),
  3673. SH_PFC_PIN_GROUP(drif3_ctrl_a),
  3674. SH_PFC_PIN_GROUP(drif3_data0_a),
  3675. SH_PFC_PIN_GROUP(drif3_data1_a),
  3676. SH_PFC_PIN_GROUP(drif3_ctrl_b),
  3677. SH_PFC_PIN_GROUP(drif3_data0_b),
  3678. SH_PFC_PIN_GROUP(drif3_data1_b),
  3679. SH_PFC_PIN_GROUP(du_rgb666),
  3680. SH_PFC_PIN_GROUP(du_rgb888),
  3681. SH_PFC_PIN_GROUP(du_clk_out_0),
  3682. SH_PFC_PIN_GROUP(du_clk_out_1),
  3683. SH_PFC_PIN_GROUP(du_sync),
  3684. SH_PFC_PIN_GROUP(du_oddf),
  3685. SH_PFC_PIN_GROUP(du_cde),
  3686. SH_PFC_PIN_GROUP(du_disp),
  3687. SH_PFC_PIN_GROUP(hscif0_data),
  3688. SH_PFC_PIN_GROUP(hscif0_clk),
  3689. SH_PFC_PIN_GROUP(hscif0_ctrl),
  3690. SH_PFC_PIN_GROUP(hscif1_data_a),
  3691. SH_PFC_PIN_GROUP(hscif1_clk_a),
  3692. SH_PFC_PIN_GROUP(hscif1_ctrl_a),
  3693. SH_PFC_PIN_GROUP(hscif1_data_b),
  3694. SH_PFC_PIN_GROUP(hscif1_clk_b),
  3695. SH_PFC_PIN_GROUP(hscif1_ctrl_b),
  3696. SH_PFC_PIN_GROUP(hscif2_data_a),
  3697. SH_PFC_PIN_GROUP(hscif2_clk_a),
  3698. SH_PFC_PIN_GROUP(hscif2_ctrl_a),
  3699. SH_PFC_PIN_GROUP(hscif2_data_b),
  3700. SH_PFC_PIN_GROUP(hscif2_clk_b),
  3701. SH_PFC_PIN_GROUP(hscif2_ctrl_b),
  3702. SH_PFC_PIN_GROUP(hscif3_data_a),
  3703. SH_PFC_PIN_GROUP(hscif3_clk),
  3704. SH_PFC_PIN_GROUP(hscif3_ctrl),
  3705. SH_PFC_PIN_GROUP(hscif3_data_b),
  3706. SH_PFC_PIN_GROUP(hscif3_data_c),
  3707. SH_PFC_PIN_GROUP(hscif3_data_d),
  3708. SH_PFC_PIN_GROUP(hscif4_data_a),
  3709. SH_PFC_PIN_GROUP(hscif4_clk),
  3710. SH_PFC_PIN_GROUP(hscif4_ctrl),
  3711. SH_PFC_PIN_GROUP(hscif4_data_b),
  3712. SH_PFC_PIN_GROUP(i2c0),
  3713. SH_PFC_PIN_GROUP(i2c1_a),
  3714. SH_PFC_PIN_GROUP(i2c1_b),
  3715. SH_PFC_PIN_GROUP(i2c2_a),
  3716. SH_PFC_PIN_GROUP(i2c2_b),
  3717. SH_PFC_PIN_GROUP(i2c3),
  3718. SH_PFC_PIN_GROUP(i2c5),
  3719. SH_PFC_PIN_GROUP(i2c6_a),
  3720. SH_PFC_PIN_GROUP(i2c6_b),
  3721. SH_PFC_PIN_GROUP(i2c6_c),
  3722. SH_PFC_PIN_GROUP(intc_ex_irq0),
  3723. SH_PFC_PIN_GROUP(intc_ex_irq1),
  3724. SH_PFC_PIN_GROUP(intc_ex_irq2),
  3725. SH_PFC_PIN_GROUP(intc_ex_irq3),
  3726. SH_PFC_PIN_GROUP(intc_ex_irq4),
  3727. SH_PFC_PIN_GROUP(intc_ex_irq5),
  3728. SH_PFC_PIN_GROUP(mlb_3pin),
  3729. SH_PFC_PIN_GROUP(msiof0_clk),
  3730. SH_PFC_PIN_GROUP(msiof0_sync),
  3731. SH_PFC_PIN_GROUP(msiof0_ss1),
  3732. SH_PFC_PIN_GROUP(msiof0_ss2),
  3733. SH_PFC_PIN_GROUP(msiof0_txd),
  3734. SH_PFC_PIN_GROUP(msiof0_rxd),
  3735. SH_PFC_PIN_GROUP(msiof1_clk_a),
  3736. SH_PFC_PIN_GROUP(msiof1_sync_a),
  3737. SH_PFC_PIN_GROUP(msiof1_ss1_a),
  3738. SH_PFC_PIN_GROUP(msiof1_ss2_a),
  3739. SH_PFC_PIN_GROUP(msiof1_txd_a),
  3740. SH_PFC_PIN_GROUP(msiof1_rxd_a),
  3741. SH_PFC_PIN_GROUP(msiof1_clk_b),
  3742. SH_PFC_PIN_GROUP(msiof1_sync_b),
  3743. SH_PFC_PIN_GROUP(msiof1_ss1_b),
  3744. SH_PFC_PIN_GROUP(msiof1_ss2_b),
  3745. SH_PFC_PIN_GROUP(msiof1_txd_b),
  3746. SH_PFC_PIN_GROUP(msiof1_rxd_b),
  3747. SH_PFC_PIN_GROUP(msiof1_clk_c),
  3748. SH_PFC_PIN_GROUP(msiof1_sync_c),
  3749. SH_PFC_PIN_GROUP(msiof1_ss1_c),
  3750. SH_PFC_PIN_GROUP(msiof1_ss2_c),
  3751. SH_PFC_PIN_GROUP(msiof1_txd_c),
  3752. SH_PFC_PIN_GROUP(msiof1_rxd_c),
  3753. SH_PFC_PIN_GROUP(msiof1_clk_d),
  3754. SH_PFC_PIN_GROUP(msiof1_sync_d),
  3755. SH_PFC_PIN_GROUP(msiof1_ss1_d),
  3756. SH_PFC_PIN_GROUP(msiof1_ss2_d),
  3757. SH_PFC_PIN_GROUP(msiof1_txd_d),
  3758. SH_PFC_PIN_GROUP(msiof1_rxd_d),
  3759. SH_PFC_PIN_GROUP(msiof1_clk_e),
  3760. SH_PFC_PIN_GROUP(msiof1_sync_e),
  3761. SH_PFC_PIN_GROUP(msiof1_ss1_e),
  3762. SH_PFC_PIN_GROUP(msiof1_ss2_e),
  3763. SH_PFC_PIN_GROUP(msiof1_txd_e),
  3764. SH_PFC_PIN_GROUP(msiof1_rxd_e),
  3765. SH_PFC_PIN_GROUP(msiof1_clk_f),
  3766. SH_PFC_PIN_GROUP(msiof1_sync_f),
  3767. SH_PFC_PIN_GROUP(msiof1_ss1_f),
  3768. SH_PFC_PIN_GROUP(msiof1_ss2_f),
  3769. SH_PFC_PIN_GROUP(msiof1_txd_f),
  3770. SH_PFC_PIN_GROUP(msiof1_rxd_f),
  3771. SH_PFC_PIN_GROUP(msiof1_clk_g),
  3772. SH_PFC_PIN_GROUP(msiof1_sync_g),
  3773. SH_PFC_PIN_GROUP(msiof1_ss1_g),
  3774. SH_PFC_PIN_GROUP(msiof1_ss2_g),
  3775. SH_PFC_PIN_GROUP(msiof1_txd_g),
  3776. SH_PFC_PIN_GROUP(msiof1_rxd_g),
  3777. SH_PFC_PIN_GROUP(msiof2_clk_a),
  3778. SH_PFC_PIN_GROUP(msiof2_sync_a),
  3779. SH_PFC_PIN_GROUP(msiof2_ss1_a),
  3780. SH_PFC_PIN_GROUP(msiof2_ss2_a),
  3781. SH_PFC_PIN_GROUP(msiof2_txd_a),
  3782. SH_PFC_PIN_GROUP(msiof2_rxd_a),
  3783. SH_PFC_PIN_GROUP(msiof2_clk_b),
  3784. SH_PFC_PIN_GROUP(msiof2_sync_b),
  3785. SH_PFC_PIN_GROUP(msiof2_ss1_b),
  3786. SH_PFC_PIN_GROUP(msiof2_ss2_b),
  3787. SH_PFC_PIN_GROUP(msiof2_txd_b),
  3788. SH_PFC_PIN_GROUP(msiof2_rxd_b),
  3789. SH_PFC_PIN_GROUP(msiof2_clk_c),
  3790. SH_PFC_PIN_GROUP(msiof2_sync_c),
  3791. SH_PFC_PIN_GROUP(msiof2_ss1_c),
  3792. SH_PFC_PIN_GROUP(msiof2_ss2_c),
  3793. SH_PFC_PIN_GROUP(msiof2_txd_c),
  3794. SH_PFC_PIN_GROUP(msiof2_rxd_c),
  3795. SH_PFC_PIN_GROUP(msiof2_clk_d),
  3796. SH_PFC_PIN_GROUP(msiof2_sync_d),
  3797. SH_PFC_PIN_GROUP(msiof2_ss1_d),
  3798. SH_PFC_PIN_GROUP(msiof2_ss2_d),
  3799. SH_PFC_PIN_GROUP(msiof2_txd_d),
  3800. SH_PFC_PIN_GROUP(msiof2_rxd_d),
  3801. SH_PFC_PIN_GROUP(msiof3_clk_a),
  3802. SH_PFC_PIN_GROUP(msiof3_sync_a),
  3803. SH_PFC_PIN_GROUP(msiof3_ss1_a),
  3804. SH_PFC_PIN_GROUP(msiof3_ss2_a),
  3805. SH_PFC_PIN_GROUP(msiof3_txd_a),
  3806. SH_PFC_PIN_GROUP(msiof3_rxd_a),
  3807. SH_PFC_PIN_GROUP(msiof3_clk_b),
  3808. SH_PFC_PIN_GROUP(msiof3_sync_b),
  3809. SH_PFC_PIN_GROUP(msiof3_ss1_b),
  3810. SH_PFC_PIN_GROUP(msiof3_ss2_b),
  3811. SH_PFC_PIN_GROUP(msiof3_txd_b),
  3812. SH_PFC_PIN_GROUP(msiof3_rxd_b),
  3813. SH_PFC_PIN_GROUP(msiof3_clk_c),
  3814. SH_PFC_PIN_GROUP(msiof3_sync_c),
  3815. SH_PFC_PIN_GROUP(msiof3_txd_c),
  3816. SH_PFC_PIN_GROUP(msiof3_rxd_c),
  3817. SH_PFC_PIN_GROUP(msiof3_clk_d),
  3818. SH_PFC_PIN_GROUP(msiof3_sync_d),
  3819. SH_PFC_PIN_GROUP(msiof3_ss1_d),
  3820. SH_PFC_PIN_GROUP(msiof3_txd_d),
  3821. SH_PFC_PIN_GROUP(msiof3_rxd_d),
  3822. SH_PFC_PIN_GROUP(pwm0),
  3823. SH_PFC_PIN_GROUP(pwm1_a),
  3824. SH_PFC_PIN_GROUP(pwm1_b),
  3825. SH_PFC_PIN_GROUP(pwm2_a),
  3826. SH_PFC_PIN_GROUP(pwm2_b),
  3827. SH_PFC_PIN_GROUP(pwm3_a),
  3828. SH_PFC_PIN_GROUP(pwm3_b),
  3829. SH_PFC_PIN_GROUP(pwm4_a),
  3830. SH_PFC_PIN_GROUP(pwm4_b),
  3831. SH_PFC_PIN_GROUP(pwm5_a),
  3832. SH_PFC_PIN_GROUP(pwm5_b),
  3833. SH_PFC_PIN_GROUP(pwm6_a),
  3834. SH_PFC_PIN_GROUP(pwm6_b),
  3835. SH_PFC_PIN_GROUP(qspi0_ctrl),
  3836. BUS_DATA_PIN_GROUP(qspi0_data, 2),
  3837. BUS_DATA_PIN_GROUP(qspi0_data, 4),
  3838. SH_PFC_PIN_GROUP(qspi1_ctrl),
  3839. BUS_DATA_PIN_GROUP(qspi1_data, 2),
  3840. BUS_DATA_PIN_GROUP(qspi1_data, 4),
  3841. SH_PFC_PIN_GROUP(sata0_devslp_a),
  3842. SH_PFC_PIN_GROUP(sata0_devslp_b),
  3843. SH_PFC_PIN_GROUP(scif0_data),
  3844. SH_PFC_PIN_GROUP(scif0_clk),
  3845. SH_PFC_PIN_GROUP(scif0_ctrl),
  3846. SH_PFC_PIN_GROUP(scif1_data_a),
  3847. SH_PFC_PIN_GROUP(scif1_clk),
  3848. SH_PFC_PIN_GROUP(scif1_ctrl),
  3849. SH_PFC_PIN_GROUP(scif1_data_b),
  3850. SH_PFC_PIN_GROUP(scif2_data_a),
  3851. SH_PFC_PIN_GROUP(scif2_clk),
  3852. SH_PFC_PIN_GROUP(scif2_data_b),
  3853. SH_PFC_PIN_GROUP(scif3_data_a),
  3854. SH_PFC_PIN_GROUP(scif3_clk),
  3855. SH_PFC_PIN_GROUP(scif3_ctrl),
  3856. SH_PFC_PIN_GROUP(scif3_data_b),
  3857. SH_PFC_PIN_GROUP(scif4_data_a),
  3858. SH_PFC_PIN_GROUP(scif4_clk_a),
  3859. SH_PFC_PIN_GROUP(scif4_ctrl_a),
  3860. SH_PFC_PIN_GROUP(scif4_data_b),
  3861. SH_PFC_PIN_GROUP(scif4_clk_b),
  3862. SH_PFC_PIN_GROUP(scif4_ctrl_b),
  3863. SH_PFC_PIN_GROUP(scif4_data_c),
  3864. SH_PFC_PIN_GROUP(scif4_clk_c),
  3865. SH_PFC_PIN_GROUP(scif4_ctrl_c),
  3866. SH_PFC_PIN_GROUP(scif5_data),
  3867. SH_PFC_PIN_GROUP(scif5_clk),
  3868. SH_PFC_PIN_GROUP(scif_clk_a),
  3869. SH_PFC_PIN_GROUP(scif_clk_b),
  3870. BUS_DATA_PIN_GROUP(sdhi0_data, 1),
  3871. BUS_DATA_PIN_GROUP(sdhi0_data, 4),
  3872. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  3873. SH_PFC_PIN_GROUP(sdhi0_cd),
  3874. SH_PFC_PIN_GROUP(sdhi0_wp),
  3875. BUS_DATA_PIN_GROUP(sdhi1_data, 1),
  3876. BUS_DATA_PIN_GROUP(sdhi1_data, 4),
  3877. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  3878. SH_PFC_PIN_GROUP(sdhi1_cd),
  3879. SH_PFC_PIN_GROUP(sdhi1_wp),
  3880. BUS_DATA_PIN_GROUP(sdhi2_data, 1),
  3881. BUS_DATA_PIN_GROUP(sdhi2_data, 4),
  3882. BUS_DATA_PIN_GROUP(sdhi2_data, 8),
  3883. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  3884. SH_PFC_PIN_GROUP(sdhi2_cd_a),
  3885. SH_PFC_PIN_GROUP(sdhi2_wp_a),
  3886. SH_PFC_PIN_GROUP(sdhi2_cd_b),
  3887. SH_PFC_PIN_GROUP(sdhi2_wp_b),
  3888. SH_PFC_PIN_GROUP(sdhi2_ds),
  3889. BUS_DATA_PIN_GROUP(sdhi3_data, 1),
  3890. BUS_DATA_PIN_GROUP(sdhi3_data, 4),
  3891. BUS_DATA_PIN_GROUP(sdhi3_data, 8),
  3892. SH_PFC_PIN_GROUP(sdhi3_ctrl),
  3893. SH_PFC_PIN_GROUP(sdhi3_cd),
  3894. SH_PFC_PIN_GROUP(sdhi3_wp),
  3895. SH_PFC_PIN_GROUP(sdhi3_ds),
  3896. SH_PFC_PIN_GROUP(ssi0_data),
  3897. SH_PFC_PIN_GROUP(ssi01239_ctrl),
  3898. SH_PFC_PIN_GROUP(ssi1_data_a),
  3899. SH_PFC_PIN_GROUP(ssi1_data_b),
  3900. SH_PFC_PIN_GROUP(ssi1_ctrl_a),
  3901. SH_PFC_PIN_GROUP(ssi1_ctrl_b),
  3902. SH_PFC_PIN_GROUP(ssi2_data_a),
  3903. SH_PFC_PIN_GROUP(ssi2_data_b),
  3904. SH_PFC_PIN_GROUP(ssi2_ctrl_a),
  3905. SH_PFC_PIN_GROUP(ssi2_ctrl_b),
  3906. SH_PFC_PIN_GROUP(ssi3_data),
  3907. SH_PFC_PIN_GROUP(ssi349_ctrl),
  3908. SH_PFC_PIN_GROUP(ssi4_data),
  3909. SH_PFC_PIN_GROUP(ssi4_ctrl),
  3910. SH_PFC_PIN_GROUP(ssi5_data),
  3911. SH_PFC_PIN_GROUP(ssi5_ctrl),
  3912. SH_PFC_PIN_GROUP(ssi6_data),
  3913. SH_PFC_PIN_GROUP(ssi6_ctrl),
  3914. SH_PFC_PIN_GROUP(ssi7_data),
  3915. SH_PFC_PIN_GROUP(ssi78_ctrl),
  3916. SH_PFC_PIN_GROUP(ssi8_data),
  3917. SH_PFC_PIN_GROUP(ssi9_data_a),
  3918. SH_PFC_PIN_GROUP(ssi9_data_b),
  3919. SH_PFC_PIN_GROUP(ssi9_ctrl_a),
  3920. SH_PFC_PIN_GROUP(ssi9_ctrl_b),
  3921. SH_PFC_PIN_GROUP(tmu_tclk1_a),
  3922. SH_PFC_PIN_GROUP(tmu_tclk1_b),
  3923. SH_PFC_PIN_GROUP(tmu_tclk2_a),
  3924. SH_PFC_PIN_GROUP(tmu_tclk2_b),
  3925. SH_PFC_PIN_GROUP(tpu_to0),
  3926. SH_PFC_PIN_GROUP(tpu_to1),
  3927. SH_PFC_PIN_GROUP(tpu_to2),
  3928. SH_PFC_PIN_GROUP(tpu_to3),
  3929. SH_PFC_PIN_GROUP(usb0),
  3930. SH_PFC_PIN_GROUP(usb1),
  3931. SH_PFC_PIN_GROUP(usb2),
  3932. SH_PFC_PIN_GROUP(usb30),
  3933. SH_PFC_PIN_GROUP(usb31),
  3934. };
  3935. static const char * const audio_clk_groups[] = {
  3936. "audio_clk_a_a",
  3937. "audio_clk_a_b",
  3938. "audio_clk_a_c",
  3939. "audio_clk_b_a",
  3940. "audio_clk_b_b",
  3941. "audio_clk_c_a",
  3942. "audio_clk_c_b",
  3943. "audio_clkout_a",
  3944. "audio_clkout_b",
  3945. "audio_clkout_c",
  3946. "audio_clkout_d",
  3947. "audio_clkout1_a",
  3948. "audio_clkout1_b",
  3949. "audio_clkout2_a",
  3950. "audio_clkout2_b",
  3951. "audio_clkout3_a",
  3952. "audio_clkout3_b",
  3953. };
  3954. static const char * const avb_groups[] = {
  3955. "avb_link",
  3956. "avb_magic",
  3957. "avb_phy_int",
  3958. "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
  3959. "avb_mdio",
  3960. "avb_mii",
  3961. "avb_avtp_pps",
  3962. "avb_avtp_match_a",
  3963. "avb_avtp_capture_a",
  3964. "avb_avtp_match_b",
  3965. "avb_avtp_capture_b",
  3966. };
  3967. static const char * const can0_groups[] = {
  3968. "can0_data_a",
  3969. "can0_data_b",
  3970. };
  3971. static const char * const can1_groups[] = {
  3972. "can1_data",
  3973. };
  3974. static const char * const can_clk_groups[] = {
  3975. "can_clk",
  3976. };
  3977. static const char * const canfd0_groups[] = {
  3978. "canfd0_data_a",
  3979. "canfd0_data_b",
  3980. };
  3981. static const char * const canfd1_groups[] = {
  3982. "canfd1_data",
  3983. };
  3984. static const char * const drif0_groups[] = {
  3985. "drif0_ctrl_a",
  3986. "drif0_data0_a",
  3987. "drif0_data1_a",
  3988. "drif0_ctrl_b",
  3989. "drif0_data0_b",
  3990. "drif0_data1_b",
  3991. "drif0_ctrl_c",
  3992. "drif0_data0_c",
  3993. "drif0_data1_c",
  3994. };
  3995. static const char * const drif1_groups[] = {
  3996. "drif1_ctrl_a",
  3997. "drif1_data0_a",
  3998. "drif1_data1_a",
  3999. "drif1_ctrl_b",
  4000. "drif1_data0_b",
  4001. "drif1_data1_b",
  4002. "drif1_ctrl_c",
  4003. "drif1_data0_c",
  4004. "drif1_data1_c",
  4005. };
  4006. static const char * const drif2_groups[] = {
  4007. "drif2_ctrl_a",
  4008. "drif2_data0_a",
  4009. "drif2_data1_a",
  4010. "drif2_ctrl_b",
  4011. "drif2_data0_b",
  4012. "drif2_data1_b",
  4013. };
  4014. static const char * const drif3_groups[] = {
  4015. "drif3_ctrl_a",
  4016. "drif3_data0_a",
  4017. "drif3_data1_a",
  4018. "drif3_ctrl_b",
  4019. "drif3_data0_b",
  4020. "drif3_data1_b",
  4021. };
  4022. static const char * const du_groups[] = {
  4023. "du_rgb666",
  4024. "du_rgb888",
  4025. "du_clk_out_0",
  4026. "du_clk_out_1",
  4027. "du_sync",
  4028. "du_oddf",
  4029. "du_cde",
  4030. "du_disp",
  4031. };
  4032. static const char * const hscif0_groups[] = {
  4033. "hscif0_data",
  4034. "hscif0_clk",
  4035. "hscif0_ctrl",
  4036. };
  4037. static const char * const hscif1_groups[] = {
  4038. "hscif1_data_a",
  4039. "hscif1_clk_a",
  4040. "hscif1_ctrl_a",
  4041. "hscif1_data_b",
  4042. "hscif1_clk_b",
  4043. "hscif1_ctrl_b",
  4044. };
  4045. static const char * const hscif2_groups[] = {
  4046. "hscif2_data_a",
  4047. "hscif2_clk_a",
  4048. "hscif2_ctrl_a",
  4049. "hscif2_data_b",
  4050. "hscif2_clk_b",
  4051. "hscif2_ctrl_b",
  4052. };
  4053. static const char * const hscif3_groups[] = {
  4054. "hscif3_data_a",
  4055. "hscif3_clk",
  4056. "hscif3_ctrl",
  4057. "hscif3_data_b",
  4058. "hscif3_data_c",
  4059. "hscif3_data_d",
  4060. };
  4061. static const char * const hscif4_groups[] = {
  4062. "hscif4_data_a",
  4063. "hscif4_clk",
  4064. "hscif4_ctrl",
  4065. "hscif4_data_b",
  4066. };
  4067. static const char * const i2c0_groups[] = {
  4068. "i2c0",
  4069. };
  4070. static const char * const i2c1_groups[] = {
  4071. "i2c1_a",
  4072. "i2c1_b",
  4073. };
  4074. static const char * const i2c2_groups[] = {
  4075. "i2c2_a",
  4076. "i2c2_b",
  4077. };
  4078. static const char * const i2c3_groups[] = {
  4079. "i2c3",
  4080. };
  4081. static const char * const i2c5_groups[] = {
  4082. "i2c5",
  4083. };
  4084. static const char * const i2c6_groups[] = {
  4085. "i2c6_a",
  4086. "i2c6_b",
  4087. "i2c6_c",
  4088. };
  4089. static const char * const intc_ex_groups[] = {
  4090. "intc_ex_irq0",
  4091. "intc_ex_irq1",
  4092. "intc_ex_irq2",
  4093. "intc_ex_irq3",
  4094. "intc_ex_irq4",
  4095. "intc_ex_irq5",
  4096. };
  4097. static const char * const mlb_3pin_groups[] = {
  4098. "mlb_3pin",
  4099. };
  4100. static const char * const msiof0_groups[] = {
  4101. "msiof0_clk",
  4102. "msiof0_sync",
  4103. "msiof0_ss1",
  4104. "msiof0_ss2",
  4105. "msiof0_txd",
  4106. "msiof0_rxd",
  4107. };
  4108. static const char * const msiof1_groups[] = {
  4109. "msiof1_clk_a",
  4110. "msiof1_sync_a",
  4111. "msiof1_ss1_a",
  4112. "msiof1_ss2_a",
  4113. "msiof1_txd_a",
  4114. "msiof1_rxd_a",
  4115. "msiof1_clk_b",
  4116. "msiof1_sync_b",
  4117. "msiof1_ss1_b",
  4118. "msiof1_ss2_b",
  4119. "msiof1_txd_b",
  4120. "msiof1_rxd_b",
  4121. "msiof1_clk_c",
  4122. "msiof1_sync_c",
  4123. "msiof1_ss1_c",
  4124. "msiof1_ss2_c",
  4125. "msiof1_txd_c",
  4126. "msiof1_rxd_c",
  4127. "msiof1_clk_d",
  4128. "msiof1_sync_d",
  4129. "msiof1_ss1_d",
  4130. "msiof1_ss2_d",
  4131. "msiof1_txd_d",
  4132. "msiof1_rxd_d",
  4133. "msiof1_clk_e",
  4134. "msiof1_sync_e",
  4135. "msiof1_ss1_e",
  4136. "msiof1_ss2_e",
  4137. "msiof1_txd_e",
  4138. "msiof1_rxd_e",
  4139. "msiof1_clk_f",
  4140. "msiof1_sync_f",
  4141. "msiof1_ss1_f",
  4142. "msiof1_ss2_f",
  4143. "msiof1_txd_f",
  4144. "msiof1_rxd_f",
  4145. "msiof1_clk_g",
  4146. "msiof1_sync_g",
  4147. "msiof1_ss1_g",
  4148. "msiof1_ss2_g",
  4149. "msiof1_txd_g",
  4150. "msiof1_rxd_g",
  4151. };
  4152. static const char * const msiof2_groups[] = {
  4153. "msiof2_clk_a",
  4154. "msiof2_sync_a",
  4155. "msiof2_ss1_a",
  4156. "msiof2_ss2_a",
  4157. "msiof2_txd_a",
  4158. "msiof2_rxd_a",
  4159. "msiof2_clk_b",
  4160. "msiof2_sync_b",
  4161. "msiof2_ss1_b",
  4162. "msiof2_ss2_b",
  4163. "msiof2_txd_b",
  4164. "msiof2_rxd_b",
  4165. "msiof2_clk_c",
  4166. "msiof2_sync_c",
  4167. "msiof2_ss1_c",
  4168. "msiof2_ss2_c",
  4169. "msiof2_txd_c",
  4170. "msiof2_rxd_c",
  4171. "msiof2_clk_d",
  4172. "msiof2_sync_d",
  4173. "msiof2_ss1_d",
  4174. "msiof2_ss2_d",
  4175. "msiof2_txd_d",
  4176. "msiof2_rxd_d",
  4177. };
  4178. static const char * const msiof3_groups[] = {
  4179. "msiof3_clk_a",
  4180. "msiof3_sync_a",
  4181. "msiof3_ss1_a",
  4182. "msiof3_ss2_a",
  4183. "msiof3_txd_a",
  4184. "msiof3_rxd_a",
  4185. "msiof3_clk_b",
  4186. "msiof3_sync_b",
  4187. "msiof3_ss1_b",
  4188. "msiof3_ss2_b",
  4189. "msiof3_txd_b",
  4190. "msiof3_rxd_b",
  4191. "msiof3_clk_c",
  4192. "msiof3_sync_c",
  4193. "msiof3_txd_c",
  4194. "msiof3_rxd_c",
  4195. "msiof3_clk_d",
  4196. "msiof3_sync_d",
  4197. "msiof3_ss1_d",
  4198. "msiof3_txd_d",
  4199. "msiof3_rxd_d",
  4200. };
  4201. static const char * const pwm0_groups[] = {
  4202. "pwm0",
  4203. };
  4204. static const char * const pwm1_groups[] = {
  4205. "pwm1_a",
  4206. "pwm1_b",
  4207. };
  4208. static const char * const pwm2_groups[] = {
  4209. "pwm2_a",
  4210. "pwm2_b",
  4211. };
  4212. static const char * const pwm3_groups[] = {
  4213. "pwm3_a",
  4214. "pwm3_b",
  4215. };
  4216. static const char * const pwm4_groups[] = {
  4217. "pwm4_a",
  4218. "pwm4_b",
  4219. };
  4220. static const char * const pwm5_groups[] = {
  4221. "pwm5_a",
  4222. "pwm5_b",
  4223. };
  4224. static const char * const pwm6_groups[] = {
  4225. "pwm6_a",
  4226. "pwm6_b",
  4227. };
  4228. static const char * const qspi0_groups[] = {
  4229. "qspi0_ctrl",
  4230. "qspi0_data2",
  4231. "qspi0_data4",
  4232. };
  4233. static const char * const qspi1_groups[] = {
  4234. "qspi1_ctrl",
  4235. "qspi1_data2",
  4236. "qspi1_data4",
  4237. };
  4238. static const char * const sata0_groups[] = {
  4239. "sata0_devslp_a",
  4240. "sata0_devslp_b",
  4241. };
  4242. static const char * const scif0_groups[] = {
  4243. "scif0_data",
  4244. "scif0_clk",
  4245. "scif0_ctrl",
  4246. };
  4247. static const char * const scif1_groups[] = {
  4248. "scif1_data_a",
  4249. "scif1_clk",
  4250. "scif1_ctrl",
  4251. "scif1_data_b",
  4252. };
  4253. static const char * const scif2_groups[] = {
  4254. "scif2_data_a",
  4255. "scif2_clk",
  4256. "scif2_data_b",
  4257. };
  4258. static const char * const scif3_groups[] = {
  4259. "scif3_data_a",
  4260. "scif3_clk",
  4261. "scif3_ctrl",
  4262. "scif3_data_b",
  4263. };
  4264. static const char * const scif4_groups[] = {
  4265. "scif4_data_a",
  4266. "scif4_clk_a",
  4267. "scif4_ctrl_a",
  4268. "scif4_data_b",
  4269. "scif4_clk_b",
  4270. "scif4_ctrl_b",
  4271. "scif4_data_c",
  4272. "scif4_clk_c",
  4273. "scif4_ctrl_c",
  4274. };
  4275. static const char * const scif5_groups[] = {
  4276. "scif5_data",
  4277. "scif5_clk",
  4278. };
  4279. static const char * const scif_clk_groups[] = {
  4280. "scif_clk_a",
  4281. "scif_clk_b",
  4282. };
  4283. static const char * const sdhi0_groups[] = {
  4284. "sdhi0_data1",
  4285. "sdhi0_data4",
  4286. "sdhi0_ctrl",
  4287. "sdhi0_cd",
  4288. "sdhi0_wp",
  4289. };
  4290. static const char * const sdhi1_groups[] = {
  4291. "sdhi1_data1",
  4292. "sdhi1_data4",
  4293. "sdhi1_ctrl",
  4294. "sdhi1_cd",
  4295. "sdhi1_wp",
  4296. };
  4297. static const char * const sdhi2_groups[] = {
  4298. "sdhi2_data1",
  4299. "sdhi2_data4",
  4300. "sdhi2_data8",
  4301. "sdhi2_ctrl",
  4302. "sdhi2_cd_a",
  4303. "sdhi2_wp_a",
  4304. "sdhi2_cd_b",
  4305. "sdhi2_wp_b",
  4306. "sdhi2_ds",
  4307. };
  4308. static const char * const sdhi3_groups[] = {
  4309. "sdhi3_data1",
  4310. "sdhi3_data4",
  4311. "sdhi3_data8",
  4312. "sdhi3_ctrl",
  4313. "sdhi3_cd",
  4314. "sdhi3_wp",
  4315. "sdhi3_ds",
  4316. };
  4317. static const char * const ssi_groups[] = {
  4318. "ssi0_data",
  4319. "ssi01239_ctrl",
  4320. "ssi1_data_a",
  4321. "ssi1_data_b",
  4322. "ssi1_ctrl_a",
  4323. "ssi1_ctrl_b",
  4324. "ssi2_data_a",
  4325. "ssi2_data_b",
  4326. "ssi2_ctrl_a",
  4327. "ssi2_ctrl_b",
  4328. "ssi3_data",
  4329. "ssi349_ctrl",
  4330. "ssi4_data",
  4331. "ssi4_ctrl",
  4332. "ssi5_data",
  4333. "ssi5_ctrl",
  4334. "ssi6_data",
  4335. "ssi6_ctrl",
  4336. "ssi7_data",
  4337. "ssi78_ctrl",
  4338. "ssi8_data",
  4339. "ssi9_data_a",
  4340. "ssi9_data_b",
  4341. "ssi9_ctrl_a",
  4342. "ssi9_ctrl_b",
  4343. };
  4344. static const char * const tmu_groups[] = {
  4345. "tmu_tclk1_a",
  4346. "tmu_tclk1_b",
  4347. "tmu_tclk2_a",
  4348. "tmu_tclk2_b",
  4349. };
  4350. static const char * const tpu_groups[] = {
  4351. "tpu_to0",
  4352. "tpu_to1",
  4353. "tpu_to2",
  4354. "tpu_to3",
  4355. };
  4356. static const char * const usb0_groups[] = {
  4357. "usb0",
  4358. };
  4359. static const char * const usb1_groups[] = {
  4360. "usb1",
  4361. };
  4362. static const char * const usb2_groups[] = {
  4363. "usb2",
  4364. };
  4365. static const char * const usb30_groups[] = {
  4366. "usb30",
  4367. };
  4368. static const char * const usb31_groups[] = {
  4369. "usb31",
  4370. };
  4371. static const struct sh_pfc_function pinmux_functions[] = {
  4372. SH_PFC_FUNCTION(audio_clk),
  4373. SH_PFC_FUNCTION(avb),
  4374. SH_PFC_FUNCTION(can0),
  4375. SH_PFC_FUNCTION(can1),
  4376. SH_PFC_FUNCTION(can_clk),
  4377. SH_PFC_FUNCTION(canfd0),
  4378. SH_PFC_FUNCTION(canfd1),
  4379. SH_PFC_FUNCTION(drif0),
  4380. SH_PFC_FUNCTION(drif1),
  4381. SH_PFC_FUNCTION(drif2),
  4382. SH_PFC_FUNCTION(drif3),
  4383. SH_PFC_FUNCTION(du),
  4384. SH_PFC_FUNCTION(hscif0),
  4385. SH_PFC_FUNCTION(hscif1),
  4386. SH_PFC_FUNCTION(hscif2),
  4387. SH_PFC_FUNCTION(hscif3),
  4388. SH_PFC_FUNCTION(hscif4),
  4389. SH_PFC_FUNCTION(i2c0),
  4390. SH_PFC_FUNCTION(i2c1),
  4391. SH_PFC_FUNCTION(i2c2),
  4392. SH_PFC_FUNCTION(i2c3),
  4393. SH_PFC_FUNCTION(i2c5),
  4394. SH_PFC_FUNCTION(i2c6),
  4395. SH_PFC_FUNCTION(intc_ex),
  4396. SH_PFC_FUNCTION(mlb_3pin),
  4397. SH_PFC_FUNCTION(msiof0),
  4398. SH_PFC_FUNCTION(msiof1),
  4399. SH_PFC_FUNCTION(msiof2),
  4400. SH_PFC_FUNCTION(msiof3),
  4401. SH_PFC_FUNCTION(pwm0),
  4402. SH_PFC_FUNCTION(pwm1),
  4403. SH_PFC_FUNCTION(pwm2),
  4404. SH_PFC_FUNCTION(pwm3),
  4405. SH_PFC_FUNCTION(pwm4),
  4406. SH_PFC_FUNCTION(pwm5),
  4407. SH_PFC_FUNCTION(pwm6),
  4408. SH_PFC_FUNCTION(qspi0),
  4409. SH_PFC_FUNCTION(qspi1),
  4410. SH_PFC_FUNCTION(sata0),
  4411. SH_PFC_FUNCTION(scif0),
  4412. SH_PFC_FUNCTION(scif1),
  4413. SH_PFC_FUNCTION(scif2),
  4414. SH_PFC_FUNCTION(scif3),
  4415. SH_PFC_FUNCTION(scif4),
  4416. SH_PFC_FUNCTION(scif5),
  4417. SH_PFC_FUNCTION(scif_clk),
  4418. SH_PFC_FUNCTION(sdhi0),
  4419. SH_PFC_FUNCTION(sdhi1),
  4420. SH_PFC_FUNCTION(sdhi2),
  4421. SH_PFC_FUNCTION(sdhi3),
  4422. SH_PFC_FUNCTION(ssi),
  4423. SH_PFC_FUNCTION(tmu),
  4424. SH_PFC_FUNCTION(tpu),
  4425. SH_PFC_FUNCTION(usb0),
  4426. SH_PFC_FUNCTION(usb1),
  4427. SH_PFC_FUNCTION(usb2),
  4428. SH_PFC_FUNCTION(usb30),
  4429. SH_PFC_FUNCTION(usb31),
  4430. };
  4431. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  4432. #define F_(x, y) FN_##y
  4433. #define FM(x) FN_##x
  4434. { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
  4435. GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  4436. 1, 1, 1, 1, 1),
  4437. GROUP(
  4438. /* GP0_31_16 RESERVED */
  4439. GP_0_15_FN, GPSR0_15,
  4440. GP_0_14_FN, GPSR0_14,
  4441. GP_0_13_FN, GPSR0_13,
  4442. GP_0_12_FN, GPSR0_12,
  4443. GP_0_11_FN, GPSR0_11,
  4444. GP_0_10_FN, GPSR0_10,
  4445. GP_0_9_FN, GPSR0_9,
  4446. GP_0_8_FN, GPSR0_8,
  4447. GP_0_7_FN, GPSR0_7,
  4448. GP_0_6_FN, GPSR0_6,
  4449. GP_0_5_FN, GPSR0_5,
  4450. GP_0_4_FN, GPSR0_4,
  4451. GP_0_3_FN, GPSR0_3,
  4452. GP_0_2_FN, GPSR0_2,
  4453. GP_0_1_FN, GPSR0_1,
  4454. GP_0_0_FN, GPSR0_0, ))
  4455. },
  4456. { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
  4457. 0, 0,
  4458. 0, 0,
  4459. 0, 0,
  4460. 0, 0,
  4461. GP_1_27_FN, GPSR1_27,
  4462. GP_1_26_FN, GPSR1_26,
  4463. GP_1_25_FN, GPSR1_25,
  4464. GP_1_24_FN, GPSR1_24,
  4465. GP_1_23_FN, GPSR1_23,
  4466. GP_1_22_FN, GPSR1_22,
  4467. GP_1_21_FN, GPSR1_21,
  4468. GP_1_20_FN, GPSR1_20,
  4469. GP_1_19_FN, GPSR1_19,
  4470. GP_1_18_FN, GPSR1_18,
  4471. GP_1_17_FN, GPSR1_17,
  4472. GP_1_16_FN, GPSR1_16,
  4473. GP_1_15_FN, GPSR1_15,
  4474. GP_1_14_FN, GPSR1_14,
  4475. GP_1_13_FN, GPSR1_13,
  4476. GP_1_12_FN, GPSR1_12,
  4477. GP_1_11_FN, GPSR1_11,
  4478. GP_1_10_FN, GPSR1_10,
  4479. GP_1_9_FN, GPSR1_9,
  4480. GP_1_8_FN, GPSR1_8,
  4481. GP_1_7_FN, GPSR1_7,
  4482. GP_1_6_FN, GPSR1_6,
  4483. GP_1_5_FN, GPSR1_5,
  4484. GP_1_4_FN, GPSR1_4,
  4485. GP_1_3_FN, GPSR1_3,
  4486. GP_1_2_FN, GPSR1_2,
  4487. GP_1_1_FN, GPSR1_1,
  4488. GP_1_0_FN, GPSR1_0, ))
  4489. },
  4490. { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
  4491. GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  4492. 1, 1, 1, 1),
  4493. GROUP(
  4494. /* GP2_31_15 RESERVED */
  4495. GP_2_14_FN, GPSR2_14,
  4496. GP_2_13_FN, GPSR2_13,
  4497. GP_2_12_FN, GPSR2_12,
  4498. GP_2_11_FN, GPSR2_11,
  4499. GP_2_10_FN, GPSR2_10,
  4500. GP_2_9_FN, GPSR2_9,
  4501. GP_2_8_FN, GPSR2_8,
  4502. GP_2_7_FN, GPSR2_7,
  4503. GP_2_6_FN, GPSR2_6,
  4504. GP_2_5_FN, GPSR2_5,
  4505. GP_2_4_FN, GPSR2_4,
  4506. GP_2_3_FN, GPSR2_3,
  4507. GP_2_2_FN, GPSR2_2,
  4508. GP_2_1_FN, GPSR2_1,
  4509. GP_2_0_FN, GPSR2_0, ))
  4510. },
  4511. { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
  4512. GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  4513. 1, 1, 1, 1, 1),
  4514. GROUP(
  4515. /* GP3_31_16 RESERVED */
  4516. GP_3_15_FN, GPSR3_15,
  4517. GP_3_14_FN, GPSR3_14,
  4518. GP_3_13_FN, GPSR3_13,
  4519. GP_3_12_FN, GPSR3_12,
  4520. GP_3_11_FN, GPSR3_11,
  4521. GP_3_10_FN, GPSR3_10,
  4522. GP_3_9_FN, GPSR3_9,
  4523. GP_3_8_FN, GPSR3_8,
  4524. GP_3_7_FN, GPSR3_7,
  4525. GP_3_6_FN, GPSR3_6,
  4526. GP_3_5_FN, GPSR3_5,
  4527. GP_3_4_FN, GPSR3_4,
  4528. GP_3_3_FN, GPSR3_3,
  4529. GP_3_2_FN, GPSR3_2,
  4530. GP_3_1_FN, GPSR3_1,
  4531. GP_3_0_FN, GPSR3_0, ))
  4532. },
  4533. { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
  4534. GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  4535. 1, 1, 1, 1, 1, 1, 1),
  4536. GROUP(
  4537. /* GP4_31_18 RESERVED */
  4538. GP_4_17_FN, GPSR4_17,
  4539. GP_4_16_FN, GPSR4_16,
  4540. GP_4_15_FN, GPSR4_15,
  4541. GP_4_14_FN, GPSR4_14,
  4542. GP_4_13_FN, GPSR4_13,
  4543. GP_4_12_FN, GPSR4_12,
  4544. GP_4_11_FN, GPSR4_11,
  4545. GP_4_10_FN, GPSR4_10,
  4546. GP_4_9_FN, GPSR4_9,
  4547. GP_4_8_FN, GPSR4_8,
  4548. GP_4_7_FN, GPSR4_7,
  4549. GP_4_6_FN, GPSR4_6,
  4550. GP_4_5_FN, GPSR4_5,
  4551. GP_4_4_FN, GPSR4_4,
  4552. GP_4_3_FN, GPSR4_3,
  4553. GP_4_2_FN, GPSR4_2,
  4554. GP_4_1_FN, GPSR4_1,
  4555. GP_4_0_FN, GPSR4_0, ))
  4556. },
  4557. { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
  4558. 0, 0,
  4559. 0, 0,
  4560. 0, 0,
  4561. 0, 0,
  4562. 0, 0,
  4563. 0, 0,
  4564. GP_5_25_FN, GPSR5_25,
  4565. GP_5_24_FN, GPSR5_24,
  4566. GP_5_23_FN, GPSR5_23,
  4567. GP_5_22_FN, GPSR5_22,
  4568. GP_5_21_FN, GPSR5_21,
  4569. GP_5_20_FN, GPSR5_20,
  4570. GP_5_19_FN, GPSR5_19,
  4571. GP_5_18_FN, GPSR5_18,
  4572. GP_5_17_FN, GPSR5_17,
  4573. GP_5_16_FN, GPSR5_16,
  4574. GP_5_15_FN, GPSR5_15,
  4575. GP_5_14_FN, GPSR5_14,
  4576. GP_5_13_FN, GPSR5_13,
  4577. GP_5_12_FN, GPSR5_12,
  4578. GP_5_11_FN, GPSR5_11,
  4579. GP_5_10_FN, GPSR5_10,
  4580. GP_5_9_FN, GPSR5_9,
  4581. GP_5_8_FN, GPSR5_8,
  4582. GP_5_7_FN, GPSR5_7,
  4583. GP_5_6_FN, GPSR5_6,
  4584. GP_5_5_FN, GPSR5_5,
  4585. GP_5_4_FN, GPSR5_4,
  4586. GP_5_3_FN, GPSR5_3,
  4587. GP_5_2_FN, GPSR5_2,
  4588. GP_5_1_FN, GPSR5_1,
  4589. GP_5_0_FN, GPSR5_0, ))
  4590. },
  4591. { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
  4592. GP_6_31_FN, GPSR6_31,
  4593. GP_6_30_FN, GPSR6_30,
  4594. GP_6_29_FN, GPSR6_29,
  4595. GP_6_28_FN, GPSR6_28,
  4596. GP_6_27_FN, GPSR6_27,
  4597. GP_6_26_FN, GPSR6_26,
  4598. GP_6_25_FN, GPSR6_25,
  4599. GP_6_24_FN, GPSR6_24,
  4600. GP_6_23_FN, GPSR6_23,
  4601. GP_6_22_FN, GPSR6_22,
  4602. GP_6_21_FN, GPSR6_21,
  4603. GP_6_20_FN, GPSR6_20,
  4604. GP_6_19_FN, GPSR6_19,
  4605. GP_6_18_FN, GPSR6_18,
  4606. GP_6_17_FN, GPSR6_17,
  4607. GP_6_16_FN, GPSR6_16,
  4608. GP_6_15_FN, GPSR6_15,
  4609. GP_6_14_FN, GPSR6_14,
  4610. GP_6_13_FN, GPSR6_13,
  4611. GP_6_12_FN, GPSR6_12,
  4612. GP_6_11_FN, GPSR6_11,
  4613. GP_6_10_FN, GPSR6_10,
  4614. GP_6_9_FN, GPSR6_9,
  4615. GP_6_8_FN, GPSR6_8,
  4616. GP_6_7_FN, GPSR6_7,
  4617. GP_6_6_FN, GPSR6_6,
  4618. GP_6_5_FN, GPSR6_5,
  4619. GP_6_4_FN, GPSR6_4,
  4620. GP_6_3_FN, GPSR6_3,
  4621. GP_6_2_FN, GPSR6_2,
  4622. GP_6_1_FN, GPSR6_1,
  4623. GP_6_0_FN, GPSR6_0, ))
  4624. },
  4625. { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
  4626. GROUP(-28, 1, 1, 1, 1),
  4627. GROUP(
  4628. /* GP7_31_4 RESERVED */
  4629. GP_7_3_FN, GPSR7_3,
  4630. GP_7_2_FN, GPSR7_2,
  4631. GP_7_1_FN, GPSR7_1,
  4632. GP_7_0_FN, GPSR7_0, ))
  4633. },
  4634. #undef F_
  4635. #undef FM
  4636. #define F_(x, y) x,
  4637. #define FM(x) FN_##x,
  4638. { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
  4639. IP0_31_28
  4640. IP0_27_24
  4641. IP0_23_20
  4642. IP0_19_16
  4643. IP0_15_12
  4644. IP0_11_8
  4645. IP0_7_4
  4646. IP0_3_0 ))
  4647. },
  4648. { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
  4649. IP1_31_28
  4650. IP1_27_24
  4651. IP1_23_20
  4652. IP1_19_16
  4653. IP1_15_12
  4654. IP1_11_8
  4655. IP1_7_4
  4656. IP1_3_0 ))
  4657. },
  4658. { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
  4659. IP2_31_28
  4660. IP2_27_24
  4661. IP2_23_20
  4662. IP2_19_16
  4663. IP2_15_12
  4664. IP2_11_8
  4665. IP2_7_4
  4666. IP2_3_0 ))
  4667. },
  4668. { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
  4669. IP3_31_28
  4670. IP3_27_24
  4671. IP3_23_20
  4672. IP3_19_16
  4673. IP3_15_12
  4674. IP3_11_8
  4675. IP3_7_4
  4676. IP3_3_0 ))
  4677. },
  4678. { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
  4679. IP4_31_28
  4680. IP4_27_24
  4681. IP4_23_20
  4682. IP4_19_16
  4683. IP4_15_12
  4684. IP4_11_8
  4685. IP4_7_4
  4686. IP4_3_0 ))
  4687. },
  4688. { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
  4689. IP5_31_28
  4690. IP5_27_24
  4691. IP5_23_20
  4692. IP5_19_16
  4693. IP5_15_12
  4694. IP5_11_8
  4695. IP5_7_4
  4696. IP5_3_0 ))
  4697. },
  4698. { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
  4699. IP6_31_28
  4700. IP6_27_24
  4701. IP6_23_20
  4702. IP6_19_16
  4703. IP6_15_12
  4704. IP6_11_8
  4705. IP6_7_4
  4706. IP6_3_0 ))
  4707. },
  4708. { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
  4709. IP7_31_28
  4710. IP7_27_24
  4711. IP7_23_20
  4712. IP7_19_16
  4713. IP7_15_12
  4714. IP7_11_8
  4715. IP7_7_4
  4716. IP7_3_0 ))
  4717. },
  4718. { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
  4719. IP8_31_28
  4720. IP8_27_24
  4721. IP8_23_20
  4722. IP8_19_16
  4723. IP8_15_12
  4724. IP8_11_8
  4725. IP8_7_4
  4726. IP8_3_0 ))
  4727. },
  4728. { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
  4729. IP9_31_28
  4730. IP9_27_24
  4731. IP9_23_20
  4732. IP9_19_16
  4733. IP9_15_12
  4734. IP9_11_8
  4735. IP9_7_4
  4736. IP9_3_0 ))
  4737. },
  4738. { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
  4739. IP10_31_28
  4740. IP10_27_24
  4741. IP10_23_20
  4742. IP10_19_16
  4743. IP10_15_12
  4744. IP10_11_8
  4745. IP10_7_4
  4746. IP10_3_0 ))
  4747. },
  4748. { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
  4749. IP11_31_28
  4750. IP11_27_24
  4751. IP11_23_20
  4752. IP11_19_16
  4753. IP11_15_12
  4754. IP11_11_8
  4755. IP11_7_4
  4756. IP11_3_0 ))
  4757. },
  4758. { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
  4759. IP12_31_28
  4760. IP12_27_24
  4761. IP12_23_20
  4762. IP12_19_16
  4763. IP12_15_12
  4764. IP12_11_8
  4765. IP12_7_4
  4766. IP12_3_0 ))
  4767. },
  4768. { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
  4769. IP13_31_28
  4770. IP13_27_24
  4771. IP13_23_20
  4772. IP13_19_16
  4773. IP13_15_12
  4774. IP13_11_8
  4775. IP13_7_4
  4776. IP13_3_0 ))
  4777. },
  4778. { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
  4779. IP14_31_28
  4780. IP14_27_24
  4781. IP14_23_20
  4782. IP14_19_16
  4783. IP14_15_12
  4784. IP14_11_8
  4785. IP14_7_4
  4786. IP14_3_0 ))
  4787. },
  4788. { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
  4789. IP15_31_28
  4790. IP15_27_24
  4791. IP15_23_20
  4792. IP15_19_16
  4793. IP15_15_12
  4794. IP15_11_8
  4795. IP15_7_4
  4796. IP15_3_0 ))
  4797. },
  4798. { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
  4799. IP16_31_28
  4800. IP16_27_24
  4801. IP16_23_20
  4802. IP16_19_16
  4803. IP16_15_12
  4804. IP16_11_8
  4805. IP16_7_4
  4806. IP16_3_0 ))
  4807. },
  4808. { PINMUX_CFG_REG_VAR("IPSR17", 0xe6060244, 32,
  4809. GROUP(-24, 4, 4),
  4810. GROUP(
  4811. /* IP17_31_8 RESERVED */
  4812. IP17_7_4
  4813. IP17_3_0 ))
  4814. },
  4815. #undef F_
  4816. #undef FM
  4817. #define F_(x, y) x,
  4818. #define FM(x) FN_##x,
  4819. { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
  4820. GROUP(-1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
  4821. 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, -1),
  4822. GROUP(
  4823. /* RESERVED 31 */
  4824. MOD_SEL0_30_29
  4825. MOD_SEL0_28_27
  4826. MOD_SEL0_26_25_24
  4827. MOD_SEL0_23
  4828. MOD_SEL0_22
  4829. MOD_SEL0_21_20
  4830. MOD_SEL0_19
  4831. MOD_SEL0_18
  4832. MOD_SEL0_17
  4833. MOD_SEL0_16_15
  4834. MOD_SEL0_14
  4835. MOD_SEL0_13
  4836. MOD_SEL0_12
  4837. MOD_SEL0_11
  4838. MOD_SEL0_10
  4839. MOD_SEL0_9
  4840. MOD_SEL0_8
  4841. MOD_SEL0_7_6
  4842. MOD_SEL0_5_4
  4843. MOD_SEL0_3
  4844. MOD_SEL0_2_1
  4845. /* RESERVED 0 */ ))
  4846. },
  4847. { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
  4848. GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
  4849. 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
  4850. GROUP(
  4851. MOD_SEL1_31_30
  4852. MOD_SEL1_29_28_27
  4853. MOD_SEL1_26
  4854. MOD_SEL1_25_24
  4855. MOD_SEL1_23_22_21
  4856. MOD_SEL1_20
  4857. MOD_SEL1_19
  4858. MOD_SEL1_18_17
  4859. MOD_SEL1_16
  4860. MOD_SEL1_15_14
  4861. MOD_SEL1_13
  4862. MOD_SEL1_12
  4863. MOD_SEL1_11
  4864. MOD_SEL1_10
  4865. MOD_SEL1_9
  4866. /* RESERVED 8, 7 */
  4867. MOD_SEL1_6
  4868. MOD_SEL1_5
  4869. MOD_SEL1_4
  4870. MOD_SEL1_3
  4871. MOD_SEL1_2
  4872. MOD_SEL1_1
  4873. MOD_SEL1_0 ))
  4874. },
  4875. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
  4876. GROUP(1, 1, 1, -28, 1),
  4877. GROUP(
  4878. MOD_SEL2_31
  4879. MOD_SEL2_30
  4880. MOD_SEL2_29
  4881. /* RESERVED 28-1 */
  4882. MOD_SEL2_0 ))
  4883. },
  4884. { },
  4885. };
  4886. static const struct pinmux_drive_reg pinmux_drive_regs[] = {
  4887. { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
  4888. { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
  4889. { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
  4890. { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
  4891. { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
  4892. { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
  4893. { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
  4894. { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
  4895. { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
  4896. } },
  4897. { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
  4898. { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
  4899. { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
  4900. { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
  4901. { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
  4902. { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
  4903. { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
  4904. { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
  4905. { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
  4906. } },
  4907. { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
  4908. { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
  4909. { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
  4910. { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
  4911. { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
  4912. { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
  4913. { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
  4914. { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
  4915. { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
  4916. } },
  4917. { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
  4918. { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
  4919. { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
  4920. { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
  4921. { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
  4922. { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
  4923. { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
  4924. { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
  4925. { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
  4926. } },
  4927. { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
  4928. { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
  4929. { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
  4930. { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
  4931. { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
  4932. { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
  4933. { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
  4934. { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
  4935. { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
  4936. } },
  4937. { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
  4938. { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
  4939. { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
  4940. { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
  4941. { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
  4942. { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
  4943. { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
  4944. { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
  4945. { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
  4946. } },
  4947. { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
  4948. { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
  4949. { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
  4950. { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
  4951. { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
  4952. { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
  4953. { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
  4954. { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
  4955. { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
  4956. } },
  4957. { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
  4958. { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
  4959. { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
  4960. { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
  4961. { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
  4962. { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
  4963. { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
  4964. { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
  4965. { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
  4966. } },
  4967. { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
  4968. { PIN_CLKOUT, 28, 3 }, /* CLKOUT */
  4969. { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
  4970. { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
  4971. { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
  4972. { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
  4973. { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
  4974. { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
  4975. { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
  4976. } },
  4977. { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
  4978. { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
  4979. { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
  4980. { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
  4981. { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
  4982. { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
  4983. { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
  4984. { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
  4985. { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
  4986. } },
  4987. { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
  4988. { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
  4989. { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
  4990. { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
  4991. { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
  4992. { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
  4993. { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
  4994. { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
  4995. { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
  4996. } },
  4997. { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
  4998. { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
  4999. { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
  5000. { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
  5001. { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
  5002. { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
  5003. { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
  5004. { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
  5005. { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
  5006. } },
  5007. { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
  5008. { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
  5009. { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
  5010. { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
  5011. { PIN_TMS, 4, 2 }, /* TMS */
  5012. } },
  5013. { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
  5014. { PIN_TDO, 28, 2 }, /* TDO */
  5015. { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
  5016. { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
  5017. { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
  5018. { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
  5019. { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
  5020. { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
  5021. { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
  5022. } },
  5023. { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
  5024. { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
  5025. { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
  5026. { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
  5027. { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
  5028. { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
  5029. { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
  5030. { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
  5031. { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
  5032. } },
  5033. { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
  5034. { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
  5035. { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
  5036. { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
  5037. { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
  5038. { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
  5039. { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
  5040. { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
  5041. { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
  5042. } },
  5043. { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
  5044. { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
  5045. { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
  5046. { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
  5047. { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
  5048. { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
  5049. { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
  5050. { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
  5051. { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
  5052. } },
  5053. { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
  5054. { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
  5055. { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
  5056. { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
  5057. { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
  5058. { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
  5059. { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
  5060. { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
  5061. { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
  5062. } },
  5063. { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
  5064. { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
  5065. { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
  5066. { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
  5067. { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
  5068. { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
  5069. { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
  5070. { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
  5071. { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
  5072. } },
  5073. { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
  5074. { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
  5075. { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
  5076. { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
  5077. { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
  5078. { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
  5079. { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
  5080. { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
  5081. { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
  5082. } },
  5083. { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
  5084. { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
  5085. { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
  5086. { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
  5087. { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
  5088. { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
  5089. { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
  5090. { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
  5091. { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
  5092. } },
  5093. { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
  5094. { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
  5095. { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
  5096. { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
  5097. { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
  5098. { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
  5099. { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
  5100. { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
  5101. { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
  5102. } },
  5103. { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
  5104. { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
  5105. { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
  5106. { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
  5107. { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
  5108. { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
  5109. { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
  5110. { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
  5111. { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
  5112. } },
  5113. { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
  5114. { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
  5115. { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
  5116. { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
  5117. { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
  5118. { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
  5119. { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
  5120. { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
  5121. { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
  5122. } },
  5123. { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
  5124. { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
  5125. { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
  5126. { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
  5127. { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
  5128. { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
  5129. { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
  5130. { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
  5131. } },
  5132. { },
  5133. };
  5134. enum ioctrl_regs {
  5135. POCCTRL,
  5136. TDSELCTRL,
  5137. };
  5138. static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
  5139. [POCCTRL] = { 0xe6060380, },
  5140. [TDSELCTRL] = { 0xe60603c0, },
  5141. { /* sentinel */ },
  5142. };
  5143. static int r8a77950_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
  5144. {
  5145. int bit = -EINVAL;
  5146. *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
  5147. if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
  5148. bit = pin & 0x1f;
  5149. if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
  5150. bit = (pin & 0x1f) + 12;
  5151. return bit;
  5152. }
  5153. static const struct pinmux_bias_reg pinmux_bias_regs[] = {
  5154. { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
  5155. [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
  5156. [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
  5157. [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
  5158. [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
  5159. [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
  5160. [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
  5161. [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
  5162. [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
  5163. [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
  5164. [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
  5165. [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
  5166. [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
  5167. [12] = PIN_RPC_INT_N, /* RPC_INT# */
  5168. [13] = PIN_RPC_WP_N, /* RPC_WP# */
  5169. [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
  5170. [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
  5171. [16] = PIN_AVB_RXC, /* AVB_RXC */
  5172. [17] = PIN_AVB_RD0, /* AVB_RD0 */
  5173. [18] = PIN_AVB_RD1, /* AVB_RD1 */
  5174. [19] = PIN_AVB_RD2, /* AVB_RD2 */
  5175. [20] = PIN_AVB_RD3, /* AVB_RD3 */
  5176. [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
  5177. [22] = PIN_AVB_TXC, /* AVB_TXC */
  5178. [23] = PIN_AVB_TD0, /* AVB_TD0 */
  5179. [24] = PIN_AVB_TD1, /* AVB_TD1 */
  5180. [25] = PIN_AVB_TD2, /* AVB_TD2 */
  5181. [26] = PIN_AVB_TD3, /* AVB_TD3 */
  5182. [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
  5183. [28] = PIN_AVB_MDIO, /* AVB_MDIO */
  5184. [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
  5185. [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
  5186. [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
  5187. } },
  5188. { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
  5189. [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
  5190. [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
  5191. [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
  5192. [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
  5193. [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
  5194. [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
  5195. [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
  5196. [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
  5197. [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
  5198. [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
  5199. [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
  5200. [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
  5201. [12] = RCAR_GP_PIN(1, 0), /* A0 */
  5202. [13] = RCAR_GP_PIN(1, 1), /* A1 */
  5203. [14] = RCAR_GP_PIN(1, 2), /* A2 */
  5204. [15] = RCAR_GP_PIN(1, 3), /* A3 */
  5205. [16] = RCAR_GP_PIN(1, 4), /* A4 */
  5206. [17] = RCAR_GP_PIN(1, 5), /* A5 */
  5207. [18] = RCAR_GP_PIN(1, 6), /* A6 */
  5208. [19] = RCAR_GP_PIN(1, 7), /* A7 */
  5209. [20] = RCAR_GP_PIN(1, 8), /* A8 */
  5210. [21] = RCAR_GP_PIN(1, 9), /* A9 */
  5211. [22] = RCAR_GP_PIN(1, 10), /* A10 */
  5212. [23] = RCAR_GP_PIN(1, 11), /* A11 */
  5213. [24] = RCAR_GP_PIN(1, 12), /* A12 */
  5214. [25] = RCAR_GP_PIN(1, 13), /* A13 */
  5215. [26] = RCAR_GP_PIN(1, 14), /* A14 */
  5216. [27] = RCAR_GP_PIN(1, 15), /* A15 */
  5217. [28] = RCAR_GP_PIN(1, 16), /* A16 */
  5218. [29] = RCAR_GP_PIN(1, 17), /* A17 */
  5219. [30] = RCAR_GP_PIN(1, 18), /* A18 */
  5220. [31] = RCAR_GP_PIN(1, 19), /* A19 */
  5221. } },
  5222. { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
  5223. [ 0] = PIN_CLKOUT, /* CLKOUT */
  5224. [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
  5225. [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
  5226. [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
  5227. [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
  5228. [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
  5229. [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
  5230. [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
  5231. [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
  5232. [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
  5233. [10] = RCAR_GP_PIN(0, 0), /* D0 */
  5234. [11] = RCAR_GP_PIN(0, 1), /* D1 */
  5235. [12] = RCAR_GP_PIN(0, 2), /* D2 */
  5236. [13] = RCAR_GP_PIN(0, 3), /* D3 */
  5237. [14] = RCAR_GP_PIN(0, 4), /* D4 */
  5238. [15] = RCAR_GP_PIN(0, 5), /* D5 */
  5239. [16] = RCAR_GP_PIN(0, 6), /* D6 */
  5240. [17] = RCAR_GP_PIN(0, 7), /* D7 */
  5241. [18] = RCAR_GP_PIN(0, 8), /* D8 */
  5242. [19] = RCAR_GP_PIN(0, 9), /* D9 */
  5243. [20] = RCAR_GP_PIN(0, 10), /* D10 */
  5244. [21] = RCAR_GP_PIN(0, 11), /* D11 */
  5245. [22] = RCAR_GP_PIN(0, 12), /* D12 */
  5246. [23] = RCAR_GP_PIN(0, 13), /* D13 */
  5247. [24] = RCAR_GP_PIN(0, 14), /* D14 */
  5248. [25] = RCAR_GP_PIN(0, 15), /* D15 */
  5249. [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
  5250. [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
  5251. [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
  5252. [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
  5253. [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
  5254. [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
  5255. } },
  5256. { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
  5257. [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
  5258. [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
  5259. [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
  5260. [ 3] = PIN_EXTALR, /* EXTALR*/
  5261. [ 4] = PIN_TRST_N, /* TRST# */
  5262. [ 5] = PIN_TCK, /* TCK */
  5263. [ 6] = PIN_TMS, /* TMS */
  5264. [ 7] = PIN_TDI, /* TDI */
  5265. [ 8] = SH_PFC_PIN_NONE,
  5266. [ 9] = PIN_ASEBRK, /* ASEBRK */
  5267. [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
  5268. [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
  5269. [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
  5270. [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
  5271. [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
  5272. [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
  5273. [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
  5274. [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
  5275. [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
  5276. [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
  5277. [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
  5278. [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
  5279. [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
  5280. [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
  5281. [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
  5282. [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
  5283. [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
  5284. [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
  5285. [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
  5286. [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
  5287. [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
  5288. [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
  5289. } },
  5290. { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
  5291. [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
  5292. [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
  5293. [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
  5294. [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
  5295. [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
  5296. [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
  5297. [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
  5298. [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
  5299. [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
  5300. [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
  5301. [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
  5302. [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
  5303. [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
  5304. [13] = RCAR_GP_PIN(5, 1), /* RX0 */
  5305. [14] = RCAR_GP_PIN(5, 2), /* TX0 */
  5306. [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
  5307. [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
  5308. [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
  5309. [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
  5310. [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
  5311. [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
  5312. [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
  5313. [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
  5314. [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
  5315. [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
  5316. [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
  5317. [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
  5318. [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
  5319. [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
  5320. [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
  5321. [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
  5322. [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
  5323. } },
  5324. { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
  5325. [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
  5326. [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
  5327. [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
  5328. [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
  5329. [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
  5330. [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
  5331. [ 6] = PIN_MLB_REF, /* MLB_REF */
  5332. [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
  5333. [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
  5334. [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
  5335. [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
  5336. [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
  5337. [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
  5338. [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
  5339. [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
  5340. [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
  5341. [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
  5342. [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
  5343. [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
  5344. [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
  5345. [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
  5346. [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
  5347. [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
  5348. [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
  5349. [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
  5350. [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
  5351. [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
  5352. [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
  5353. [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
  5354. [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
  5355. [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
  5356. [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
  5357. } },
  5358. { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
  5359. [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
  5360. [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
  5361. [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
  5362. [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
  5363. [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
  5364. [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
  5365. [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
  5366. [ 7] = SH_PFC_PIN_NONE,
  5367. [ 8] = SH_PFC_PIN_NONE,
  5368. [ 9] = SH_PFC_PIN_NONE,
  5369. [10] = SH_PFC_PIN_NONE,
  5370. [11] = SH_PFC_PIN_NONE,
  5371. [12] = SH_PFC_PIN_NONE,
  5372. [13] = SH_PFC_PIN_NONE,
  5373. [14] = SH_PFC_PIN_NONE,
  5374. [15] = SH_PFC_PIN_NONE,
  5375. [16] = SH_PFC_PIN_NONE,
  5376. [17] = SH_PFC_PIN_NONE,
  5377. [18] = SH_PFC_PIN_NONE,
  5378. [19] = SH_PFC_PIN_NONE,
  5379. [20] = SH_PFC_PIN_NONE,
  5380. [21] = SH_PFC_PIN_NONE,
  5381. [22] = SH_PFC_PIN_NONE,
  5382. [23] = SH_PFC_PIN_NONE,
  5383. [24] = SH_PFC_PIN_NONE,
  5384. [25] = SH_PFC_PIN_NONE,
  5385. [26] = SH_PFC_PIN_NONE,
  5386. [27] = SH_PFC_PIN_NONE,
  5387. [28] = SH_PFC_PIN_NONE,
  5388. [29] = SH_PFC_PIN_NONE,
  5389. [30] = SH_PFC_PIN_NONE,
  5390. [31] = SH_PFC_PIN_NONE,
  5391. } },
  5392. { /* sentinel */ },
  5393. };
  5394. static const struct sh_pfc_soc_operations r8a77950_pfc_ops = {
  5395. .pin_to_pocctrl = r8a77950_pin_to_pocctrl,
  5396. .get_bias = rcar_pinmux_get_bias,
  5397. .set_bias = rcar_pinmux_set_bias,
  5398. };
  5399. const struct sh_pfc_soc_info r8a77950_pinmux_info = {
  5400. .name = "r8a77950_pfc",
  5401. .ops = &r8a77950_pfc_ops,
  5402. .unlock_reg = 0xe6060000, /* PMMR */
  5403. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5404. .pins = pinmux_pins,
  5405. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5406. .groups = pinmux_groups,
  5407. .nr_groups = ARRAY_SIZE(pinmux_groups),
  5408. .functions = pinmux_functions,
  5409. .nr_functions = ARRAY_SIZE(pinmux_functions),
  5410. .cfg_regs = pinmux_config_regs,
  5411. .drive_regs = pinmux_drive_regs,
  5412. .bias_regs = pinmux_bias_regs,
  5413. .ioctrl_regs = pinmux_ioctrl_regs,
  5414. .pinmux_data = pinmux_data,
  5415. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5416. };