pinctrl-st.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
  4. * Authors:
  5. * Srinivas Kandagatla <[email protected]>
  6. */
  7. #include <linux/init.h>
  8. #include <linux/module.h>
  9. #include <linux/slab.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/of_address.h>
  15. #include <linux/gpio/driver.h>
  16. #include <linux/regmap.h>
  17. #include <linux/mfd/syscon.h>
  18. #include <linux/pinctrl/pinctrl.h>
  19. #include <linux/pinctrl/pinmux.h>
  20. #include <linux/pinctrl/pinconf.h>
  21. #include <linux/platform_device.h>
  22. #include "core.h"
  23. /* PIO Block registers */
  24. /* PIO output */
  25. #define REG_PIO_POUT 0x00
  26. /* Set bits of POUT */
  27. #define REG_PIO_SET_POUT 0x04
  28. /* Clear bits of POUT */
  29. #define REG_PIO_CLR_POUT 0x08
  30. /* PIO input */
  31. #define REG_PIO_PIN 0x10
  32. /* PIO configuration */
  33. #define REG_PIO_PC(n) (0x20 + (n) * 0x10)
  34. /* Set bits of PC[2:0] */
  35. #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)
  36. /* Clear bits of PC[2:0] */
  37. #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)
  38. /* PIO input comparison */
  39. #define REG_PIO_PCOMP 0x50
  40. /* Set bits of PCOMP */
  41. #define REG_PIO_SET_PCOMP 0x54
  42. /* Clear bits of PCOMP */
  43. #define REG_PIO_CLR_PCOMP 0x58
  44. /* PIO input comparison mask */
  45. #define REG_PIO_PMASK 0x60
  46. /* Set bits of PMASK */
  47. #define REG_PIO_SET_PMASK 0x64
  48. /* Clear bits of PMASK */
  49. #define REG_PIO_CLR_PMASK 0x68
  50. #define ST_GPIO_DIRECTION_BIDIR 0x1
  51. #define ST_GPIO_DIRECTION_OUT 0x2
  52. #define ST_GPIO_DIRECTION_IN 0x4
  53. /*
  54. * Packed style retime configuration.
  55. * There are two registers cfg0 and cfg1 in this style for each bank.
  56. * Each field in this register is 8 bit corresponding to 8 pins in the bank.
  57. */
  58. #define RT_P_CFGS_PER_BANK 2
  59. #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)
  60. #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)
  61. #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)
  62. #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)
  63. #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)
  64. #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)
  65. #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)
  66. /*
  67. * Dedicated style retime Configuration register
  68. * each register is dedicated per pin.
  69. */
  70. #define RT_D_CFGS_PER_BANK 8
  71. #define RT_D_CFG_CLK_SHIFT 0
  72. #define RT_D_CFG_CLK_MASK (0x3 << 0)
  73. #define RT_D_CFG_CLKNOTDATA_SHIFT 2
  74. #define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
  75. #define RT_D_CFG_DELAY_SHIFT 3
  76. #define RT_D_CFG_DELAY_MASK (0xf << 3)
  77. #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7
  78. #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
  79. #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8
  80. #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
  81. #define RT_D_CFG_INVERTCLK_SHIFT 9
  82. #define RT_D_CFG_INVERTCLK_MASK BIT(9)
  83. #define RT_D_CFG_RETIME_SHIFT 10
  84. #define RT_D_CFG_RETIME_MASK BIT(10)
  85. /*
  86. * Pinconf is represented in an opaque unsigned long variable.
  87. * Below is the bit allocation details for each possible configuration.
  88. * All the bit fields can be encapsulated into four variables
  89. * (direction, retime-type, retime-clk, retime-delay)
  90. *
  91. * +----------------+
  92. *[31:28]| reserved-3 |
  93. * +----------------+-------------
  94. *[27] | oe | |
  95. * +----------------+ v
  96. *[26] | pu | [Direction ]
  97. * +----------------+ ^
  98. *[25] | od | |
  99. * +----------------+-------------
  100. *[24] | reserved-2 |
  101. * +----------------+-------------
  102. *[23] | retime | |
  103. * +----------------+ |
  104. *[22] | retime-invclk | |
  105. * +----------------+ v
  106. *[21] |retime-clknotdat| [Retime-type ]
  107. * +----------------+ ^
  108. *[20] | retime-de | |
  109. * +----------------+-------------
  110. *[19:18]| retime-clk |------>[Retime-Clk ]
  111. * +----------------+
  112. *[17:16]| reserved-1 |
  113. * +----------------+
  114. *[15..0]| retime-delay |------>[Retime Delay]
  115. * +----------------+
  116. */
  117. #define ST_PINCONF_UNPACK(conf, param)\
  118. ((conf >> ST_PINCONF_ ##param ##_SHIFT) \
  119. & ST_PINCONF_ ##param ##_MASK)
  120. #define ST_PINCONF_PACK(conf, val, param) (conf |=\
  121. ((val & ST_PINCONF_ ##param ##_MASK) << \
  122. ST_PINCONF_ ##param ##_SHIFT))
  123. /* Output enable */
  124. #define ST_PINCONF_OE_MASK 0x1
  125. #define ST_PINCONF_OE_SHIFT 27
  126. #define ST_PINCONF_OE BIT(27)
  127. #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)
  128. #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
  129. /* Pull Up */
  130. #define ST_PINCONF_PU_MASK 0x1
  131. #define ST_PINCONF_PU_SHIFT 26
  132. #define ST_PINCONF_PU BIT(26)
  133. #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
  134. #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
  135. /* Open Drain */
  136. #define ST_PINCONF_OD_MASK 0x1
  137. #define ST_PINCONF_OD_SHIFT 25
  138. #define ST_PINCONF_OD BIT(25)
  139. #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)
  140. #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)
  141. #define ST_PINCONF_RT_MASK 0x1
  142. #define ST_PINCONF_RT_SHIFT 23
  143. #define ST_PINCONF_RT BIT(23)
  144. #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
  145. #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
  146. #define ST_PINCONF_RT_INVERTCLK_MASK 0x1
  147. #define ST_PINCONF_RT_INVERTCLK_SHIFT 22
  148. #define ST_PINCONF_RT_INVERTCLK BIT(22)
  149. #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
  150. ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
  151. #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
  152. ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
  153. #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1
  154. #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21
  155. #define ST_PINCONF_RT_CLKNOTDATA BIT(21)
  156. #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \
  157. ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
  158. #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
  159. ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
  160. #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1
  161. #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
  162. #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)
  163. #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
  164. ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
  165. #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
  166. ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
  167. #define ST_PINCONF_RT_CLK_MASK 0x3
  168. #define ST_PINCONF_RT_CLK_SHIFT 18
  169. #define ST_PINCONF_RT_CLK BIT(18)
  170. #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)
  171. #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
  172. /* RETIME_DELAY in Pico Secs */
  173. #define ST_PINCONF_RT_DELAY_MASK 0xffff
  174. #define ST_PINCONF_RT_DELAY_SHIFT 0
  175. #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
  176. #define ST_PINCONF_PACK_RT_DELAY(conf, val) \
  177. ST_PINCONF_PACK(conf, val, RT_DELAY)
  178. #define ST_GPIO_PINS_PER_BANK (8)
  179. #define OF_GPIO_ARGS_MIN (4)
  180. #define OF_RT_ARGS_MIN (2)
  181. #define gpio_range_to_bank(chip) \
  182. container_of(chip, struct st_gpio_bank, range)
  183. #define pc_to_bank(pc) \
  184. container_of(pc, struct st_gpio_bank, pc)
  185. enum st_retime_style {
  186. st_retime_style_none,
  187. st_retime_style_packed,
  188. st_retime_style_dedicated,
  189. };
  190. struct st_retime_dedicated {
  191. struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
  192. };
  193. struct st_retime_packed {
  194. struct regmap_field *clk1notclk0;
  195. struct regmap_field *delay_0;
  196. struct regmap_field *delay_1;
  197. struct regmap_field *invertclk;
  198. struct regmap_field *retime;
  199. struct regmap_field *clknotdata;
  200. struct regmap_field *double_edge;
  201. };
  202. struct st_pio_control {
  203. u32 rt_pin_mask;
  204. struct regmap_field *alt, *oe, *pu, *od;
  205. /* retiming */
  206. union {
  207. struct st_retime_packed rt_p;
  208. struct st_retime_dedicated rt_d;
  209. } rt;
  210. };
  211. struct st_pctl_data {
  212. const enum st_retime_style rt_style;
  213. const unsigned int *input_delays;
  214. const int ninput_delays;
  215. const unsigned int *output_delays;
  216. const int noutput_delays;
  217. /* register offset information */
  218. const int alt, oe, pu, od, rt;
  219. };
  220. struct st_pinconf {
  221. int pin;
  222. const char *name;
  223. unsigned long config;
  224. int altfunc;
  225. };
  226. struct st_pmx_func {
  227. const char *name;
  228. const char **groups;
  229. unsigned ngroups;
  230. };
  231. struct st_pctl_group {
  232. const char *name;
  233. unsigned int *pins;
  234. unsigned npins;
  235. struct st_pinconf *pin_conf;
  236. };
  237. /*
  238. * Edge triggers are not supported at hardware level, it is supported by
  239. * software by exploiting the level trigger support in hardware.
  240. * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
  241. * of each gpio pin in a GPIO bank.
  242. *
  243. * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
  244. * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
  245. *
  246. * bit allocation per pin is:
  247. * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
  248. * --------------------------------------------------------
  249. * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
  250. * --------------------------------------------------------
  251. *
  252. * A pin can have one of following the values in its edge configuration field.
  253. *
  254. * ------- ----------------------------
  255. * [0-3] - Description
  256. * ------- ----------------------------
  257. * 0000 - No edge IRQ.
  258. * 0001 - Falling edge IRQ.
  259. * 0010 - Rising edge IRQ.
  260. * 0011 - Rising and Falling edge IRQ.
  261. * ------- ----------------------------
  262. */
  263. #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
  264. #define ST_IRQ_EDGE_MASK 0xf
  265. #define ST_IRQ_EDGE_FALLING BIT(0)
  266. #define ST_IRQ_EDGE_RISING BIT(1)
  267. #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
  268. #define ST_IRQ_RISING_EDGE_CONF(pin) \
  269. (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
  270. #define ST_IRQ_FALLING_EDGE_CONF(pin) \
  271. (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
  272. #define ST_IRQ_BOTH_EDGE_CONF(pin) \
  273. (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
  274. #define ST_IRQ_EDGE_CONF(conf, pin) \
  275. (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
  276. struct st_gpio_bank {
  277. struct gpio_chip gpio_chip;
  278. struct pinctrl_gpio_range range;
  279. void __iomem *base;
  280. struct st_pio_control pc;
  281. unsigned long irq_edge_conf;
  282. spinlock_t lock;
  283. };
  284. struct st_pinctrl {
  285. struct device *dev;
  286. struct pinctrl_dev *pctl;
  287. struct st_gpio_bank *banks;
  288. int nbanks;
  289. struct st_pmx_func *functions;
  290. int nfunctions;
  291. struct st_pctl_group *groups;
  292. int ngroups;
  293. struct regmap *regmap;
  294. const struct st_pctl_data *data;
  295. void __iomem *irqmux_base;
  296. };
  297. /* SOC specific data */
  298. static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,
  299. 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
  300. static const struct st_pctl_data stih407_data = {
  301. .rt_style = st_retime_style_dedicated,
  302. .input_delays = stih407_delays,
  303. .ninput_delays = ARRAY_SIZE(stih407_delays),
  304. .output_delays = stih407_delays,
  305. .noutput_delays = ARRAY_SIZE(stih407_delays),
  306. .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
  307. };
  308. static const struct st_pctl_data stih407_flashdata = {
  309. .rt_style = st_retime_style_none,
  310. .input_delays = stih407_delays,
  311. .ninput_delays = ARRAY_SIZE(stih407_delays),
  312. .output_delays = stih407_delays,
  313. .noutput_delays = ARRAY_SIZE(stih407_delays),
  314. .alt = 0,
  315. .oe = -1, /* Not Available */
  316. .pu = -1, /* Not Available */
  317. .od = 60,
  318. .rt = 100,
  319. };
  320. static struct st_pio_control *st_get_pio_control(
  321. struct pinctrl_dev *pctldev, int pin)
  322. {
  323. struct pinctrl_gpio_range *range =
  324. pinctrl_find_gpio_range_from_pin(pctldev, pin);
  325. struct st_gpio_bank *bank = gpio_range_to_bank(range);
  326. return &bank->pc;
  327. }
  328. /* Low level functions.. */
  329. static inline int st_gpio_bank(int gpio)
  330. {
  331. return gpio/ST_GPIO_PINS_PER_BANK;
  332. }
  333. static inline int st_gpio_pin(int gpio)
  334. {
  335. return gpio%ST_GPIO_PINS_PER_BANK;
  336. }
  337. static void st_pinconf_set_config(struct st_pio_control *pc,
  338. int pin, unsigned long config)
  339. {
  340. struct regmap_field *output_enable = pc->oe;
  341. struct regmap_field *pull_up = pc->pu;
  342. struct regmap_field *open_drain = pc->od;
  343. unsigned int oe_value, pu_value, od_value;
  344. unsigned long mask = BIT(pin);
  345. if (output_enable) {
  346. regmap_field_read(output_enable, &oe_value);
  347. oe_value &= ~mask;
  348. if (config & ST_PINCONF_OE)
  349. oe_value |= mask;
  350. regmap_field_write(output_enable, oe_value);
  351. }
  352. if (pull_up) {
  353. regmap_field_read(pull_up, &pu_value);
  354. pu_value &= ~mask;
  355. if (config & ST_PINCONF_PU)
  356. pu_value |= mask;
  357. regmap_field_write(pull_up, pu_value);
  358. }
  359. if (open_drain) {
  360. regmap_field_read(open_drain, &od_value);
  361. od_value &= ~mask;
  362. if (config & ST_PINCONF_OD)
  363. od_value |= mask;
  364. regmap_field_write(open_drain, od_value);
  365. }
  366. }
  367. static void st_pctl_set_function(struct st_pio_control *pc,
  368. int pin_id, int function)
  369. {
  370. struct regmap_field *alt = pc->alt;
  371. unsigned int val;
  372. int pin = st_gpio_pin(pin_id);
  373. int offset = pin * 4;
  374. if (!alt)
  375. return;
  376. regmap_field_read(alt, &val);
  377. val &= ~(0xf << offset);
  378. val |= function << offset;
  379. regmap_field_write(alt, val);
  380. }
  381. static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
  382. {
  383. struct regmap_field *alt = pc->alt;
  384. unsigned int val;
  385. int offset = pin * 4;
  386. if (!alt)
  387. return 0;
  388. regmap_field_read(alt, &val);
  389. return (val >> offset) & 0xf;
  390. }
  391. static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
  392. const struct st_pctl_data *data, unsigned long config)
  393. {
  394. const unsigned int *delay_times;
  395. int num_delay_times, i, closest_index = -1;
  396. unsigned int closest_divergence = UINT_MAX;
  397. if (ST_PINCONF_UNPACK_OE(config)) {
  398. delay_times = data->output_delays;
  399. num_delay_times = data->noutput_delays;
  400. } else {
  401. delay_times = data->input_delays;
  402. num_delay_times = data->ninput_delays;
  403. }
  404. for (i = 0; i < num_delay_times; i++) {
  405. unsigned int divergence = abs(delay - delay_times[i]);
  406. if (divergence == 0)
  407. return i;
  408. if (divergence < closest_divergence) {
  409. closest_divergence = divergence;
  410. closest_index = i;
  411. }
  412. }
  413. pr_warn("Attempt to set delay %d, closest available %d\n",
  414. delay, delay_times[closest_index]);
  415. return closest_index;
  416. }
  417. static unsigned long st_pinconf_bit_to_delay(unsigned int index,
  418. const struct st_pctl_data *data, unsigned long output)
  419. {
  420. const unsigned int *delay_times;
  421. int num_delay_times;
  422. if (output) {
  423. delay_times = data->output_delays;
  424. num_delay_times = data->noutput_delays;
  425. } else {
  426. delay_times = data->input_delays;
  427. num_delay_times = data->ninput_delays;
  428. }
  429. if (index < num_delay_times) {
  430. return delay_times[index];
  431. } else {
  432. pr_warn("Delay not found in/out delay list\n");
  433. return 0;
  434. }
  435. }
  436. static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
  437. int enable, int pin)
  438. {
  439. unsigned int val = 0;
  440. regmap_field_read(field, &val);
  441. if (enable)
  442. val |= BIT(pin);
  443. else
  444. val &= ~BIT(pin);
  445. regmap_field_write(field, val);
  446. }
  447. static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
  448. struct st_pio_control *pc, unsigned long config, int pin)
  449. {
  450. const struct st_pctl_data *data = info->data;
  451. struct st_retime_packed *rt_p = &pc->rt.rt_p;
  452. unsigned int delay;
  453. st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
  454. ST_PINCONF_UNPACK_RT_CLK(config), pin);
  455. st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
  456. ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
  457. st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
  458. ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
  459. st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
  460. ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
  461. st_regmap_field_bit_set_clear_pin(rt_p->retime,
  462. ST_PINCONF_UNPACK_RT(config), pin);
  463. delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
  464. data, config);
  465. /* 2 bit delay, lsb */
  466. st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
  467. /* 2 bit delay, msb */
  468. st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
  469. }
  470. static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
  471. struct st_pio_control *pc, unsigned long config, int pin)
  472. {
  473. int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
  474. int clk = ST_PINCONF_UNPACK_RT_CLK(config);
  475. int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
  476. int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
  477. int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config);
  478. int retime = ST_PINCONF_UNPACK_RT(config);
  479. unsigned long delay = st_pinconf_delay_to_bit(
  480. ST_PINCONF_UNPACK_RT_DELAY(config),
  481. info->data, config);
  482. struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
  483. unsigned long retime_config =
  484. ((clk) << RT_D_CFG_CLK_SHIFT) |
  485. ((delay) << RT_D_CFG_DELAY_SHIFT) |
  486. ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
  487. ((retime) << RT_D_CFG_RETIME_SHIFT) |
  488. ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
  489. ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
  490. ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
  491. regmap_field_write(rt_d->rt[pin], retime_config);
  492. }
  493. static void st_pinconf_get_direction(struct st_pio_control *pc,
  494. int pin, unsigned long *config)
  495. {
  496. unsigned int oe_value, pu_value, od_value;
  497. if (pc->oe) {
  498. regmap_field_read(pc->oe, &oe_value);
  499. if (oe_value & BIT(pin))
  500. ST_PINCONF_PACK_OE(*config);
  501. }
  502. if (pc->pu) {
  503. regmap_field_read(pc->pu, &pu_value);
  504. if (pu_value & BIT(pin))
  505. ST_PINCONF_PACK_PU(*config);
  506. }
  507. if (pc->od) {
  508. regmap_field_read(pc->od, &od_value);
  509. if (od_value & BIT(pin))
  510. ST_PINCONF_PACK_OD(*config);
  511. }
  512. }
  513. static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
  514. struct st_pio_control *pc, int pin, unsigned long *config)
  515. {
  516. const struct st_pctl_data *data = info->data;
  517. struct st_retime_packed *rt_p = &pc->rt.rt_p;
  518. unsigned int delay_bits, delay, delay0, delay1, val;
  519. int output = ST_PINCONF_UNPACK_OE(*config);
  520. if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
  521. ST_PINCONF_PACK_RT(*config);
  522. if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
  523. ST_PINCONF_PACK_RT_CLK(*config, 1);
  524. if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
  525. ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
  526. if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
  527. ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
  528. if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
  529. ST_PINCONF_PACK_RT_INVERTCLK(*config);
  530. regmap_field_read(rt_p->delay_0, &delay0);
  531. regmap_field_read(rt_p->delay_1, &delay1);
  532. delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
  533. (((delay0 & BIT(pin)) ? 1 : 0));
  534. delay = st_pinconf_bit_to_delay(delay_bits, data, output);
  535. ST_PINCONF_PACK_RT_DELAY(*config, delay);
  536. return 0;
  537. }
  538. static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
  539. struct st_pio_control *pc, int pin, unsigned long *config)
  540. {
  541. unsigned int value;
  542. unsigned long delay_bits, delay, rt_clk;
  543. int output = ST_PINCONF_UNPACK_OE(*config);
  544. struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
  545. regmap_field_read(rt_d->rt[pin], &value);
  546. rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
  547. ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
  548. delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
  549. delay = st_pinconf_bit_to_delay(delay_bits, info->data, output);
  550. ST_PINCONF_PACK_RT_DELAY(*config, delay);
  551. if (value & RT_D_CFG_CLKNOTDATA_MASK)
  552. ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
  553. if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
  554. ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
  555. if (value & RT_D_CFG_INVERTCLK_MASK)
  556. ST_PINCONF_PACK_RT_INVERTCLK(*config);
  557. if (value & RT_D_CFG_RETIME_MASK)
  558. ST_PINCONF_PACK_RT(*config);
  559. return 0;
  560. }
  561. /* GPIO related functions */
  562. static inline void __st_gpio_set(struct st_gpio_bank *bank,
  563. unsigned offset, int value)
  564. {
  565. if (value)
  566. writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
  567. else
  568. writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
  569. }
  570. static void st_gpio_direction(struct st_gpio_bank *bank,
  571. unsigned int gpio, unsigned int direction)
  572. {
  573. int offset = st_gpio_pin(gpio);
  574. int i = 0;
  575. /**
  576. * There are three configuration registers (PIOn_PC0, PIOn_PC1
  577. * and PIOn_PC2) for each port. These are used to configure the
  578. * PIO port pins. Each pin can be configured as an input, output,
  579. * bidirectional, or alternative function pin. Three bits, one bit
  580. * from each of the three registers, configure the corresponding bit of
  581. * the port. Valid bit settings is:
  582. *
  583. * PC2 PC1 PC0 Direction.
  584. * 0 0 0 [Input Weak pull-up]
  585. * 0 0 or 1 1 [Bidirection]
  586. * 0 1 0 [Output]
  587. * 1 0 0 [Input]
  588. *
  589. * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
  590. * individually.
  591. */
  592. for (i = 0; i <= 2; i++) {
  593. if (direction & BIT(i))
  594. writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
  595. else
  596. writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
  597. }
  598. }
  599. static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
  600. {
  601. struct st_gpio_bank *bank = gpiochip_get_data(chip);
  602. return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
  603. }
  604. static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  605. {
  606. struct st_gpio_bank *bank = gpiochip_get_data(chip);
  607. __st_gpio_set(bank, offset, value);
  608. }
  609. static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  610. {
  611. pinctrl_gpio_direction_input(chip->base + offset);
  612. return 0;
  613. }
  614. static int st_gpio_direction_output(struct gpio_chip *chip,
  615. unsigned offset, int value)
  616. {
  617. struct st_gpio_bank *bank = gpiochip_get_data(chip);
  618. __st_gpio_set(bank, offset, value);
  619. pinctrl_gpio_direction_output(chip->base + offset);
  620. return 0;
  621. }
  622. static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  623. {
  624. struct st_gpio_bank *bank = gpiochip_get_data(chip);
  625. struct st_pio_control pc = bank->pc;
  626. unsigned long config;
  627. unsigned int direction = 0;
  628. unsigned int function;
  629. unsigned int value;
  630. int i = 0;
  631. /* Alternate function direction is handled by Pinctrl */
  632. function = st_pctl_get_pin_function(&pc, offset);
  633. if (function) {
  634. st_pinconf_get_direction(&pc, offset, &config);
  635. if (ST_PINCONF_UNPACK_OE(config))
  636. return GPIO_LINE_DIRECTION_OUT;
  637. return GPIO_LINE_DIRECTION_IN;
  638. }
  639. /*
  640. * GPIO direction is handled differently
  641. * - See st_gpio_direction() above for an explanation
  642. */
  643. for (i = 0; i <= 2; i++) {
  644. value = readl(bank->base + REG_PIO_PC(i));
  645. direction |= ((value >> offset) & 0x1) << i;
  646. }
  647. if (direction == ST_GPIO_DIRECTION_IN)
  648. return GPIO_LINE_DIRECTION_IN;
  649. return GPIO_LINE_DIRECTION_OUT;
  650. }
  651. /* Pinctrl Groups */
  652. static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
  653. {
  654. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  655. return info->ngroups;
  656. }
  657. static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
  658. unsigned selector)
  659. {
  660. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  661. return info->groups[selector].name;
  662. }
  663. static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
  664. unsigned selector, const unsigned **pins, unsigned *npins)
  665. {
  666. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  667. if (selector >= info->ngroups)
  668. return -EINVAL;
  669. *pins = info->groups[selector].pins;
  670. *npins = info->groups[selector].npins;
  671. return 0;
  672. }
  673. static inline const struct st_pctl_group *st_pctl_find_group_by_name(
  674. const struct st_pinctrl *info, const char *name)
  675. {
  676. int i;
  677. for (i = 0; i < info->ngroups; i++) {
  678. if (!strcmp(info->groups[i].name, name))
  679. return &info->groups[i];
  680. }
  681. return NULL;
  682. }
  683. static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
  684. struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
  685. {
  686. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  687. const struct st_pctl_group *grp;
  688. struct device *dev = info->dev;
  689. struct pinctrl_map *new_map;
  690. struct device_node *parent;
  691. int map_num, i;
  692. grp = st_pctl_find_group_by_name(info, np->name);
  693. if (!grp) {
  694. dev_err(dev, "unable to find group for node %pOFn\n", np);
  695. return -EINVAL;
  696. }
  697. map_num = grp->npins + 1;
  698. new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL);
  699. if (!new_map)
  700. return -ENOMEM;
  701. parent = of_get_parent(np);
  702. if (!parent) {
  703. devm_kfree(dev, new_map);
  704. return -EINVAL;
  705. }
  706. *map = new_map;
  707. *num_maps = map_num;
  708. new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
  709. new_map[0].data.mux.function = parent->name;
  710. new_map[0].data.mux.group = np->name;
  711. of_node_put(parent);
  712. /* create config map per pin */
  713. new_map++;
  714. for (i = 0; i < grp->npins; i++) {
  715. new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
  716. new_map[i].data.configs.group_or_pin =
  717. pin_get_name(pctldev, grp->pins[i]);
  718. new_map[i].data.configs.configs = &grp->pin_conf[i].config;
  719. new_map[i].data.configs.num_configs = 1;
  720. }
  721. dev_info(dev, "maps: function %s group %s num %d\n",
  722. (*map)->data.mux.function, grp->name, map_num);
  723. return 0;
  724. }
  725. static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
  726. struct pinctrl_map *map, unsigned num_maps)
  727. {
  728. }
  729. static const struct pinctrl_ops st_pctlops = {
  730. .get_groups_count = st_pctl_get_groups_count,
  731. .get_group_pins = st_pctl_get_group_pins,
  732. .get_group_name = st_pctl_get_group_name,
  733. .dt_node_to_map = st_pctl_dt_node_to_map,
  734. .dt_free_map = st_pctl_dt_free_map,
  735. };
  736. /* Pinmux */
  737. static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
  738. {
  739. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  740. return info->nfunctions;
  741. }
  742. static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
  743. unsigned selector)
  744. {
  745. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  746. return info->functions[selector].name;
  747. }
  748. static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
  749. unsigned selector, const char * const **grps, unsigned * const ngrps)
  750. {
  751. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  752. *grps = info->functions[selector].groups;
  753. *ngrps = info->functions[selector].ngroups;
  754. return 0;
  755. }
  756. static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
  757. unsigned group)
  758. {
  759. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  760. struct st_pinconf *conf = info->groups[group].pin_conf;
  761. struct st_pio_control *pc;
  762. int i;
  763. for (i = 0; i < info->groups[group].npins; i++) {
  764. pc = st_get_pio_control(pctldev, conf[i].pin);
  765. st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
  766. }
  767. return 0;
  768. }
  769. static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
  770. struct pinctrl_gpio_range *range, unsigned gpio,
  771. bool input)
  772. {
  773. struct st_gpio_bank *bank = gpio_range_to_bank(range);
  774. /*
  775. * When a PIO bank is used in its primary function mode (altfunc = 0)
  776. * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
  777. * for the primary PIO functions are driven by the related PIO block
  778. */
  779. st_pctl_set_function(&bank->pc, gpio, 0);
  780. st_gpio_direction(bank, gpio, input ?
  781. ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
  782. return 0;
  783. }
  784. static const struct pinmux_ops st_pmxops = {
  785. .get_functions_count = st_pmx_get_funcs_count,
  786. .get_function_name = st_pmx_get_fname,
  787. .get_function_groups = st_pmx_get_groups,
  788. .set_mux = st_pmx_set_mux,
  789. .gpio_set_direction = st_pmx_set_gpio_direction,
  790. .strict = true,
  791. };
  792. /* Pinconf */
  793. static void st_pinconf_get_retime(struct st_pinctrl *info,
  794. struct st_pio_control *pc, int pin, unsigned long *config)
  795. {
  796. if (info->data->rt_style == st_retime_style_packed)
  797. st_pinconf_get_retime_packed(info, pc, pin, config);
  798. else if (info->data->rt_style == st_retime_style_dedicated)
  799. if ((BIT(pin) & pc->rt_pin_mask))
  800. st_pinconf_get_retime_dedicated(info, pc,
  801. pin, config);
  802. }
  803. static void st_pinconf_set_retime(struct st_pinctrl *info,
  804. struct st_pio_control *pc, int pin, unsigned long config)
  805. {
  806. if (info->data->rt_style == st_retime_style_packed)
  807. st_pinconf_set_retime_packed(info, pc, config, pin);
  808. else if (info->data->rt_style == st_retime_style_dedicated)
  809. if ((BIT(pin) & pc->rt_pin_mask))
  810. st_pinconf_set_retime_dedicated(info, pc,
  811. config, pin);
  812. }
  813. static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
  814. unsigned long *configs, unsigned num_configs)
  815. {
  816. int pin = st_gpio_pin(pin_id);
  817. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  818. struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
  819. int i;
  820. for (i = 0; i < num_configs; i++) {
  821. st_pinconf_set_config(pc, pin, configs[i]);
  822. st_pinconf_set_retime(info, pc, pin, configs[i]);
  823. } /* for each config */
  824. return 0;
  825. }
  826. static int st_pinconf_get(struct pinctrl_dev *pctldev,
  827. unsigned pin_id, unsigned long *config)
  828. {
  829. int pin = st_gpio_pin(pin_id);
  830. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  831. struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
  832. *config = 0;
  833. st_pinconf_get_direction(pc, pin, config);
  834. st_pinconf_get_retime(info, pc, pin, config);
  835. return 0;
  836. }
  837. static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
  838. struct seq_file *s, unsigned pin_id)
  839. {
  840. struct st_pio_control *pc;
  841. unsigned long config;
  842. unsigned int function;
  843. int offset = st_gpio_pin(pin_id);
  844. char f[16];
  845. int oe;
  846. mutex_unlock(&pctldev->mutex);
  847. pc = st_get_pio_control(pctldev, pin_id);
  848. st_pinconf_get(pctldev, pin_id, &config);
  849. mutex_lock(&pctldev->mutex);
  850. function = st_pctl_get_pin_function(pc, offset);
  851. if (function)
  852. snprintf(f, 10, "Alt Fn %u", function);
  853. else
  854. snprintf(f, 5, "GPIO");
  855. oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset);
  856. seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
  857. "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
  858. "de:%ld,rt-clk:%ld,rt-delay:%ld]",
  859. (oe == GPIO_LINE_DIRECTION_OUT),
  860. ST_PINCONF_UNPACK_PU(config),
  861. ST_PINCONF_UNPACK_OD(config),
  862. f,
  863. ST_PINCONF_UNPACK_RT(config),
  864. ST_PINCONF_UNPACK_RT_INVERTCLK(config),
  865. ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
  866. ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
  867. ST_PINCONF_UNPACK_RT_CLK(config),
  868. ST_PINCONF_UNPACK_RT_DELAY(config));
  869. }
  870. static const struct pinconf_ops st_confops = {
  871. .pin_config_get = st_pinconf_get,
  872. .pin_config_set = st_pinconf_set,
  873. .pin_config_dbg_show = st_pinconf_dbg_show,
  874. };
  875. static void st_pctl_dt_child_count(struct st_pinctrl *info,
  876. struct device_node *np)
  877. {
  878. struct device_node *child;
  879. for_each_child_of_node(np, child) {
  880. if (of_property_read_bool(child, "gpio-controller")) {
  881. info->nbanks++;
  882. } else {
  883. info->nfunctions++;
  884. info->ngroups += of_get_child_count(child);
  885. }
  886. }
  887. }
  888. static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
  889. int bank, struct st_pio_control *pc)
  890. {
  891. struct device *dev = info->dev;
  892. struct regmap *rm = info->regmap;
  893. const struct st_pctl_data *data = info->data;
  894. /* 2 registers per bank */
  895. int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
  896. struct st_retime_packed *rt_p = &pc->rt.rt_p;
  897. /* cfg0 */
  898. struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
  899. struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
  900. struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
  901. /* cfg1 */
  902. struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
  903. struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
  904. struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
  905. struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
  906. rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
  907. rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0);
  908. rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
  909. rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
  910. rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
  911. rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
  912. rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
  913. if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
  914. IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
  915. IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
  916. IS_ERR(rt_p->double_edge))
  917. return -EINVAL;
  918. return 0;
  919. }
  920. static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
  921. int bank, struct st_pio_control *pc)
  922. {
  923. struct device *dev = info->dev;
  924. struct regmap *rm = info->regmap;
  925. const struct st_pctl_data *data = info->data;
  926. /* 8 registers per bank */
  927. int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
  928. struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
  929. unsigned int j;
  930. u32 pin_mask = pc->rt_pin_mask;
  931. for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
  932. if (BIT(j) & pin_mask) {
  933. struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
  934. rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
  935. if (IS_ERR(rt_d->rt[j]))
  936. return -EINVAL;
  937. reg_offset += 4;
  938. }
  939. }
  940. return 0;
  941. }
  942. static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
  943. int bank, struct st_pio_control *pc)
  944. {
  945. const struct st_pctl_data *data = info->data;
  946. if (data->rt_style == st_retime_style_packed)
  947. return st_pctl_dt_setup_retime_packed(info, bank, pc);
  948. else if (data->rt_style == st_retime_style_dedicated)
  949. return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
  950. return -EINVAL;
  951. }
  952. static struct regmap_field *st_pc_get_value(struct device *dev,
  953. struct regmap *regmap, int bank,
  954. int data, int lsb, int msb)
  955. {
  956. struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
  957. if (data < 0)
  958. return NULL;
  959. return devm_regmap_field_alloc(dev, regmap, reg);
  960. }
  961. static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
  962. struct device_node *np)
  963. {
  964. const struct st_pctl_data *data = info->data;
  965. /**
  966. * For a given shared register like OE/PU/OD, there are 8 bits per bank
  967. * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
  968. * So each register is shared across 4 banks.
  969. */
  970. int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
  971. int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
  972. struct st_pio_control *pc = &info->banks[bank].pc;
  973. struct device *dev = info->dev;
  974. struct regmap *regmap = info->regmap;
  975. pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
  976. pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
  977. pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
  978. pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
  979. /* retime avaiable for all pins by default */
  980. pc->rt_pin_mask = 0xff;
  981. of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
  982. st_pctl_dt_setup_retime(info, bank, pc);
  983. return;
  984. }
  985. static int st_pctl_dt_calculate_pin(struct st_pinctrl *info,
  986. phandle bank, unsigned int offset)
  987. {
  988. struct device_node *np;
  989. struct gpio_chip *chip;
  990. int retval = -EINVAL;
  991. int i;
  992. np = of_find_node_by_phandle(bank);
  993. if (!np)
  994. return -EINVAL;
  995. for (i = 0; i < info->nbanks; i++) {
  996. chip = &info->banks[i].gpio_chip;
  997. if (chip->of_node == np) {
  998. if (offset < chip->ngpio)
  999. retval = chip->base + offset;
  1000. break;
  1001. }
  1002. }
  1003. of_node_put(np);
  1004. return retval;
  1005. }
  1006. /*
  1007. * Each pin is represented in of the below forms.
  1008. * <bank offset mux direction rt_type rt_delay rt_clk>
  1009. */
  1010. static int st_pctl_dt_parse_groups(struct device_node *np,
  1011. struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
  1012. {
  1013. /* bank pad direction val altfunction */
  1014. const __be32 *list;
  1015. struct property *pp;
  1016. struct device *dev = info->dev;
  1017. struct st_pinconf *conf;
  1018. struct device_node *pins;
  1019. phandle bank;
  1020. unsigned int offset;
  1021. int i = 0, npins = 0, nr_props, ret = 0;
  1022. pins = of_get_child_by_name(np, "st,pins");
  1023. if (!pins)
  1024. return -ENODATA;
  1025. for_each_property_of_node(pins, pp) {
  1026. /* Skip those we do not want to proceed */
  1027. if (!strcmp(pp->name, "name"))
  1028. continue;
  1029. if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
  1030. npins++;
  1031. } else {
  1032. pr_warn("Invalid st,pins in %pOFn node\n", np);
  1033. ret = -EINVAL;
  1034. goto out_put_node;
  1035. }
  1036. }
  1037. grp->npins = npins;
  1038. grp->name = np->name;
  1039. grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL);
  1040. grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL);
  1041. if (!grp->pins || !grp->pin_conf) {
  1042. ret = -ENOMEM;
  1043. goto out_put_node;
  1044. }
  1045. /* <bank offset mux direction rt_type rt_delay rt_clk> */
  1046. for_each_property_of_node(pins, pp) {
  1047. if (!strcmp(pp->name, "name"))
  1048. continue;
  1049. nr_props = pp->length/sizeof(u32);
  1050. list = pp->value;
  1051. conf = &grp->pin_conf[i];
  1052. /* bank & offset */
  1053. bank = be32_to_cpup(list++);
  1054. offset = be32_to_cpup(list++);
  1055. conf->pin = st_pctl_dt_calculate_pin(info, bank, offset);
  1056. conf->name = pp->name;
  1057. grp->pins[i] = conf->pin;
  1058. /* mux */
  1059. conf->altfunc = be32_to_cpup(list++);
  1060. conf->config = 0;
  1061. /* direction */
  1062. conf->config |= be32_to_cpup(list++);
  1063. /* rt_type rt_delay rt_clk */
  1064. if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
  1065. /* rt_type */
  1066. conf->config |= be32_to_cpup(list++);
  1067. /* rt_delay */
  1068. conf->config |= be32_to_cpup(list++);
  1069. /* rt_clk */
  1070. if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
  1071. conf->config |= be32_to_cpup(list++);
  1072. }
  1073. i++;
  1074. }
  1075. out_put_node:
  1076. of_node_put(pins);
  1077. return ret;
  1078. }
  1079. static int st_pctl_parse_functions(struct device_node *np,
  1080. struct st_pinctrl *info, u32 index, int *grp_index)
  1081. {
  1082. struct device *dev = info->dev;
  1083. struct device_node *child;
  1084. struct st_pmx_func *func;
  1085. struct st_pctl_group *grp;
  1086. int ret, i;
  1087. func = &info->functions[index];
  1088. func->name = np->name;
  1089. func->ngroups = of_get_child_count(np);
  1090. if (func->ngroups == 0)
  1091. return dev_err_probe(dev, -EINVAL, "No groups defined\n");
  1092. func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
  1093. if (!func->groups)
  1094. return -ENOMEM;
  1095. i = 0;
  1096. for_each_child_of_node(np, child) {
  1097. func->groups[i] = child->name;
  1098. grp = &info->groups[*grp_index];
  1099. *grp_index += 1;
  1100. ret = st_pctl_dt_parse_groups(child, grp, info, i++);
  1101. if (ret) {
  1102. of_node_put(child);
  1103. return ret;
  1104. }
  1105. }
  1106. dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups);
  1107. return 0;
  1108. }
  1109. static void st_gpio_irq_mask(struct irq_data *d)
  1110. {
  1111. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1112. struct st_gpio_bank *bank = gpiochip_get_data(gc);
  1113. writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
  1114. }
  1115. static void st_gpio_irq_unmask(struct irq_data *d)
  1116. {
  1117. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1118. struct st_gpio_bank *bank = gpiochip_get_data(gc);
  1119. writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
  1120. }
  1121. static int st_gpio_irq_request_resources(struct irq_data *d)
  1122. {
  1123. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1124. st_gpio_direction_input(gc, d->hwirq);
  1125. return gpiochip_lock_as_irq(gc, d->hwirq);
  1126. }
  1127. static void st_gpio_irq_release_resources(struct irq_data *d)
  1128. {
  1129. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1130. gpiochip_unlock_as_irq(gc, d->hwirq);
  1131. }
  1132. static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
  1133. {
  1134. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1135. struct st_gpio_bank *bank = gpiochip_get_data(gc);
  1136. unsigned long flags;
  1137. int comp, pin = d->hwirq;
  1138. u32 val;
  1139. u32 pin_edge_conf = 0;
  1140. switch (type) {
  1141. case IRQ_TYPE_LEVEL_HIGH:
  1142. comp = 0;
  1143. break;
  1144. case IRQ_TYPE_EDGE_FALLING:
  1145. comp = 0;
  1146. pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
  1147. break;
  1148. case IRQ_TYPE_LEVEL_LOW:
  1149. comp = 1;
  1150. break;
  1151. case IRQ_TYPE_EDGE_RISING:
  1152. comp = 1;
  1153. pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
  1154. break;
  1155. case IRQ_TYPE_EDGE_BOTH:
  1156. comp = st_gpio_get(&bank->gpio_chip, pin);
  1157. pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
  1158. break;
  1159. default:
  1160. return -EINVAL;
  1161. }
  1162. spin_lock_irqsave(&bank->lock, flags);
  1163. bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
  1164. pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
  1165. bank->irq_edge_conf |= pin_edge_conf;
  1166. spin_unlock_irqrestore(&bank->lock, flags);
  1167. val = readl(bank->base + REG_PIO_PCOMP);
  1168. val &= ~BIT(pin);
  1169. val |= (comp << pin);
  1170. writel(val, bank->base + REG_PIO_PCOMP);
  1171. return 0;
  1172. }
  1173. /*
  1174. * As edge triggers are not supported at hardware level, it is supported by
  1175. * software by exploiting the level trigger support in hardware.
  1176. *
  1177. * Steps for detection raising edge interrupt in software.
  1178. *
  1179. * Step 1: CONFIGURE pin to detect level LOW interrupts.
  1180. *
  1181. * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
  1182. * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
  1183. * IGNORE calling the actual interrupt handler for the pin at this stage.
  1184. *
  1185. * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
  1186. * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
  1187. * DISPATCH the interrupt to the interrupt handler of the pin.
  1188. *
  1189. * step-1 ________ __________
  1190. * | | step - 3
  1191. * | |
  1192. * step -2 |_____|
  1193. *
  1194. * falling edge is also detected int the same way.
  1195. *
  1196. */
  1197. static void __gpio_irq_handler(struct st_gpio_bank *bank)
  1198. {
  1199. unsigned long port_in, port_mask, port_comp, active_irqs;
  1200. unsigned long bank_edge_mask, flags;
  1201. int n, val, ecfg;
  1202. spin_lock_irqsave(&bank->lock, flags);
  1203. bank_edge_mask = bank->irq_edge_conf;
  1204. spin_unlock_irqrestore(&bank->lock, flags);
  1205. for (;;) {
  1206. port_in = readl(bank->base + REG_PIO_PIN);
  1207. port_comp = readl(bank->base + REG_PIO_PCOMP);
  1208. port_mask = readl(bank->base + REG_PIO_PMASK);
  1209. active_irqs = (port_in ^ port_comp) & port_mask;
  1210. if (active_irqs == 0)
  1211. break;
  1212. for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
  1213. /* check if we are detecting fake edges ... */
  1214. ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
  1215. if (ecfg) {
  1216. /* edge detection. */
  1217. val = st_gpio_get(&bank->gpio_chip, n);
  1218. writel(BIT(n),
  1219. val ? bank->base + REG_PIO_SET_PCOMP :
  1220. bank->base + REG_PIO_CLR_PCOMP);
  1221. if (ecfg != ST_IRQ_EDGE_BOTH &&
  1222. !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
  1223. continue;
  1224. }
  1225. generic_handle_domain_irq(bank->gpio_chip.irq.domain, n);
  1226. }
  1227. }
  1228. }
  1229. static void st_gpio_irq_handler(struct irq_desc *desc)
  1230. {
  1231. /* interrupt dedicated per bank */
  1232. struct irq_chip *chip = irq_desc_get_chip(desc);
  1233. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  1234. struct st_gpio_bank *bank = gpiochip_get_data(gc);
  1235. chained_irq_enter(chip, desc);
  1236. __gpio_irq_handler(bank);
  1237. chained_irq_exit(chip, desc);
  1238. }
  1239. static void st_gpio_irqmux_handler(struct irq_desc *desc)
  1240. {
  1241. struct irq_chip *chip = irq_desc_get_chip(desc);
  1242. struct st_pinctrl *info = irq_desc_get_handler_data(desc);
  1243. unsigned long status;
  1244. int n;
  1245. chained_irq_enter(chip, desc);
  1246. status = readl(info->irqmux_base);
  1247. for_each_set_bit(n, &status, info->nbanks)
  1248. __gpio_irq_handler(&info->banks[n]);
  1249. chained_irq_exit(chip, desc);
  1250. }
  1251. static const struct gpio_chip st_gpio_template = {
  1252. .request = gpiochip_generic_request,
  1253. .free = gpiochip_generic_free,
  1254. .get = st_gpio_get,
  1255. .set = st_gpio_set,
  1256. .direction_input = st_gpio_direction_input,
  1257. .direction_output = st_gpio_direction_output,
  1258. .get_direction = st_gpio_get_direction,
  1259. .ngpio = ST_GPIO_PINS_PER_BANK,
  1260. };
  1261. static struct irq_chip st_gpio_irqchip = {
  1262. .name = "GPIO",
  1263. .irq_request_resources = st_gpio_irq_request_resources,
  1264. .irq_release_resources = st_gpio_irq_release_resources,
  1265. .irq_disable = st_gpio_irq_mask,
  1266. .irq_mask = st_gpio_irq_mask,
  1267. .irq_unmask = st_gpio_irq_unmask,
  1268. .irq_set_type = st_gpio_irq_set_type,
  1269. .flags = IRQCHIP_SKIP_SET_WAKE,
  1270. };
  1271. static int st_gpiolib_register_bank(struct st_pinctrl *info,
  1272. int bank_nr, struct device_node *np)
  1273. {
  1274. struct st_gpio_bank *bank = &info->banks[bank_nr];
  1275. struct pinctrl_gpio_range *range = &bank->range;
  1276. struct device *dev = info->dev;
  1277. int bank_num = of_alias_get_id(np, "gpio");
  1278. struct resource res, irq_res;
  1279. int err;
  1280. if (of_address_to_resource(np, 0, &res))
  1281. return -ENODEV;
  1282. bank->base = devm_ioremap_resource(dev, &res);
  1283. if (IS_ERR(bank->base))
  1284. return PTR_ERR(bank->base);
  1285. bank->gpio_chip = st_gpio_template;
  1286. bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
  1287. bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
  1288. bank->gpio_chip.of_node = np;
  1289. bank->gpio_chip.parent = dev;
  1290. spin_lock_init(&bank->lock);
  1291. of_property_read_string(np, "st,bank-name", &range->name);
  1292. bank->gpio_chip.label = range->name;
  1293. range->id = bank_num;
  1294. range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
  1295. range->npins = bank->gpio_chip.ngpio;
  1296. range->gc = &bank->gpio_chip;
  1297. /**
  1298. * GPIO bank can have one of the two possible types of
  1299. * interrupt-wirings.
  1300. *
  1301. * First type is via irqmux, single interrupt is used by multiple
  1302. * gpio banks. This reduces number of overall interrupts numbers
  1303. * required. All these banks belong to a single pincontroller.
  1304. * _________
  1305. * | |----> [gpio-bank (n) ]
  1306. * | |----> [gpio-bank (n + 1)]
  1307. * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
  1308. * | |----> [gpio-bank (... )]
  1309. * |_________|----> [gpio-bank (n + 7)]
  1310. *
  1311. * Second type has a dedicated interrupt per each gpio bank.
  1312. *
  1313. * [irqN]----> [gpio-bank (n)]
  1314. */
  1315. if (of_irq_to_resource(np, 0, &irq_res) > 0) {
  1316. struct gpio_irq_chip *girq;
  1317. int gpio_irq = irq_res.start;
  1318. /* This is not a valid IRQ */
  1319. if (gpio_irq <= 0) {
  1320. dev_err(dev, "invalid IRQ for %pOF bank\n", np);
  1321. goto skip_irq;
  1322. }
  1323. /* We need to have a mux as well */
  1324. if (!info->irqmux_base) {
  1325. dev_err(dev, "no irqmux for %pOF bank\n", np);
  1326. goto skip_irq;
  1327. }
  1328. girq = &bank->gpio_chip.irq;
  1329. girq->chip = &st_gpio_irqchip;
  1330. girq->parent_handler = st_gpio_irq_handler;
  1331. girq->num_parents = 1;
  1332. girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
  1333. GFP_KERNEL);
  1334. if (!girq->parents)
  1335. return -ENOMEM;
  1336. girq->parents[0] = gpio_irq;
  1337. girq->default_type = IRQ_TYPE_NONE;
  1338. girq->handler = handle_simple_irq;
  1339. }
  1340. skip_irq:
  1341. err = gpiochip_add_data(&bank->gpio_chip, bank);
  1342. if (err)
  1343. return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num);
  1344. dev_info(dev, "%s bank added.\n", range->name);
  1345. return 0;
  1346. }
  1347. static const struct of_device_id st_pctl_of_match[] = {
  1348. { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
  1349. { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
  1350. { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
  1351. { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
  1352. { /* sentinel */ }
  1353. };
  1354. static int st_pctl_probe_dt(struct platform_device *pdev,
  1355. struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
  1356. {
  1357. struct device *dev = &pdev->dev;
  1358. int ret = 0;
  1359. int i = 0, j = 0, k = 0, bank;
  1360. struct pinctrl_pin_desc *pdesc;
  1361. struct device_node *np = dev->of_node;
  1362. struct device_node *child;
  1363. int grp_index = 0;
  1364. int irq = 0;
  1365. st_pctl_dt_child_count(info, np);
  1366. if (!info->nbanks)
  1367. return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n");
  1368. dev_info(dev, "nbanks = %d\n", info->nbanks);
  1369. dev_info(dev, "nfunctions = %d\n", info->nfunctions);
  1370. dev_info(dev, "ngroups = %d\n", info->ngroups);
  1371. info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
  1372. info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
  1373. info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL);
  1374. if (!info->functions || !info->groups || !info->banks)
  1375. return -ENOMEM;
  1376. info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
  1377. if (IS_ERR(info->regmap))
  1378. return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n");
  1379. info->data = of_match_node(st_pctl_of_match, np)->data;
  1380. irq = platform_get_irq(pdev, 0);
  1381. if (irq > 0) {
  1382. info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux");
  1383. if (IS_ERR(info->irqmux_base))
  1384. return PTR_ERR(info->irqmux_base);
  1385. irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,
  1386. info);
  1387. }
  1388. pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
  1389. pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL);
  1390. if (!pdesc)
  1391. return -ENOMEM;
  1392. pctl_desc->pins = pdesc;
  1393. bank = 0;
  1394. for_each_child_of_node(np, child) {
  1395. if (of_property_read_bool(child, "gpio-controller")) {
  1396. const char *bank_name = NULL;
  1397. char **pin_names;
  1398. ret = st_gpiolib_register_bank(info, bank, child);
  1399. if (ret) {
  1400. of_node_put(child);
  1401. return ret;
  1402. }
  1403. k = info->banks[bank].range.pin_base;
  1404. bank_name = info->banks[bank].range.name;
  1405. pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK);
  1406. if (IS_ERR(pin_names)) {
  1407. of_node_put(child);
  1408. return PTR_ERR(pin_names);
  1409. }
  1410. for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
  1411. pdesc->number = k;
  1412. pdesc->name = pin_names[j];
  1413. pdesc++;
  1414. }
  1415. st_parse_syscfgs(info, bank, child);
  1416. bank++;
  1417. } else {
  1418. ret = st_pctl_parse_functions(child, info,
  1419. i++, &grp_index);
  1420. if (ret) {
  1421. dev_err(dev, "No functions found.\n");
  1422. of_node_put(child);
  1423. return ret;
  1424. }
  1425. }
  1426. }
  1427. return 0;
  1428. }
  1429. static int st_pctl_probe(struct platform_device *pdev)
  1430. {
  1431. struct device *dev = &pdev->dev;
  1432. struct st_pinctrl *info;
  1433. struct pinctrl_desc *pctl_desc;
  1434. int ret, i;
  1435. if (!dev->of_node) {
  1436. dev_err(dev, "device node not found.\n");
  1437. return -EINVAL;
  1438. }
  1439. pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
  1440. if (!pctl_desc)
  1441. return -ENOMEM;
  1442. info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
  1443. if (!info)
  1444. return -ENOMEM;
  1445. info->dev = dev;
  1446. platform_set_drvdata(pdev, info);
  1447. ret = st_pctl_probe_dt(pdev, pctl_desc, info);
  1448. if (ret)
  1449. return ret;
  1450. pctl_desc->owner = THIS_MODULE;
  1451. pctl_desc->pctlops = &st_pctlops;
  1452. pctl_desc->pmxops = &st_pmxops;
  1453. pctl_desc->confops = &st_confops;
  1454. pctl_desc->name = dev_name(dev);
  1455. info->pctl = devm_pinctrl_register(dev, pctl_desc, info);
  1456. if (IS_ERR(info->pctl))
  1457. return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n");
  1458. for (i = 0; i < info->nbanks; i++)
  1459. pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
  1460. return 0;
  1461. }
  1462. static struct platform_driver st_pctl_driver = {
  1463. .driver = {
  1464. .name = "st-pinctrl",
  1465. .of_match_table = st_pctl_of_match,
  1466. },
  1467. .probe = st_pctl_probe,
  1468. };
  1469. static int __init st_pctl_init(void)
  1470. {
  1471. return platform_driver_register(&st_pctl_driver);
  1472. }
  1473. arch_initcall(st_pctl_init);