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android_kernel_...
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drivers
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pinctrl
/
mediatek
/
pinctrl-mt8173.c

pinctrl-mt8173.c 13 KB
Előzmények Nyers

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  1. // SPDX-License-Identifier: GPL-2.0-only
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2014-2015 MediaTek Inc.
    4. 

  4.  * Author: Hongzhou.Yang <[email protected]>
    5. 

  5.  */
    6. 

  6. 

  7. #include <linux/init.h>
    8. 

  8. #include <linux/platform_device.h>
    9. 

  9. #include <linux/of.h>
    10. 

  10. #include <linux/of_device.h>
    11. 

  11. #include <linux/pinctrl/pinctrl.h>
    12. 

  12. #include <linux/regmap.h>
    13. 

  13. #include <linux/pinctrl/pinconf-generic.h>
    14. 

  14. #include <dt-bindings/pinctrl/mt65xx.h>
    15. 

  15. 

  16. #include "pinctrl-mtk-common.h"
    17. 

  17. #include "pinctrl-mtk-mt8173.h"
    18. 

  18. 

  19. #define DRV_BASE				0xb00
    20. 

  20. 

  21. static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
    22. 

  22. 	MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0),  /* KROW0 */
    23. 

  23. 	MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4),  /* KROW1 */
    24. 

  24. 	MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
    25. 

  25. 	MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0),  /* KCOL0 */
    26. 

  26. 	MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4),  /* KCOL1 */
    27. 

  27. 	MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
    28. 

  28. 

  29. 	MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0),   /* ms0 DS */
    30. 

  30. 	MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0),   /* ms0 RST */
    31. 

  31. 	MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0),   /* ms0 cmd */
    32. 

  32. 	MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0),   /* ms0 clk */
    33. 

  33. 	MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0),   /* ms0 data0 */
    34. 

  34. 	MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0),   /* ms0 data1 */
    35. 

  35. 	MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0),   /* ms0 data2 */
    36. 

  36. 	MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0),   /* ms0 data3 */
    37. 

  37. 	MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0),   /* ms0 data4 */
    38. 

  38. 	MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0),   /* ms0 data5 */
    39. 

  39. 	MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0),   /* ms0 data6 */
    40. 

  40. 	MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0),   /* ms0 data7 */
    41. 

  41. 

  42. 	MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0),    /* ms1 cmd */
    43. 

  43. 	MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0),    /* ms1 dat0 */
    44. 

  44. 	MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4),    /* ms1 dat1 */
    45. 

  45. 	MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8),   /* ms1 dat2 */
    46. 

  46. 	MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
    47. 

  47. 	MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0),    /* ms1 clk */
    48. 

  48. 

  49. 	MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0),    /* ms2 dat0 */
    50. 

  50. 	MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4),    /* ms2 dat1 */
    51. 

  51. 	MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8),   /* ms2 dat2 */
    52. 

  52. 	MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
    53. 

  53. 	MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0),    /* ms2 clk */
    54. 

  54. 	MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0),    /* ms2 cmd */
    55. 

  55. 

  56. 	MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0),    /* ms3 dat0 */
    57. 

  57. 	MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4),    /* ms3 dat1 */
    58. 

  58. 	MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8),   /* ms3 dat2 */
    59. 

  59. 	MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
    60. 

  60. 	MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0),    /* ms3 clk */
    61. 

  61. 	MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0)     /* ms3 cmd */
    62. 

  62. };
    63. 

  63. 

  64. static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
    65. 

  65. 	MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
    66. 

  66. 	MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
    67. 

  67. 	MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10),
    68. 

  68. 	MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10),
    69. 

  69. 	MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0),
    70. 

  70. 	MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
    71. 

  71. 	MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3),
    72. 

  72. 	MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13),
    73. 

  73. 	MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13),
    74. 

  74. 	MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13),
    75. 

  75. 	MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13),
    76. 

  76. 	MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3),
    77. 

  77. 	MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4),
    78. 

  78. 	MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5),
    79. 

  79. 	MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6),
    80. 

  80. 	MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7),
    81. 

  81. 	MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
    82. 

  82. 	MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0),
    83. 

  83. 	MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11),
    84. 

  84. 	MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12),
    85. 

  85. 	MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13),
    86. 

  86. 	MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13),
    87. 

  87. 	MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13),
    88. 

  88. 	MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13),
    89. 

  89. 	MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13),
    90. 

  90. 	MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14),
    91. 

  91. 	MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13),
    92. 

  92. 	MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13),
    93. 

  93. 	MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13),
    94. 

  94. 	MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15),
    95. 

  95. 	MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0),
    96. 

  96. 	MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1),
    97. 

  97. 	MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
    98. 

  98. 	MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13),
    99. 

  99. 	MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14),
    100. 

  100. 	MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15),
    101. 

  101. 	MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13),
    102. 

  102. 	MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13),
    103. 

  103. 	MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13),
    104. 

  104. 	MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4),
    105. 

  105. 	MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1),
    106. 

  106. 	MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
    107. 

  107. 	MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5),
    108. 

  108. 	MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6),
    109. 

  109. 	MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7),
    110. 

  110. 	MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0),
    111. 

  111. 	MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
    112. 

  112. 	MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9),
    113. 

  113. 	MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
    114. 

  114. 	MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
    115. 

  115. };
    116. 

  116. 

  117. static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
    118. 

  118. 	MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1),
    119. 

  119. 	MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
    120. 

  120. 	MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10),
    121. 

  121. 	MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10),
    122. 

  122. 	MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0),
    123. 

  123. 	MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
    124. 

  124. 	MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3),
    125. 

  125. 	MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14),
    126. 

  126. 	MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14),
    127. 

  127. 	MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14),
    128. 

  128. 	MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14),
    129. 

  129. 	MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
    130. 

  130. 	MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4),
    131. 

  131. 	MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5),
    132. 

  132. 	MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6),
    133. 

  133. 	MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7),
    134. 

  134. 	MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
    135. 

  135. 	MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0),
    136. 

  136. 	MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11),
    137. 

  137. 	MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12),
    138. 

  138. 	MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14),
    139. 

  139. 	MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14),
    140. 

  140. 	MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14),
    141. 

  141. 	MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14),
    142. 

  142. 	MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14),
    143. 

  143. 	MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14),
    144. 

  144. 	MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14),
    145. 

  145. 	MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14),
    146. 

  146. 	MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14),
    147. 

  147. 	MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15),
    148. 

  148. 	MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0),
    149. 

  149. 	MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1),
    150. 

  150. 	MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
    151. 

  151. 	MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13),
    152. 

  152. 	MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14),
    153. 

  153. 	MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15),
    154. 

  154. 	MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14),
    155. 

  155. 	MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14),
    156. 

  156. 	MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14),
    157. 

  157. 	MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4),
    158. 

  158. 	MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1),
    159. 

  159. 	MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
    160. 

  160. 	MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5),
    161. 

  161. 	MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6),
    162. 

  162. 	MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7),
    163. 

  163. 	MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0),
    164. 

  164. 	MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
    165. 

  165. 	MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9),
    166. 

  166. 	MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
    167. 

  167. 	MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
    168. 

  168. };
    169. 

  169. 

  170. static const struct mtk_drv_group_desc mt8173_drv_grp[] =  {
    171. 

  171. 	/* 0E4E8SR 4/8/12/16 */
    172. 

  172. 	MTK_DRV_GRP(4, 16, 1, 2, 4),
    173. 

  173. 	/* 0E2E4SR  2/4/6/8 */
    174. 

  174. 	MTK_DRV_GRP(2, 8, 1, 2, 2),
    175. 

  175. 	/* E8E4E2  2/4/6/8/10/12/14/16 */
    176. 

  176. 	MTK_DRV_GRP(2, 16, 0, 2, 2)
    177. 

  177. };
    178. 

  178. 

  179. static const struct mtk_pin_drv_grp mt8173_pin_drv[] = {
    180. 

  180. 	MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
    181. 

  181. 	MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
    182. 

  182. 	MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
    183. 

  183. 	MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
    184. 

  184. 	MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
    185. 

  185. 	MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
    186. 

  186. 	MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
    187. 

  187. 	MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
    188. 

  188. 	MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
    189. 

  189. 	MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
    190. 

  190. 	MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
    191. 

  191. 	MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
    192. 

  192. 	MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
    193. 

  193. 	MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1),
    194. 

  194. 	MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
    195. 

  195. 	MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
    196. 

  196. 	MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
    197. 

  197. 	MTK_PIN_DRV_GRP(17, 0xce0, 8, 2),
    198. 

  198. 	MTK_PIN_DRV_GRP(22, 0xce0, 8, 2),
    199. 

  199. 	MTK_PIN_DRV_GRP(23, 0xce0, 8, 2),
    200. 

  200. 	MTK_PIN_DRV_GRP(24, 0xce0, 8, 2),
    201. 

  201. 	MTK_PIN_DRV_GRP(25, 0xce0, 8, 2),
    202. 

  202. 	MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2),
    203. 

  203. 	MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2),
    204. 

  204. 	MTK_PIN_DRV_GRP(28, 0xd70, 8, 2),
    205. 

  205. 	MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1),
    206. 

  206. 	MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1),
    207. 

  207. 	MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1),
    208. 

  208. 	MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1),
    209. 

  209. 	MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1),
    210. 

  210. 	MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
    211. 

  211. 	MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
    212. 

  212. 	MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
    213. 

  213. 	MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1),
    214. 

  214. 	MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1),
    215. 

  215. 	MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0),
    216. 

  216. 	MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
    217. 

  217. 	MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
    218. 

  218. 	MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
    219. 

  219. 	MTK_PIN_DRV_GRP(57, 0xc20, 8, 2),
    220. 

  220. 	MTK_PIN_DRV_GRP(58, 0xc20, 8, 2),
    221. 

  221. 	MTK_PIN_DRV_GRP(59, 0xc20, 8, 2),
    222. 

  222. 	MTK_PIN_DRV_GRP(60, 0xc20, 8, 2),
    223. 

  223. 	MTK_PIN_DRV_GRP(61, 0xc20, 8, 2),
    224. 

  224. 	MTK_PIN_DRV_GRP(62, 0xc20, 8, 2),
    225. 

  225. 	MTK_PIN_DRV_GRP(63, 0xc20, 8, 2),
    226. 

  226. 	MTK_PIN_DRV_GRP(64, 0xc20, 8, 2),
    227. 

  227. 	MTK_PIN_DRV_GRP(65, 0xc00, 8, 2),
    228. 

  228. 	MTK_PIN_DRV_GRP(66, 0xc10, 8, 2),
    229. 

  229. 	MTK_PIN_DRV_GRP(67, 0xd10, 8, 2),
    230. 

  230. 	MTK_PIN_DRV_GRP(68, 0xd00, 8, 2),
    231. 

  231. 	MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1),
    232. 

  232. 	MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1),
    233. 

  233. 	MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1),
    234. 

  234. 	MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1),
    235. 

  235. 	MTK_PIN_DRV_GRP(73, 0xc60, 8, 2),
    236. 

  236. 	MTK_PIN_DRV_GRP(74, 0xc60, 8, 2),
    237. 

  237. 	MTK_PIN_DRV_GRP(75, 0xc60, 8, 2),
    238. 

  238. 	MTK_PIN_DRV_GRP(76, 0xc60, 8, 2),
    239. 

  239. 	MTK_PIN_DRV_GRP(77, 0xc40, 8, 2),
    240. 

  240. 	MTK_PIN_DRV_GRP(78, 0xc50, 8, 2),
    241. 

  241. 	MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1),
    242. 

  242. 	MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1),
    243. 

  243. 	MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1),
    244. 

  244. 	MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1),
    245. 

  245. 	MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1),
    246. 

  246. 	MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1),
    247. 

  247. 	MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1),
    248. 

  248. 	MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
    249. 

  249. 	MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
    250. 

  250. 	MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
    251. 

  251. 	MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
    252. 

  252. 	MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
    253. 

  253. 	MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
    254. 

  254. 	MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
    255. 

  255. 	MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0),
    256. 

  256. 	MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0),
    257. 

  257. 	MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0),
    258. 

  258. 	MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0),
    259. 

  259. 	MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
    260. 

  260. 	MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
    261. 

  261. 	MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
    262. 

  262. 	MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
    263. 

  263. 	MTK_PIN_DRV_GRP(100, 0xca0, 8, 2),
    264. 

  264. 	MTK_PIN_DRV_GRP(101, 0xca0, 8, 2),
    265. 

  265. 	MTK_PIN_DRV_GRP(102, 0xca0, 8, 2),
    266. 

  266. 	MTK_PIN_DRV_GRP(103, 0xca0, 8, 2),
    267. 

  267. 	MTK_PIN_DRV_GRP(104, 0xc80, 8, 2),
    268. 

  268. 	MTK_PIN_DRV_GRP(105, 0xc90, 8, 2),
    269. 

  269. 	MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
    270. 

  270. 	MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
    271. 

  271. 	MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
    272. 

  272. 	MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
    273. 

  273. 	MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
    274. 

  274. 	MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1),
    275. 

  275. 	MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1),
    276. 

  276. 	MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1),
    277. 

  277. 	MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1),
    278. 

  278. 	MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1),
    279. 

  279. 	MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1),
    280. 

  280. 	MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
    281. 

  281. 	MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
    282. 

  282. 	MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
    283. 

  283. 	MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1),
    284. 

  284. 	MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1),
    285. 

  285. 	MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1),
    286. 

  286. 	MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1),
    287. 

  287. 	MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1),
    288. 

  288. 	MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
    289. 

  289. 	MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1),
    290. 

  290. 	MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1),
    291. 

  291. 	MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1),
    292. 

  292. 	MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1),
    293. 

  293. 	MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1)
    294. 

  294. };
    295. 

  295. 

  296. static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
    297. 

  297. 	.pins = mtk_pins_mt8173,
    298. 

  298. 	.npins = ARRAY_SIZE(mtk_pins_mt8173),
    299. 

  299. 	.grp_desc = mt8173_drv_grp,
    300. 

  300. 	.n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
    301. 

  301. 	.pin_drv_grp = mt8173_pin_drv,
    302. 

  302. 	.n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
    303. 

  303. 	.spec_ies = mt8173_ies_set,
    304. 

  304. 	.n_spec_ies = ARRAY_SIZE(mt8173_ies_set),
    305. 

  305. 	.spec_pupd = mt8173_spec_pupd,
    306. 

  306. 	.n_spec_pupd = ARRAY_SIZE(mt8173_spec_pupd),
    307. 

  307. 	.spec_smt = mt8173_smt_set,
    308. 

  308. 	.n_spec_smt = ARRAY_SIZE(mt8173_smt_set),
    309. 

  309. 	.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
    310. 

  310. 	.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
    311. 

  311. 	.dir_offset = 0x0000,
    312. 

  312. 	.pullen_offset = 0x0100,
    313. 

  313. 	.pullsel_offset = 0x0200,
    314. 

  314. 	.dout_offset = 0x0400,
    315. 

  315. 	.din_offset = 0x0500,
    316. 

  316. 	.pinmux_offset = 0x0600,
    317. 

  317. 	.type1_start = 135,
    318. 

  318. 	.type1_end = 135,
    319. 

  319. 	.port_shf = 4,
    320. 

  320. 	.port_mask = 0xf,
    321. 

  321. 	.port_align = 4,
    322. 

  322. 	.mode_mask = 0xf,
    323. 

  323. 	.mode_per_reg = 5,
    324. 

  324. 	.mode_shf = 4,
    325. 

  325. 	.eint_hw = {
    326. 

  326. 		.port_mask = 7,
    327. 

  327. 		.ports     = 6,
    328. 

  328. 		.ap_num    = 224,
    329. 

  329. 		.db_cnt    = 16,
    330. 

  330. 		.db_time   = debounce_time_mt2701,
    331. 

  331. 	},
    332. 

  332. };
    333. 

  333. 

  334. static int mt8173_pinctrl_probe(struct platform_device *pdev)
    335. 

  335. {
    336. 

  336. 	return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL);
    337. 

  337. }
    338. 

  338. 

  339. static const struct of_device_id mt8173_pctrl_match[] = {
    340. 

  340. 	{
    341. 

  341. 		.compatible = "mediatek,mt8173-pinctrl",
    342. 

  342. 	},
    343. 

  343. 	{ }
    344. 

  344. };
    345. 

  345. 

  346. static struct platform_driver mtk_pinctrl_driver = {
    347. 

  347. 	.probe = mt8173_pinctrl_probe,
    348. 

  348. 	.driver = {
    349. 

  349. 		.name = "mediatek-mt8173-pinctrl",
    350. 

  350. 		.of_match_table = mt8173_pctrl_match,
    351. 

  351. 		.pm = &mtk_eint_pm_ops,
    352. 

  352. 	},
    353. 

  353. };
    354. 

  354. 

  355. static int __init mtk_pinctrl_init(void)
    356. 

  356. {
    357. 

  357. 	return platform_driver_register(&mtk_pinctrl_driver);
    358. 

  358. }
    359. 

  359. arch_initcall(mtk_pinctrl_init);
    360.