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android_kernel_...
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drivers
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pinctrl
/
mediatek
/
pinctrl-mt8135.c

pinctrl-mt8135.c 11 KB
Előzmények Nyers

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  1. // SPDX-License-Identifier: GPL-2.0-only
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2014 MediaTek Inc.
    4. 

  4.  * Author: Hongzhou.Yang <[email protected]>
    5. 

  5.  */
    6. 

  6. 

  7. #include <linux/init.h>
    8. 

  8. #include <linux/platform_device.h>
    9. 

  9. #include <linux/of.h>
    10. 

  10. #include <linux/of_device.h>
    11. 

  11. #include <linux/pinctrl/pinctrl.h>
    12. 

  12. #include <linux/regmap.h>
    13. 

  13. #include <dt-bindings/pinctrl/mt65xx.h>
    14. 

  14. 

  15. #include "pinctrl-mtk-common.h"
    16. 

  16. #include "pinctrl-mtk-mt8135.h"
    17. 

  17. 

  18. #define DRV_BASE1				0x500
    19. 

  19. #define DRV_BASE2				0x510
    20. 

  20. #define PUPD_BASE1				0x400
    21. 

  21. #define PUPD_BASE2				0x450
    22. 

  22. #define R0_BASE1				0x4d0
    23. 

  23. #define R1_BASE1				0x200
    24. 

  24. #define R1_BASE2				0x250
    25. 

  25. 

  26. struct mtk_spec_pull_set {
    27. 

  27. 	unsigned char pin;
    28. 

  28. 	unsigned char pupd_bit;
    29. 

  29. 	unsigned short pupd_offset;
    30. 

  30. 	unsigned short r0_offset;
    31. 

  31. 	unsigned short r1_offset;
    32. 

  32. 	unsigned char r0_bit;
    33. 

  33. 	unsigned char r1_bit;
    34. 

  34. };
    35. 

  35. 

  36. #define SPEC_PULL(_pin, _pupd_offset, _pupd_bit, _r0_offset, \
    37. 

  37. 	_r0_bit, _r1_offset, _r1_bit)	\
    38. 

  38. 	{	\
    39. 

  39. 		.pin = _pin,	\
    40. 

  40. 		.pupd_offset = _pupd_offset,	\
    41. 

  41. 		.pupd_bit = _pupd_bit,	\
    42. 

  42. 		.r0_offset = _r0_offset, \
    43. 

  43. 		.r0_bit = _r0_bit, \
    44. 

  44. 		.r1_offset = _r1_offset, \
    45. 

  45. 		.r1_bit = _r1_bit, \
    46. 

  46. 	}
    47. 

  47. 

  48. static const struct mtk_drv_group_desc mt8135_drv_grp[] =  {
    49. 

  49. 	/* E8E4E2 2/4/6/8/10/12/14/16 */
    50. 

  50. 	MTK_DRV_GRP(2, 16, 0, 2, 2),
    51. 

  51. 	/* E8E4  4/8/12/16 */
    52. 

  52. 	MTK_DRV_GRP(4, 16, 1, 2, 4),
    53. 

  53. 	/* E4E2  2/4/6/8 */
    54. 

  54. 	MTK_DRV_GRP(2, 8, 0, 1, 2),
    55. 

  55. 	/* E16E8E4 4/8/12/16/20/24/28/32 */
    56. 

  56. 	MTK_DRV_GRP(4, 32, 0, 2, 4)
    57. 

  57. };
    58. 

  58. 

  59. static const struct mtk_pin_drv_grp mt8135_pin_drv[] = {
    60. 

  60. 	MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
    61. 

  61. 	MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
    62. 

  62. 	MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
    63. 

  63. 	MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
    64. 

  64. 	MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
    65. 

  65. 	MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
    66. 

  66. 	MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
    67. 

  67. 	MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
    68. 

  68. 	MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
    69. 

  69. 	MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),
    70. 

  70. 

  71. 	MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1),
    72. 

  72. 	MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1),
    73. 

  73. 	MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1),
    74. 

  74. 	MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1),
    75. 

  75. 	MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1),
    76. 

  76. 	MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1),
    77. 

  77. 	MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1),
    78. 

  78. 	MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1),
    79. 

  79. 	MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1),
    80. 

  80. 	MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1),
    81. 

  81. 	MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1),
    82. 

  82. 	MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1),
    83. 

  83. 	MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1),
    84. 

  84. 	MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1),
    85. 

  85. 	MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1),
    86. 

  86. 	MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1),
    87. 

  87. 	MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2),
    88. 

  88. 	MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1),
    89. 

  89. 	MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1),
    90. 

  90. 	MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1),
    91. 

  91. 	MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1),
    92. 

  92. 	MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1),
    93. 

  93. 	MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1),
    94. 

  94. 	MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1),
    95. 

  95. 	MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1),
    96. 

  96. 	MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1),
    97. 

  97. 	MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1),
    98. 

  98. 	MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1),
    99. 

  99. 

  100. 	MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),
    101. 

  101. 	MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),
    102. 

  102. 	MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),
    103. 

  103. 	MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),
    104. 

  104. 	MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),
    105. 

  105. 	MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),
    106. 

  106. 	MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),
    107. 

  107. 	MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),
    108. 

  108. 

  109. 	MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),
    110. 

  110. 	MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),
    111. 

  111. 	MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),
    112. 

  112. 	MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),
    113. 

  113. 	MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),
    114. 

  114. 	MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),
    115. 

  115. 	MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),
    116. 

  116. 	MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1),
    117. 

  117. 	MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1),
    118. 

  118. 	MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1),
    119. 

  119. 	MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1),
    120. 

  120. 	MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1),
    121. 

  121. 	MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1),
    122. 

  122. 

  123. 	MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1),
    124. 

  124. 	MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1),
    125. 

  125. 	MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1),
    126. 

  126. 	MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1),
    127. 

  127. 	MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1),
    128. 

  128. 	MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1),
    129. 

  129. 	MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1),
    130. 

  130. 	MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3),
    131. 

  131. 	MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3),
    132. 

  132. 

  133. 	MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3),
    134. 

  134. 	MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3),
    135. 

  135. 

  136. 	MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3),
    137. 

  137. 	MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3),
    138. 

  138. 

  139. 	MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3),
    140. 

  140. 	MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3),
    141. 

  141. 	MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3),
    142. 

  142. 	MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3),
    143. 

  143. 	MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3),
    144. 

  144. 	MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3),
    145. 

  145. 

  146. 	MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
    147. 

  147. 	MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
    148. 

  148. 	MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
    149. 

  149. 	MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
    150. 

  150. 	MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
    151. 

  151. 	MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
    152. 

  152. 	MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
    153. 

  153. 

  154. 	MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0),
    155. 

  155. 

  156. 	MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
    157. 

  157. 	MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
    158. 

  158. 	MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1),
    159. 

  159. 	MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1),
    160. 

  160. 	MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1),
    161. 

  161. 

  162. 

  163. 	MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1),
    164. 

  164. 	MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1),
    165. 

  165. 	MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1),
    166. 

  166. 	MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1),
    167. 

  167. 	MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1),
    168. 

  168. 	MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2),
    169. 

  169. 	MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2),
    170. 

  170. 	MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2),
    171. 

  171. 	MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2),
    172. 

  172. 	MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2),
    173. 

  173. 	MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2),
    174. 

  174. 

  175. 	MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2),
    176. 

  176. 	MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2),
    177. 

  177. 	MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2),
    178. 

  178. 	MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2),
    179. 

  179. 	MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2),
    180. 

  180. 	MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2),
    181. 

  181. 

  182. 	MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1),
    183. 

  183. 	MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1),
    184. 

  184. 	MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1),
    185. 

  185. 	MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1),
    186. 

  186. 	MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1),
    187. 

  187. 

  188. 	MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2),
    189. 

  189. 	MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2),
    190. 

  190. 	MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2),
    191. 

  191. 	MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2),
    192. 

  192. 	MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1),
    193. 

  193. 	MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1),
    194. 

  194. 	MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1),
    195. 

  195. 

  196. 	MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0),
    197. 

  197. 	MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0),
    198. 

  198. 	MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0),
    199. 

  199. 	MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0),
    200. 

  200. 	MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0),
    201. 

  201. 	MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0)
    202. 

  202. };
    203. 

  203. 

  204. static const struct mtk_spec_pull_set spec_pupd[] = {
    205. 

  205. 	SPEC_PULL(0, PUPD_BASE1, 0, R0_BASE1, 9, R1_BASE1, 0),
    206. 

  206. 	SPEC_PULL(1, PUPD_BASE1, 1, R0_BASE1, 8, R1_BASE1, 1),
    207. 

  207. 	SPEC_PULL(2, PUPD_BASE1, 2, R0_BASE1, 7, R1_BASE1, 2),
    208. 

  208. 	SPEC_PULL(3, PUPD_BASE1, 3, R0_BASE1, 6, R1_BASE1, 3),
    209. 

  209. 	SPEC_PULL(4, PUPD_BASE1, 4, R0_BASE1, 1, R1_BASE1, 4),
    210. 

  210. 	SPEC_PULL(5, PUPD_BASE1, 5, R0_BASE1, 0, R1_BASE1, 5),
    211. 

  211. 	SPEC_PULL(6, PUPD_BASE1, 6, R0_BASE1, 5, R1_BASE1, 6),
    212. 

  212. 	SPEC_PULL(7, PUPD_BASE1, 7, R0_BASE1, 4, R1_BASE1, 7),
    213. 

  213. 	SPEC_PULL(8, PUPD_BASE1, 8, R0_BASE1, 3, R1_BASE1, 8),
    214. 

  214. 	SPEC_PULL(9, PUPD_BASE1, 9, R0_BASE1, 2, R1_BASE1, 9),
    215. 

  215. 	SPEC_PULL(89, PUPD_BASE2, 9, R0_BASE1, 18, R1_BASE2, 9),
    216. 

  216. 	SPEC_PULL(90, PUPD_BASE2, 10, R0_BASE1, 19, R1_BASE2, 10),
    217. 

  217. 	SPEC_PULL(91, PUPD_BASE2, 11, R0_BASE1, 23, R1_BASE2, 11),
    218. 

  218. 	SPEC_PULL(92, PUPD_BASE2, 12, R0_BASE1, 24, R1_BASE2, 12),
    219. 

  219. 	SPEC_PULL(93, PUPD_BASE2, 13, R0_BASE1, 25, R1_BASE2, 13),
    220. 

  220. 	SPEC_PULL(94, PUPD_BASE2, 14, R0_BASE1, 22, R1_BASE2, 14),
    221. 

  221. 	SPEC_PULL(95, PUPD_BASE2, 15, R0_BASE1, 20, R1_BASE2, 15),
    222. 

  222. 	SPEC_PULL(96, PUPD_BASE2+0x10, 0, R0_BASE1, 16, R1_BASE2+0x10, 0),
    223. 

  223. 	SPEC_PULL(97, PUPD_BASE2+0x10, 1, R0_BASE1, 21, R1_BASE2+0x10, 1),
    224. 

  224. 	SPEC_PULL(98, PUPD_BASE2+0x10, 2, R0_BASE1, 17, R1_BASE2+0x10, 2),
    225. 

  225. 	SPEC_PULL(197, PUPD_BASE1+0xc0, 5, R0_BASE1, 13, R1_BASE2+0xc0, 5),
    226. 

  226. 	SPEC_PULL(198, PUPD_BASE2+0xc0, 6, R0_BASE1, 14, R1_BASE2+0xc0, 6),
    227. 

  227. 	SPEC_PULL(199, PUPD_BASE2+0xc0, 7, R0_BASE1, 11, R1_BASE2+0xc0, 7),
    228. 

  228. 	SPEC_PULL(200, PUPD_BASE2+0xc0, 8, R0_BASE1, 10, R1_BASE2+0xc0, 8),
    229. 

  229. 	SPEC_PULL(201, PUPD_BASE2+0xc0, 9, R0_BASE1, 13, R1_BASE2+0xc0, 9),
    230. 

  230. 	SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
    231. 

  231. };
    232. 

  232. 

  233. static int spec_pull_set(struct regmap *regmap,
    234. 

  234. 		const struct mtk_pinctrl_devdata *devdata,
    235. 

  235. 		unsigned int pin, bool isup, unsigned int r1r0)
    236. 

  236. {
    237. 

  237. 	unsigned int i;
    238. 

  238. 	unsigned int reg_pupd, reg_set_r0, reg_set_r1;
    239. 

  239. 	unsigned int reg_rst_r0, reg_rst_r1;
    240. 

  240. 	unsigned char align = devdata->port_align;
    241. 

  241. 	bool find = false;
    242. 

  242. 

  243. 	for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
    244. 

  244. 		if (pin == spec_pupd[i].pin) {
    245. 

  245. 			find = true;
    246. 

  246. 			break;
    247. 

  247. 		}
    248. 

  248. 	}
    249. 

  249. 

  250. 	if (!find)
    251. 

  251. 		return -EINVAL;
    252. 

  252. 

  253. 	if (isup)
    254. 

  254. 		reg_pupd = spec_pupd[i].pupd_offset + align;
    255. 

  255. 	else
    256. 

  256. 		reg_pupd = spec_pupd[i].pupd_offset + (align << 1);
    257. 

  257. 

  258. 	regmap_write(regmap, reg_pupd, spec_pupd[i].pupd_bit);
    259. 

  259. 

  260. 	reg_set_r0 = spec_pupd[i].r0_offset + align;
    261. 

  261. 	reg_rst_r0 = spec_pupd[i].r0_offset + (align << 1);
    262. 

  262. 	reg_set_r1 = spec_pupd[i].r1_offset + align;
    263. 

  263. 	reg_rst_r1 = spec_pupd[i].r1_offset + (align << 1);
    264. 

  264. 

  265. 	switch (r1r0) {
    266. 

  266. 	case MTK_PUPD_SET_R1R0_00:
    267. 

  267. 		regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
    268. 

  268. 		regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
    269. 

  269. 		break;
    270. 

  270. 	case MTK_PUPD_SET_R1R0_01:
    271. 

  271. 		regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
    272. 

  272. 		regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
    273. 

  273. 		break;
    274. 

  274. 	case MTK_PUPD_SET_R1R0_10:
    275. 

  275. 		regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
    276. 

  276. 		regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
    277. 

  277. 		break;
    278. 

  278. 	case MTK_PUPD_SET_R1R0_11:
    279. 

  279. 		regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
    280. 

  280. 		regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
    281. 

  281. 		break;
    282. 

  282. 	default:
    283. 

  283. 		return -EINVAL;
    284. 

  284. 	}
    285. 

  285. 

  286. 	return 0;
    287. 

  287. }
    288. 

  288. 

  289. static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
    290. 

  290. 	.pins = mtk_pins_mt8135,
    291. 

  291. 	.npins = ARRAY_SIZE(mtk_pins_mt8135),
    292. 

  292. 	.grp_desc = mt8135_drv_grp,
    293. 

  293. 	.n_grp_cls = ARRAY_SIZE(mt8135_drv_grp),
    294. 

  294. 	.pin_drv_grp = mt8135_pin_drv,
    295. 

  295. 	.n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv),
    296. 

  296. 	.spec_pull_set = spec_pull_set,
    297. 

  297. 	.dir_offset = 0x0000,
    298. 

  298. 	.ies_offset = 0x0100,
    299. 

  299. 	.pullen_offset = 0x0200,
    300. 

  300. 	.smt_offset = 0x0300,
    301. 

  301. 	.pullsel_offset = 0x0400,
    302. 

  302. 	.dout_offset = 0x0800,
    303. 

  303. 	.din_offset = 0x0A00,
    304. 

  304. 	.pinmux_offset = 0x0C00,
    305. 

  305. 	.type1_start = 34,
    306. 

  306. 	.type1_end = 149,
    307. 

  307. 	.port_shf = 4,
    308. 

  308. 	.port_mask = 0xf,
    309. 

  309. 	.port_align = 4,
    310. 

  310. 	.mode_mask = 0xf,
    311. 

  311. 	.mode_per_reg = 5,
    312. 

  312. 	.mode_shf = 4,
    313. 

  313. 	.eint_hw = {
    314. 

  314. 		.port_mask = 7,
    315. 

  315. 		.ports     = 6,
    316. 

  316. 		.ap_num    = 192,
    317. 

  317. 		.db_cnt    = 16,
    318. 

  318. 		.db_time = debounce_time_mt2701,
    319. 

  319. 	},
    320. 

  320. };
    321. 

  321. 

  322. static const struct of_device_id mt8135_pctrl_match[] = {
    323. 

  323. 	{ .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data },
    324. 

  324. 	{ }
    325. 

  325. };
    326. 

  326. 

  327. static struct platform_driver mtk_pinctrl_driver = {
    328. 

  328. 	.probe = mtk_pctrl_common_probe,
    329. 

  329. 	.driver = {
    330. 

  330. 		.name = "mediatek-mt8135-pinctrl",
    331. 

  331. 		.of_match_table = mt8135_pctrl_match,
    332. 

  332. 	},
    333. 

  333. };
    334. 

  334. 

  335. static int __init mtk_pinctrl_init(void)
    336. 

  336. {
    337. 

  337. 	return platform_driver_register(&mtk_pinctrl_driver);
    338. 

  338. }
    339. 

  339. arch_initcall(mtk_pinctrl_init);
    340.