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phy-qcom-qmp-pcs-v4.h

phy-qcom-qmp-pcs-v4.h 5.5 KB
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  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef QCOM_PHY_QMP_PCS_V4_H_
    7. 

  7. #define QCOM_PHY_QMP_PCS_V4_H_
    8. 

  8. 

  9. /* Only for QMP V4 PHY - USB/PCIe PCS registers */
    10. 

  10. #define QPHY_V4_PCS_SW_RESET				0x000
    11. 

  11. #define QPHY_V4_PCS_REVISION_ID0			0x004
    12. 

  12. #define QPHY_V4_PCS_REVISION_ID1			0x008
    13. 

  13. #define QPHY_V4_PCS_REVISION_ID2			0x00c
    14. 

  14. #define QPHY_V4_PCS_REVISION_ID3			0x010
    15. 

  15. #define QPHY_V4_PCS_PCS_STATUS1				0x014
    16. 

  16. #define QPHY_V4_PCS_PCS_STATUS2				0x018
    17. 

  17. #define QPHY_V4_PCS_PCS_STATUS3				0x01c
    18. 

  18. #define QPHY_V4_PCS_PCS_STATUS4				0x020
    19. 

  19. #define QPHY_V4_PCS_PCS_STATUS5				0x024
    20. 

  20. #define QPHY_V4_PCS_PCS_STATUS6				0x028
    21. 

  21. #define QPHY_V4_PCS_PCS_STATUS7				0x02c
    22. 

  22. #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS			0x030
    23. 

  23. #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS			0x034
    24. 

  24. #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS			0x038
    25. 

  25. #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS			0x03c
    26. 

  26. #define QPHY_V4_PCS_POWER_DOWN_CONTROL			0x040
    27. 

  27. #define QPHY_V4_PCS_START_CONTROL			0x044
    28. 

  28. #define QPHY_V4_PCS_INSIG_SW_CTRL1			0x048
    29. 

  29. #define QPHY_V4_PCS_INSIG_SW_CTRL2			0x04c
    30. 

  30. #define QPHY_V4_PCS_INSIG_SW_CTRL3			0x050
    31. 

  31. #define QPHY_V4_PCS_INSIG_SW_CTRL4			0x054
    32. 

  32. #define QPHY_V4_PCS_INSIG_SW_CTRL5			0x058
    33. 

  33. #define QPHY_V4_PCS_INSIG_SW_CTRL6			0x05c
    34. 

  34. #define QPHY_V4_PCS_INSIG_SW_CTRL7			0x060
    35. 

  35. #define QPHY_V4_PCS_INSIG_SW_CTRL8			0x064
    36. 

  36. #define QPHY_V4_PCS_INSIG_MX_CTRL1			0x068
    37. 

  37. #define QPHY_V4_PCS_INSIG_MX_CTRL2			0x06c
    38. 

  38. #define QPHY_V4_PCS_INSIG_MX_CTRL3			0x070
    39. 

  39. #define QPHY_V4_PCS_INSIG_MX_CTRL4			0x074
    40. 

  40. #define QPHY_V4_PCS_INSIG_MX_CTRL5			0x078
    41. 

  41. #define QPHY_V4_PCS_INSIG_MX_CTRL7			0x07c
    42. 

  42. #define QPHY_V4_PCS_INSIG_MX_CTRL8			0x080
    43. 

  43. #define QPHY_V4_PCS_OUTSIG_SW_CTRL1			0x084
    44. 

  44. #define QPHY_V4_PCS_OUTSIG_MX_CTRL1			0x088
    45. 

  45. #define QPHY_V4_PCS_CLAMP_ENABLE			0x08c
    46. 

  46. #define QPHY_V4_PCS_POWER_STATE_CONFIG1			0x090
    47. 

  47. #define QPHY_V4_PCS_POWER_STATE_CONFIG2			0x094
    48. 

  48. #define QPHY_V4_PCS_FLL_CNTRL1				0x098
    49. 

  49. #define QPHY_V4_PCS_FLL_CNTRL2				0x09c
    50. 

  50. #define QPHY_V4_PCS_FLL_CNT_VAL_L			0x0a0
    51. 

  51. #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL			0x0a4
    52. 

  52. #define QPHY_V4_PCS_FLL_MAN_CODE			0x0a8
    53. 

  53. #define QPHY_V4_PCS_TEST_CONTROL1			0x0ac
    54. 

  54. #define QPHY_V4_PCS_TEST_CONTROL2			0x0b0
    55. 

  55. #define QPHY_V4_PCS_TEST_CONTROL3			0x0b4
    56. 

  56. #define QPHY_V4_PCS_TEST_CONTROL4			0x0b8
    57. 

  57. #define QPHY_V4_PCS_TEST_CONTROL5			0x0bc
    58. 

  58. #define QPHY_V4_PCS_TEST_CONTROL6			0x0c0
    59. 

  59. #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1			0x0c4
    60. 

  60. #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2			0x0c8
    61. 

  61. #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3			0x0cc
    62. 

  62. #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4			0x0d0
    63. 

  63. #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5			0x0d4
    64. 

  64. #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6			0x0d8
    65. 

  65. #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1			0x0dc
    66. 

  66. #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2			0x0e0
    67. 

  67. #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3			0x0e4
    68. 

  68. #define QPHY_V4_PCS_BIST_CTRL				0x0e8
    69. 

  69. #define QPHY_V4_PCS_PRBS_POLY0				0x0ec
    70. 

  70. #define QPHY_V4_PCS_PRBS_POLY1				0x0f0
    71. 

  71. #define QPHY_V4_PCS_FIXED_PAT0				0x0f4
    72. 

  72. #define QPHY_V4_PCS_FIXED_PAT1				0x0f8
    73. 

  73. #define QPHY_V4_PCS_FIXED_PAT2				0x0fc
    74. 

  74. #define QPHY_V4_PCS_FIXED_PAT3				0x100
    75. 

  75. #define QPHY_V4_PCS_FIXED_PAT4				0x104
    76. 

  76. #define QPHY_V4_PCS_FIXED_PAT5				0x108
    77. 

  77. #define QPHY_V4_PCS_FIXED_PAT6				0x10c
    78. 

  78. #define QPHY_V4_PCS_FIXED_PAT7				0x110
    79. 

  79. #define QPHY_V4_PCS_FIXED_PAT8				0x114
    80. 

  80. #define QPHY_V4_PCS_FIXED_PAT9				0x118
    81. 

  81. #define QPHY_V4_PCS_FIXED_PAT10				0x11c
    82. 

  82. #define QPHY_V4_PCS_FIXED_PAT11				0x120
    83. 

  83. #define QPHY_V4_PCS_FIXED_PAT12				0x124
    84. 

  84. #define QPHY_V4_PCS_FIXED_PAT13				0x128
    85. 

  85. #define QPHY_V4_PCS_FIXED_PAT14				0x12c
    86. 

  86. #define QPHY_V4_PCS_FIXED_PAT15				0x130
    87. 

  87. #define QPHY_V4_PCS_TXMGN_CONFIG			0x134
    88. 

  88. #define QPHY_V4_PCS_G12S1_TXMGN_V0			0x138
    89. 

  89. #define QPHY_V4_PCS_G12S1_TXMGN_V1			0x13c
    90. 

  90. #define QPHY_V4_PCS_G12S1_TXMGN_V2			0x140
    91. 

  91. #define QPHY_V4_PCS_G12S1_TXMGN_V3			0x144
    92. 

  92. #define QPHY_V4_PCS_G12S1_TXMGN_V4			0x148
    93. 

  93. #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS			0x14c
    94. 

  94. #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS			0x150
    95. 

  95. #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS			0x154
    96. 

  96. #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS			0x158
    97. 

  97. #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS			0x15c
    98. 

  98. #define QPHY_V4_PCS_G3S2_TXMGN_MAIN			0x160
    99. 

  99. #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS			0x164
    100. 

  100. #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB			0x168
    101. 

  101. #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB		0x16c
    102. 

  102. #define QPHY_V4_PCS_G3S2_PRE_GAIN			0x170
    103. 

  103. #define QPHY_V4_PCS_G3S2_POST_GAIN			0x174
    104. 

  104. #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET		0x178
    105. 

  105. #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS			0x17c
    106. 

  106. #define QPHY_V4_PCS_G3S2_POST_GAIN_RS			0x180
    107. 

  107. #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS		0x184
    108. 

  108. #define QPHY_V4_PCS_RX_SIGDET_LVL			0x188
    109. 

  109. #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL		0x18c
    110. 

  110. #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L		0x190
    111. 

  111. #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H		0x194
    112. 

  112. #define QPHY_V4_PCS_RATE_SLEW_CNTRL1			0x198
    113. 

  113. #define QPHY_V4_PCS_RATE_SLEW_CNTRL2			0x19c
    114. 

  114. #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x1a0
    115. 

  115. #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L	0x1a4
    116. 

  116. #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H	0x1a8
    117. 

  117. #define QPHY_V4_PCS_TSYNC_RSYNC_TIME			0x1ac
    118. 

  118. #define QPHY_V4_PCS_CDR_RESET_TIME			0x1b0
    119. 

  119. #define QPHY_V4_PCS_TSYNC_DLY_TIME			0x1b4
    120. 

  120. #define QPHY_V4_PCS_ELECIDLE_DLY_SEL			0x1b8
    121. 

  121. #define QPHY_V4_PCS_CMN_ACK_OUT_SEL			0x1bc
    122. 

  122. #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1		0x1c0
    123. 

  123. #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2		0x1c4
    124. 

  124. #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3		0x1c8
    125. 

  125. #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4		0x1cc
    126. 

  126. #define QPHY_V4_PCS_PCS_TX_RX_CONFIG			0x1d0
    127. 

  127. #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL			0x1d4
    128. 

  128. #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG			0x1d8
    129. 

  129. #define QPHY_V4_PCS_EQ_CONFIG1				0x1dc
    130. 

  130. #define QPHY_V4_PCS_EQ_CONFIG2				0x1e0
    131. 

  131. #define QPHY_V4_PCS_EQ_CONFIG3				0x1e4
    132. 

  132. #define QPHY_V4_PCS_EQ_CONFIG4				0x1e8
    133. 

  133. #define QPHY_V4_PCS_EQ_CONFIG5				0x1ec
    134. 

  134. 

  135. #endif
    136.