phy-qcom-qmp-pcs-pcie-v5_20.h 665 B

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2017, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
  6. #define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
  7. /* Only for QMP V5_20 PHY - PCIe PCS registers */
  8. #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
  9. #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
  10. #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
  11. #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
  12. #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
  13. #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
  14. #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
  15. #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
  16. #endif