arm_spe_pmu.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Perf support for the Statistical Profiling Extension, introduced as
  4. * part of ARMv8.2.
  5. *
  6. * Copyright (C) 2016 ARM Limited
  7. *
  8. * Author: Will Deacon <[email protected]>
  9. */
  10. #define PMUNAME "arm_spe"
  11. #define DRVNAME PMUNAME "_pmu"
  12. #define pr_fmt(fmt) DRVNAME ": " fmt
  13. #include <linux/bitops.h>
  14. #include <linux/bug.h>
  15. #include <linux/capability.h>
  16. #include <linux/cpuhotplug.h>
  17. #include <linux/cpumask.h>
  18. #include <linux/device.h>
  19. #include <linux/errno.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/irq.h>
  22. #include <linux/kernel.h>
  23. #include <linux/list.h>
  24. #include <linux/module.h>
  25. #include <linux/of_address.h>
  26. #include <linux/of_device.h>
  27. #include <linux/perf_event.h>
  28. #include <linux/perf/arm_pmu.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/printk.h>
  31. #include <linux/slab.h>
  32. #include <linux/smp.h>
  33. #include <linux/vmalloc.h>
  34. #include <asm/barrier.h>
  35. #include <asm/cpufeature.h>
  36. #include <asm/mmu.h>
  37. #include <asm/sysreg.h>
  38. /*
  39. * Cache if the event is allowed to trace Context information.
  40. * This allows us to perform the check, i.e, perfmon_capable(),
  41. * in the context of the event owner, once, during the event_init().
  42. */
  43. #define SPE_PMU_HW_FLAGS_CX 0x00001
  44. static_assert((PERF_EVENT_FLAG_ARCH & SPE_PMU_HW_FLAGS_CX) == SPE_PMU_HW_FLAGS_CX);
  45. static void set_spe_event_has_cx(struct perf_event *event)
  46. {
  47. if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && perfmon_capable())
  48. event->hw.flags |= SPE_PMU_HW_FLAGS_CX;
  49. }
  50. static bool get_spe_event_has_cx(struct perf_event *event)
  51. {
  52. return !!(event->hw.flags & SPE_PMU_HW_FLAGS_CX);
  53. }
  54. #define ARM_SPE_BUF_PAD_BYTE 0
  55. struct arm_spe_pmu_buf {
  56. int nr_pages;
  57. bool snapshot;
  58. void *base;
  59. };
  60. struct arm_spe_pmu {
  61. struct pmu pmu;
  62. struct platform_device *pdev;
  63. cpumask_t supported_cpus;
  64. struct hlist_node hotplug_node;
  65. int irq; /* PPI */
  66. u16 pmsver;
  67. u16 min_period;
  68. u16 counter_sz;
  69. #define SPE_PMU_FEAT_FILT_EVT (1UL << 0)
  70. #define SPE_PMU_FEAT_FILT_TYP (1UL << 1)
  71. #define SPE_PMU_FEAT_FILT_LAT (1UL << 2)
  72. #define SPE_PMU_FEAT_ARCH_INST (1UL << 3)
  73. #define SPE_PMU_FEAT_LDS (1UL << 4)
  74. #define SPE_PMU_FEAT_ERND (1UL << 5)
  75. #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63)
  76. u64 features;
  77. u16 max_record_sz;
  78. u16 align;
  79. struct perf_output_handle __percpu *handle;
  80. };
  81. #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu))
  82. /* Convert a free-running index from perf into an SPE buffer offset */
  83. #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
  84. /* Keep track of our dynamic hotplug state */
  85. static enum cpuhp_state arm_spe_pmu_online;
  86. enum arm_spe_pmu_buf_fault_action {
  87. SPE_PMU_BUF_FAULT_ACT_SPURIOUS,
  88. SPE_PMU_BUF_FAULT_ACT_FATAL,
  89. SPE_PMU_BUF_FAULT_ACT_OK,
  90. };
  91. /* This sysfs gunk was really good fun to write. */
  92. enum arm_spe_pmu_capabilities {
  93. SPE_PMU_CAP_ARCH_INST = 0,
  94. SPE_PMU_CAP_ERND,
  95. SPE_PMU_CAP_FEAT_MAX,
  96. SPE_PMU_CAP_CNT_SZ = SPE_PMU_CAP_FEAT_MAX,
  97. SPE_PMU_CAP_MIN_IVAL,
  98. };
  99. static int arm_spe_pmu_feat_caps[SPE_PMU_CAP_FEAT_MAX] = {
  100. [SPE_PMU_CAP_ARCH_INST] = SPE_PMU_FEAT_ARCH_INST,
  101. [SPE_PMU_CAP_ERND] = SPE_PMU_FEAT_ERND,
  102. };
  103. static u32 arm_spe_pmu_cap_get(struct arm_spe_pmu *spe_pmu, int cap)
  104. {
  105. if (cap < SPE_PMU_CAP_FEAT_MAX)
  106. return !!(spe_pmu->features & arm_spe_pmu_feat_caps[cap]);
  107. switch (cap) {
  108. case SPE_PMU_CAP_CNT_SZ:
  109. return spe_pmu->counter_sz;
  110. case SPE_PMU_CAP_MIN_IVAL:
  111. return spe_pmu->min_period;
  112. default:
  113. WARN(1, "unknown cap %d\n", cap);
  114. }
  115. return 0;
  116. }
  117. static ssize_t arm_spe_pmu_cap_show(struct device *dev,
  118. struct device_attribute *attr,
  119. char *buf)
  120. {
  121. struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev);
  122. struct dev_ext_attribute *ea =
  123. container_of(attr, struct dev_ext_attribute, attr);
  124. int cap = (long)ea->var;
  125. return sysfs_emit(buf, "%u\n", arm_spe_pmu_cap_get(spe_pmu, cap));
  126. }
  127. #define SPE_EXT_ATTR_ENTRY(_name, _func, _var) \
  128. &((struct dev_ext_attribute[]) { \
  129. { __ATTR(_name, S_IRUGO, _func, NULL), (void *)_var } \
  130. })[0].attr.attr
  131. #define SPE_CAP_EXT_ATTR_ENTRY(_name, _var) \
  132. SPE_EXT_ATTR_ENTRY(_name, arm_spe_pmu_cap_show, _var)
  133. static struct attribute *arm_spe_pmu_cap_attr[] = {
  134. SPE_CAP_EXT_ATTR_ENTRY(arch_inst, SPE_PMU_CAP_ARCH_INST),
  135. SPE_CAP_EXT_ATTR_ENTRY(ernd, SPE_PMU_CAP_ERND),
  136. SPE_CAP_EXT_ATTR_ENTRY(count_size, SPE_PMU_CAP_CNT_SZ),
  137. SPE_CAP_EXT_ATTR_ENTRY(min_interval, SPE_PMU_CAP_MIN_IVAL),
  138. NULL,
  139. };
  140. static const struct attribute_group arm_spe_pmu_cap_group = {
  141. .name = "caps",
  142. .attrs = arm_spe_pmu_cap_attr,
  143. };
  144. /* User ABI */
  145. #define ATTR_CFG_FLD_ts_enable_CFG config /* PMSCR_EL1.TS */
  146. #define ATTR_CFG_FLD_ts_enable_LO 0
  147. #define ATTR_CFG_FLD_ts_enable_HI 0
  148. #define ATTR_CFG_FLD_pa_enable_CFG config /* PMSCR_EL1.PA */
  149. #define ATTR_CFG_FLD_pa_enable_LO 1
  150. #define ATTR_CFG_FLD_pa_enable_HI 1
  151. #define ATTR_CFG_FLD_pct_enable_CFG config /* PMSCR_EL1.PCT */
  152. #define ATTR_CFG_FLD_pct_enable_LO 2
  153. #define ATTR_CFG_FLD_pct_enable_HI 2
  154. #define ATTR_CFG_FLD_jitter_CFG config /* PMSIRR_EL1.RND */
  155. #define ATTR_CFG_FLD_jitter_LO 16
  156. #define ATTR_CFG_FLD_jitter_HI 16
  157. #define ATTR_CFG_FLD_branch_filter_CFG config /* PMSFCR_EL1.B */
  158. #define ATTR_CFG_FLD_branch_filter_LO 32
  159. #define ATTR_CFG_FLD_branch_filter_HI 32
  160. #define ATTR_CFG_FLD_load_filter_CFG config /* PMSFCR_EL1.LD */
  161. #define ATTR_CFG_FLD_load_filter_LO 33
  162. #define ATTR_CFG_FLD_load_filter_HI 33
  163. #define ATTR_CFG_FLD_store_filter_CFG config /* PMSFCR_EL1.ST */
  164. #define ATTR_CFG_FLD_store_filter_LO 34
  165. #define ATTR_CFG_FLD_store_filter_HI 34
  166. #define ATTR_CFG_FLD_event_filter_CFG config1 /* PMSEVFR_EL1 */
  167. #define ATTR_CFG_FLD_event_filter_LO 0
  168. #define ATTR_CFG_FLD_event_filter_HI 63
  169. #define ATTR_CFG_FLD_min_latency_CFG config2 /* PMSLATFR_EL1.MINLAT */
  170. #define ATTR_CFG_FLD_min_latency_LO 0
  171. #define ATTR_CFG_FLD_min_latency_HI 11
  172. /* Why does everything I do descend into this? */
  173. #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \
  174. (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi
  175. #define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \
  176. __GEN_PMU_FORMAT_ATTR(cfg, lo, hi)
  177. #define GEN_PMU_FORMAT_ATTR(name) \
  178. PMU_FORMAT_ATTR(name, \
  179. _GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG, \
  180. ATTR_CFG_FLD_##name##_LO, \
  181. ATTR_CFG_FLD_##name##_HI))
  182. #define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \
  183. ((((attr)->cfg) >> lo) & GENMASK(hi - lo, 0))
  184. #define ATTR_CFG_GET_FLD(attr, name) \
  185. _ATTR_CFG_GET_FLD(attr, \
  186. ATTR_CFG_FLD_##name##_CFG, \
  187. ATTR_CFG_FLD_##name##_LO, \
  188. ATTR_CFG_FLD_##name##_HI)
  189. GEN_PMU_FORMAT_ATTR(ts_enable);
  190. GEN_PMU_FORMAT_ATTR(pa_enable);
  191. GEN_PMU_FORMAT_ATTR(pct_enable);
  192. GEN_PMU_FORMAT_ATTR(jitter);
  193. GEN_PMU_FORMAT_ATTR(branch_filter);
  194. GEN_PMU_FORMAT_ATTR(load_filter);
  195. GEN_PMU_FORMAT_ATTR(store_filter);
  196. GEN_PMU_FORMAT_ATTR(event_filter);
  197. GEN_PMU_FORMAT_ATTR(min_latency);
  198. static struct attribute *arm_spe_pmu_formats_attr[] = {
  199. &format_attr_ts_enable.attr,
  200. &format_attr_pa_enable.attr,
  201. &format_attr_pct_enable.attr,
  202. &format_attr_jitter.attr,
  203. &format_attr_branch_filter.attr,
  204. &format_attr_load_filter.attr,
  205. &format_attr_store_filter.attr,
  206. &format_attr_event_filter.attr,
  207. &format_attr_min_latency.attr,
  208. NULL,
  209. };
  210. static const struct attribute_group arm_spe_pmu_format_group = {
  211. .name = "format",
  212. .attrs = arm_spe_pmu_formats_attr,
  213. };
  214. static ssize_t cpumask_show(struct device *dev,
  215. struct device_attribute *attr, char *buf)
  216. {
  217. struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev);
  218. return cpumap_print_to_pagebuf(true, buf, &spe_pmu->supported_cpus);
  219. }
  220. static DEVICE_ATTR_RO(cpumask);
  221. static struct attribute *arm_spe_pmu_attrs[] = {
  222. &dev_attr_cpumask.attr,
  223. NULL,
  224. };
  225. static const struct attribute_group arm_spe_pmu_group = {
  226. .attrs = arm_spe_pmu_attrs,
  227. };
  228. static const struct attribute_group *arm_spe_pmu_attr_groups[] = {
  229. &arm_spe_pmu_group,
  230. &arm_spe_pmu_cap_group,
  231. &arm_spe_pmu_format_group,
  232. NULL,
  233. };
  234. /* Convert between user ABI and register values */
  235. static u64 arm_spe_event_to_pmscr(struct perf_event *event)
  236. {
  237. struct perf_event_attr *attr = &event->attr;
  238. u64 reg = 0;
  239. reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT;
  240. reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT;
  241. reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT;
  242. if (!attr->exclude_user)
  243. reg |= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT);
  244. if (!attr->exclude_kernel)
  245. reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT);
  246. if (get_spe_event_has_cx(event))
  247. reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT);
  248. return reg;
  249. }
  250. static void arm_spe_event_sanitise_period(struct perf_event *event)
  251. {
  252. struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
  253. u64 period = event->hw.sample_period;
  254. u64 max_period = SYS_PMSIRR_EL1_INTERVAL_MASK
  255. << SYS_PMSIRR_EL1_INTERVAL_SHIFT;
  256. if (period < spe_pmu->min_period)
  257. period = spe_pmu->min_period;
  258. else if (period > max_period)
  259. period = max_period;
  260. else
  261. period &= max_period;
  262. event->hw.sample_period = period;
  263. }
  264. static u64 arm_spe_event_to_pmsirr(struct perf_event *event)
  265. {
  266. struct perf_event_attr *attr = &event->attr;
  267. u64 reg = 0;
  268. arm_spe_event_sanitise_period(event);
  269. reg |= ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT;
  270. reg |= event->hw.sample_period;
  271. return reg;
  272. }
  273. static u64 arm_spe_event_to_pmsfcr(struct perf_event *event)
  274. {
  275. struct perf_event_attr *attr = &event->attr;
  276. u64 reg = 0;
  277. reg |= ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT;
  278. reg |= ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT;
  279. reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT;
  280. if (reg)
  281. reg |= BIT(SYS_PMSFCR_EL1_FT_SHIFT);
  282. if (ATTR_CFG_GET_FLD(attr, event_filter))
  283. reg |= BIT(SYS_PMSFCR_EL1_FE_SHIFT);
  284. if (ATTR_CFG_GET_FLD(attr, min_latency))
  285. reg |= BIT(SYS_PMSFCR_EL1_FL_SHIFT);
  286. return reg;
  287. }
  288. static u64 arm_spe_event_to_pmsevfr(struct perf_event *event)
  289. {
  290. struct perf_event_attr *attr = &event->attr;
  291. return ATTR_CFG_GET_FLD(attr, event_filter);
  292. }
  293. static u64 arm_spe_event_to_pmslatfr(struct perf_event *event)
  294. {
  295. struct perf_event_attr *attr = &event->attr;
  296. return ATTR_CFG_GET_FLD(attr, min_latency)
  297. << SYS_PMSLATFR_EL1_MINLAT_SHIFT;
  298. }
  299. static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len)
  300. {
  301. struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
  302. u64 head = PERF_IDX2OFF(handle->head, buf);
  303. memset(buf->base + head, ARM_SPE_BUF_PAD_BYTE, len);
  304. if (!buf->snapshot)
  305. perf_aux_output_skip(handle, len);
  306. }
  307. static u64 arm_spe_pmu_next_snapshot_off(struct perf_output_handle *handle)
  308. {
  309. struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
  310. struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
  311. u64 head = PERF_IDX2OFF(handle->head, buf);
  312. u64 limit = buf->nr_pages * PAGE_SIZE;
  313. /*
  314. * The trace format isn't parseable in reverse, so clamp
  315. * the limit to half of the buffer size in snapshot mode
  316. * so that the worst case is half a buffer of records, as
  317. * opposed to a single record.
  318. */
  319. if (head < limit >> 1)
  320. limit >>= 1;
  321. /*
  322. * If we're within max_record_sz of the limit, we must
  323. * pad, move the head index and recompute the limit.
  324. */
  325. if (limit - head < spe_pmu->max_record_sz) {
  326. arm_spe_pmu_pad_buf(handle, limit - head);
  327. handle->head = PERF_IDX2OFF(limit, buf);
  328. limit = ((buf->nr_pages * PAGE_SIZE) >> 1) + handle->head;
  329. }
  330. return limit;
  331. }
  332. static u64 __arm_spe_pmu_next_off(struct perf_output_handle *handle)
  333. {
  334. struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
  335. struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
  336. const u64 bufsize = buf->nr_pages * PAGE_SIZE;
  337. u64 limit = bufsize;
  338. u64 head, tail, wakeup;
  339. /*
  340. * The head can be misaligned for two reasons:
  341. *
  342. * 1. The hardware left PMBPTR pointing to the first byte after
  343. * a record when generating a buffer management event.
  344. *
  345. * 2. We used perf_aux_output_skip to consume handle->size bytes
  346. * and CIRC_SPACE was used to compute the size, which always
  347. * leaves one entry free.
  348. *
  349. * Deal with this by padding to the next alignment boundary and
  350. * moving the head index. If we run out of buffer space, we'll
  351. * reduce handle->size to zero and end up reporting truncation.
  352. */
  353. head = PERF_IDX2OFF(handle->head, buf);
  354. if (!IS_ALIGNED(head, spe_pmu->align)) {
  355. unsigned long delta = roundup(head, spe_pmu->align) - head;
  356. delta = min(delta, handle->size);
  357. arm_spe_pmu_pad_buf(handle, delta);
  358. head = PERF_IDX2OFF(handle->head, buf);
  359. }
  360. /* If we've run out of free space, then nothing more to do */
  361. if (!handle->size)
  362. goto no_space;
  363. /* Compute the tail and wakeup indices now that we've aligned head */
  364. tail = PERF_IDX2OFF(handle->head + handle->size, buf);
  365. wakeup = PERF_IDX2OFF(handle->wakeup, buf);
  366. /*
  367. * Avoid clobbering unconsumed data. We know we have space, so
  368. * if we see head == tail we know that the buffer is empty. If
  369. * head > tail, then there's nothing to clobber prior to
  370. * wrapping.
  371. */
  372. if (head < tail)
  373. limit = round_down(tail, PAGE_SIZE);
  374. /*
  375. * Wakeup may be arbitrarily far into the future. If it's not in
  376. * the current generation, either we'll wrap before hitting it,
  377. * or it's in the past and has been handled already.
  378. *
  379. * If there's a wakeup before we wrap, arrange to be woken up by
  380. * the page boundary following it. Keep the tail boundary if
  381. * that's lower.
  382. */
  383. if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
  384. limit = min(limit, round_up(wakeup, PAGE_SIZE));
  385. if (limit > head)
  386. return limit;
  387. arm_spe_pmu_pad_buf(handle, handle->size);
  388. no_space:
  389. perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
  390. perf_aux_output_end(handle, 0);
  391. return 0;
  392. }
  393. static u64 arm_spe_pmu_next_off(struct perf_output_handle *handle)
  394. {
  395. struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
  396. struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
  397. u64 limit = __arm_spe_pmu_next_off(handle);
  398. u64 head = PERF_IDX2OFF(handle->head, buf);
  399. /*
  400. * If the head has come too close to the end of the buffer,
  401. * then pad to the end and recompute the limit.
  402. */
  403. if (limit && (limit - head < spe_pmu->max_record_sz)) {
  404. arm_spe_pmu_pad_buf(handle, limit - head);
  405. limit = __arm_spe_pmu_next_off(handle);
  406. }
  407. return limit;
  408. }
  409. static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle,
  410. struct perf_event *event)
  411. {
  412. u64 base, limit;
  413. struct arm_spe_pmu_buf *buf;
  414. /* Start a new aux session */
  415. buf = perf_aux_output_begin(handle, event);
  416. if (!buf) {
  417. event->hw.state |= PERF_HES_STOPPED;
  418. /*
  419. * We still need to clear the limit pointer, since the
  420. * profiler might only be disabled by virtue of a fault.
  421. */
  422. limit = 0;
  423. goto out_write_limit;
  424. }
  425. limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle)
  426. : arm_spe_pmu_next_off(handle);
  427. if (limit)
  428. limit |= BIT(SYS_PMBLIMITR_EL1_E_SHIFT);
  429. limit += (u64)buf->base;
  430. base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf);
  431. write_sysreg_s(base, SYS_PMBPTR_EL1);
  432. out_write_limit:
  433. write_sysreg_s(limit, SYS_PMBLIMITR_EL1);
  434. }
  435. static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle)
  436. {
  437. struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
  438. u64 offset, size;
  439. offset = read_sysreg_s(SYS_PMBPTR_EL1) - (u64)buf->base;
  440. size = offset - PERF_IDX2OFF(handle->head, buf);
  441. if (buf->snapshot)
  442. handle->head = offset;
  443. perf_aux_output_end(handle, size);
  444. }
  445. static void arm_spe_pmu_disable_and_drain_local(void)
  446. {
  447. /* Disable profiling at EL0 and EL1 */
  448. write_sysreg_s(0, SYS_PMSCR_EL1);
  449. isb();
  450. /* Drain any buffered data */
  451. psb_csync();
  452. dsb(nsh);
  453. /* Disable the profiling buffer */
  454. write_sysreg_s(0, SYS_PMBLIMITR_EL1);
  455. isb();
  456. }
  457. /* IRQ handling */
  458. static enum arm_spe_pmu_buf_fault_action
  459. arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle)
  460. {
  461. const char *err_str;
  462. u64 pmbsr;
  463. enum arm_spe_pmu_buf_fault_action ret;
  464. /*
  465. * Ensure new profiling data is visible to the CPU and any external
  466. * aborts have been resolved.
  467. */
  468. psb_csync();
  469. dsb(nsh);
  470. /* Ensure hardware updates to PMBPTR_EL1 are visible */
  471. isb();
  472. /* Service required? */
  473. pmbsr = read_sysreg_s(SYS_PMBSR_EL1);
  474. if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT)))
  475. return SPE_PMU_BUF_FAULT_ACT_SPURIOUS;
  476. /*
  477. * If we've lost data, disable profiling and also set the PARTIAL
  478. * flag to indicate that the last record is corrupted.
  479. */
  480. if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT))
  481. perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED |
  482. PERF_AUX_FLAG_PARTIAL);
  483. /* Report collisions to userspace so that it can up the period */
  484. if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT))
  485. perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION);
  486. /* We only expect buffer management events */
  487. switch (pmbsr & (SYS_PMBSR_EL1_EC_MASK << SYS_PMBSR_EL1_EC_SHIFT)) {
  488. case SYS_PMBSR_EL1_EC_BUF:
  489. /* Handled below */
  490. break;
  491. case SYS_PMBSR_EL1_EC_FAULT_S1:
  492. case SYS_PMBSR_EL1_EC_FAULT_S2:
  493. err_str = "Unexpected buffer fault";
  494. goto out_err;
  495. default:
  496. err_str = "Unknown error code";
  497. goto out_err;
  498. }
  499. /* Buffer management event */
  500. switch (pmbsr &
  501. (SYS_PMBSR_EL1_BUF_BSC_MASK << SYS_PMBSR_EL1_BUF_BSC_SHIFT)) {
  502. case SYS_PMBSR_EL1_BUF_BSC_FULL:
  503. ret = SPE_PMU_BUF_FAULT_ACT_OK;
  504. goto out_stop;
  505. default:
  506. err_str = "Unknown buffer status code";
  507. }
  508. out_err:
  509. pr_err_ratelimited("%s on CPU %d [PMBSR=0x%016llx, PMBPTR=0x%016llx, PMBLIMITR=0x%016llx]\n",
  510. err_str, smp_processor_id(), pmbsr,
  511. read_sysreg_s(SYS_PMBPTR_EL1),
  512. read_sysreg_s(SYS_PMBLIMITR_EL1));
  513. ret = SPE_PMU_BUF_FAULT_ACT_FATAL;
  514. out_stop:
  515. arm_spe_perf_aux_output_end(handle);
  516. return ret;
  517. }
  518. static irqreturn_t arm_spe_pmu_irq_handler(int irq, void *dev)
  519. {
  520. struct perf_output_handle *handle = dev;
  521. struct perf_event *event = handle->event;
  522. enum arm_spe_pmu_buf_fault_action act;
  523. if (!perf_get_aux(handle))
  524. return IRQ_NONE;
  525. act = arm_spe_pmu_buf_get_fault_act(handle);
  526. if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS)
  527. return IRQ_NONE;
  528. /*
  529. * Ensure perf callbacks have completed, which may disable the
  530. * profiling buffer in response to a TRUNCATION flag.
  531. */
  532. irq_work_run();
  533. switch (act) {
  534. case SPE_PMU_BUF_FAULT_ACT_FATAL:
  535. /*
  536. * If a fatal exception occurred then leaving the profiling
  537. * buffer enabled is a recipe waiting to happen. Since
  538. * fatal faults don't always imply truncation, make sure
  539. * that the profiling buffer is disabled explicitly before
  540. * clearing the syndrome register.
  541. */
  542. arm_spe_pmu_disable_and_drain_local();
  543. break;
  544. case SPE_PMU_BUF_FAULT_ACT_OK:
  545. /*
  546. * We handled the fault (the buffer was full), so resume
  547. * profiling as long as we didn't detect truncation.
  548. * PMBPTR might be misaligned, but we'll burn that bridge
  549. * when we get to it.
  550. */
  551. if (!(handle->aux_flags & PERF_AUX_FLAG_TRUNCATED)) {
  552. arm_spe_perf_aux_output_begin(handle, event);
  553. isb();
  554. }
  555. break;
  556. case SPE_PMU_BUF_FAULT_ACT_SPURIOUS:
  557. /* We've seen you before, but GCC has the memory of a sieve. */
  558. break;
  559. }
  560. /* The buffer pointers are now sane, so resume profiling. */
  561. write_sysreg_s(0, SYS_PMBSR_EL1);
  562. return IRQ_HANDLED;
  563. }
  564. static u64 arm_spe_pmsevfr_res0(u16 pmsver)
  565. {
  566. switch (pmsver) {
  567. case ID_AA64DFR0_EL1_PMSVer_IMP:
  568. return SYS_PMSEVFR_EL1_RES0_8_2;
  569. case ID_AA64DFR0_EL1_PMSVer_V1P1:
  570. /* Return the highest version we support in default */
  571. default:
  572. return SYS_PMSEVFR_EL1_RES0_8_3;
  573. }
  574. }
  575. /* Perf callbacks */
  576. static int arm_spe_pmu_event_init(struct perf_event *event)
  577. {
  578. u64 reg;
  579. struct perf_event_attr *attr = &event->attr;
  580. struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
  581. /* This is, of course, deeply driver-specific */
  582. if (attr->type != event->pmu->type)
  583. return -ENOENT;
  584. if (event->cpu >= 0 &&
  585. !cpumask_test_cpu(event->cpu, &spe_pmu->supported_cpus))
  586. return -ENOENT;
  587. if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver))
  588. return -EOPNOTSUPP;
  589. if (attr->exclude_idle)
  590. return -EOPNOTSUPP;
  591. /*
  592. * Feedback-directed frequency throttling doesn't work when we
  593. * have a buffer of samples. We'd need to manually count the
  594. * samples in the buffer when it fills up and adjust the event
  595. * count to reflect that. Instead, just force the user to specify
  596. * a sample period.
  597. */
  598. if (attr->freq)
  599. return -EINVAL;
  600. reg = arm_spe_event_to_pmsfcr(event);
  601. if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) &&
  602. !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT))
  603. return -EOPNOTSUPP;
  604. if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) &&
  605. !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP))
  606. return -EOPNOTSUPP;
  607. if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) &&
  608. !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT))
  609. return -EOPNOTSUPP;
  610. set_spe_event_has_cx(event);
  611. reg = arm_spe_event_to_pmscr(event);
  612. if (!perfmon_capable() &&
  613. (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) |
  614. BIT(SYS_PMSCR_EL1_PCT_SHIFT))))
  615. return -EACCES;
  616. return 0;
  617. }
  618. static void arm_spe_pmu_start(struct perf_event *event, int flags)
  619. {
  620. u64 reg;
  621. struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
  622. struct hw_perf_event *hwc = &event->hw;
  623. struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle);
  624. hwc->state = 0;
  625. arm_spe_perf_aux_output_begin(handle, event);
  626. if (hwc->state)
  627. return;
  628. reg = arm_spe_event_to_pmsfcr(event);
  629. write_sysreg_s(reg, SYS_PMSFCR_EL1);
  630. reg = arm_spe_event_to_pmsevfr(event);
  631. write_sysreg_s(reg, SYS_PMSEVFR_EL1);
  632. reg = arm_spe_event_to_pmslatfr(event);
  633. write_sysreg_s(reg, SYS_PMSLATFR_EL1);
  634. if (flags & PERF_EF_RELOAD) {
  635. reg = arm_spe_event_to_pmsirr(event);
  636. write_sysreg_s(reg, SYS_PMSIRR_EL1);
  637. isb();
  638. reg = local64_read(&hwc->period_left);
  639. write_sysreg_s(reg, SYS_PMSICR_EL1);
  640. }
  641. reg = arm_spe_event_to_pmscr(event);
  642. isb();
  643. write_sysreg_s(reg, SYS_PMSCR_EL1);
  644. }
  645. static void arm_spe_pmu_stop(struct perf_event *event, int flags)
  646. {
  647. struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
  648. struct hw_perf_event *hwc = &event->hw;
  649. struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle);
  650. /* If we're already stopped, then nothing to do */
  651. if (hwc->state & PERF_HES_STOPPED)
  652. return;
  653. /* Stop all trace generation */
  654. arm_spe_pmu_disable_and_drain_local();
  655. if (flags & PERF_EF_UPDATE) {
  656. /*
  657. * If there's a fault pending then ensure we contain it
  658. * to this buffer, since we might be on the context-switch
  659. * path.
  660. */
  661. if (perf_get_aux(handle)) {
  662. enum arm_spe_pmu_buf_fault_action act;
  663. act = arm_spe_pmu_buf_get_fault_act(handle);
  664. if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS)
  665. arm_spe_perf_aux_output_end(handle);
  666. else
  667. write_sysreg_s(0, SYS_PMBSR_EL1);
  668. }
  669. /*
  670. * This may also contain ECOUNT, but nobody else should
  671. * be looking at period_left, since we forbid frequency
  672. * based sampling.
  673. */
  674. local64_set(&hwc->period_left, read_sysreg_s(SYS_PMSICR_EL1));
  675. hwc->state |= PERF_HES_UPTODATE;
  676. }
  677. hwc->state |= PERF_HES_STOPPED;
  678. }
  679. static int arm_spe_pmu_add(struct perf_event *event, int flags)
  680. {
  681. int ret = 0;
  682. struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
  683. struct hw_perf_event *hwc = &event->hw;
  684. int cpu = event->cpu == -1 ? smp_processor_id() : event->cpu;
  685. if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
  686. return -ENOENT;
  687. hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
  688. if (flags & PERF_EF_START) {
  689. arm_spe_pmu_start(event, PERF_EF_RELOAD);
  690. if (hwc->state & PERF_HES_STOPPED)
  691. ret = -EINVAL;
  692. }
  693. return ret;
  694. }
  695. static void arm_spe_pmu_del(struct perf_event *event, int flags)
  696. {
  697. arm_spe_pmu_stop(event, PERF_EF_UPDATE);
  698. }
  699. static void arm_spe_pmu_read(struct perf_event *event)
  700. {
  701. }
  702. static void *arm_spe_pmu_setup_aux(struct perf_event *event, void **pages,
  703. int nr_pages, bool snapshot)
  704. {
  705. int i, cpu = event->cpu;
  706. struct page **pglist;
  707. struct arm_spe_pmu_buf *buf;
  708. /* We need at least two pages for this to work. */
  709. if (nr_pages < 2)
  710. return NULL;
  711. /*
  712. * We require an even number of pages for snapshot mode, so that
  713. * we can effectively treat the buffer as consisting of two equal
  714. * parts and give userspace a fighting chance of getting some
  715. * useful data out of it.
  716. */
  717. if (snapshot && (nr_pages & 1))
  718. return NULL;
  719. if (cpu == -1)
  720. cpu = raw_smp_processor_id();
  721. buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, cpu_to_node(cpu));
  722. if (!buf)
  723. return NULL;
  724. pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
  725. if (!pglist)
  726. goto out_free_buf;
  727. for (i = 0; i < nr_pages; ++i)
  728. pglist[i] = virt_to_page(pages[i]);
  729. buf->base = vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
  730. if (!buf->base)
  731. goto out_free_pglist;
  732. buf->nr_pages = nr_pages;
  733. buf->snapshot = snapshot;
  734. kfree(pglist);
  735. return buf;
  736. out_free_pglist:
  737. kfree(pglist);
  738. out_free_buf:
  739. kfree(buf);
  740. return NULL;
  741. }
  742. static void arm_spe_pmu_free_aux(void *aux)
  743. {
  744. struct arm_spe_pmu_buf *buf = aux;
  745. vunmap(buf->base);
  746. kfree(buf);
  747. }
  748. /* Initialisation and teardown functions */
  749. static int arm_spe_pmu_perf_init(struct arm_spe_pmu *spe_pmu)
  750. {
  751. static atomic_t pmu_idx = ATOMIC_INIT(-1);
  752. int idx;
  753. char *name;
  754. struct device *dev = &spe_pmu->pdev->dev;
  755. spe_pmu->pmu = (struct pmu) {
  756. .module = THIS_MODULE,
  757. .capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE,
  758. .attr_groups = arm_spe_pmu_attr_groups,
  759. /*
  760. * We hitch a ride on the software context here, so that
  761. * we can support per-task profiling (which is not possible
  762. * with the invalid context as it doesn't get sched callbacks).
  763. * This requires that userspace either uses a dummy event for
  764. * perf_event_open, since the aux buffer is not setup until
  765. * a subsequent mmap, or creates the profiling event in a
  766. * disabled state and explicitly PERF_EVENT_IOC_ENABLEs it
  767. * once the buffer has been created.
  768. */
  769. .task_ctx_nr = perf_sw_context,
  770. .event_init = arm_spe_pmu_event_init,
  771. .add = arm_spe_pmu_add,
  772. .del = arm_spe_pmu_del,
  773. .start = arm_spe_pmu_start,
  774. .stop = arm_spe_pmu_stop,
  775. .read = arm_spe_pmu_read,
  776. .setup_aux = arm_spe_pmu_setup_aux,
  777. .free_aux = arm_spe_pmu_free_aux,
  778. };
  779. idx = atomic_inc_return(&pmu_idx);
  780. name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", PMUNAME, idx);
  781. if (!name) {
  782. dev_err(dev, "failed to allocate name for pmu %d\n", idx);
  783. return -ENOMEM;
  784. }
  785. return perf_pmu_register(&spe_pmu->pmu, name, -1);
  786. }
  787. static void arm_spe_pmu_perf_destroy(struct arm_spe_pmu *spe_pmu)
  788. {
  789. perf_pmu_unregister(&spe_pmu->pmu);
  790. }
  791. static void __arm_spe_pmu_dev_probe(void *info)
  792. {
  793. int fld;
  794. u64 reg;
  795. struct arm_spe_pmu *spe_pmu = info;
  796. struct device *dev = &spe_pmu->pdev->dev;
  797. fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64DFR0_EL1),
  798. ID_AA64DFR0_EL1_PMSVer_SHIFT);
  799. if (!fld) {
  800. dev_err(dev,
  801. "unsupported ID_AA64DFR0_EL1.PMSVer [%d] on CPU %d\n",
  802. fld, smp_processor_id());
  803. return;
  804. }
  805. spe_pmu->pmsver = (u16)fld;
  806. /* Read PMBIDR first to determine whether or not we have access */
  807. reg = read_sysreg_s(SYS_PMBIDR_EL1);
  808. if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) {
  809. dev_err(dev,
  810. "profiling buffer owned by higher exception level\n");
  811. return;
  812. }
  813. /* Minimum alignment. If it's out-of-range, then fail the probe */
  814. fld = reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK;
  815. spe_pmu->align = 1 << fld;
  816. if (spe_pmu->align > SZ_2K) {
  817. dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n",
  818. fld, smp_processor_id());
  819. return;
  820. }
  821. /* It's now safe to read PMSIDR and figure out what we've got */
  822. reg = read_sysreg_s(SYS_PMSIDR_EL1);
  823. if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT))
  824. spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT;
  825. if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT))
  826. spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP;
  827. if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT))
  828. spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT;
  829. if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT))
  830. spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST;
  831. if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT))
  832. spe_pmu->features |= SPE_PMU_FEAT_LDS;
  833. if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT))
  834. spe_pmu->features |= SPE_PMU_FEAT_ERND;
  835. /* This field has a spaced out encoding, so just use a look-up */
  836. fld = reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MASK;
  837. switch (fld) {
  838. case 0:
  839. spe_pmu->min_period = 256;
  840. break;
  841. case 2:
  842. spe_pmu->min_period = 512;
  843. break;
  844. case 3:
  845. spe_pmu->min_period = 768;
  846. break;
  847. case 4:
  848. spe_pmu->min_period = 1024;
  849. break;
  850. case 5:
  851. spe_pmu->min_period = 1536;
  852. break;
  853. case 6:
  854. spe_pmu->min_period = 2048;
  855. break;
  856. case 7:
  857. spe_pmu->min_period = 3072;
  858. break;
  859. default:
  860. dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n",
  861. fld);
  862. fallthrough;
  863. case 8:
  864. spe_pmu->min_period = 4096;
  865. }
  866. /* Maximum record size. If it's out-of-range, then fail the probe */
  867. fld = reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK;
  868. spe_pmu->max_record_sz = 1 << fld;
  869. if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) {
  870. dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n",
  871. fld, smp_processor_id());
  872. return;
  873. }
  874. fld = reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_MASK;
  875. switch (fld) {
  876. default:
  877. dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n",
  878. fld);
  879. fallthrough;
  880. case 2:
  881. spe_pmu->counter_sz = 12;
  882. break;
  883. case 3:
  884. spe_pmu->counter_sz = 16;
  885. }
  886. dev_info(dev,
  887. "probed for CPUs %*pbl [max_record_sz %u, align %u, features 0x%llx]\n",
  888. cpumask_pr_args(&spe_pmu->supported_cpus),
  889. spe_pmu->max_record_sz, spe_pmu->align, spe_pmu->features);
  890. spe_pmu->features |= SPE_PMU_FEAT_DEV_PROBED;
  891. }
  892. static void __arm_spe_pmu_reset_local(void)
  893. {
  894. /*
  895. * This is probably overkill, as we have no idea where we're
  896. * draining any buffered data to...
  897. */
  898. arm_spe_pmu_disable_and_drain_local();
  899. /* Reset the buffer base pointer */
  900. write_sysreg_s(0, SYS_PMBPTR_EL1);
  901. isb();
  902. /* Clear any pending management interrupts */
  903. write_sysreg_s(0, SYS_PMBSR_EL1);
  904. isb();
  905. }
  906. static void __arm_spe_pmu_setup_one(void *info)
  907. {
  908. struct arm_spe_pmu *spe_pmu = info;
  909. __arm_spe_pmu_reset_local();
  910. enable_percpu_irq(spe_pmu->irq, IRQ_TYPE_NONE);
  911. }
  912. static void __arm_spe_pmu_stop_one(void *info)
  913. {
  914. struct arm_spe_pmu *spe_pmu = info;
  915. disable_percpu_irq(spe_pmu->irq);
  916. __arm_spe_pmu_reset_local();
  917. }
  918. static int arm_spe_pmu_cpu_startup(unsigned int cpu, struct hlist_node *node)
  919. {
  920. struct arm_spe_pmu *spe_pmu;
  921. spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node);
  922. if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
  923. return 0;
  924. __arm_spe_pmu_setup_one(spe_pmu);
  925. return 0;
  926. }
  927. static int arm_spe_pmu_cpu_teardown(unsigned int cpu, struct hlist_node *node)
  928. {
  929. struct arm_spe_pmu *spe_pmu;
  930. spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node);
  931. if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
  932. return 0;
  933. __arm_spe_pmu_stop_one(spe_pmu);
  934. return 0;
  935. }
  936. static int arm_spe_pmu_dev_init(struct arm_spe_pmu *spe_pmu)
  937. {
  938. int ret;
  939. cpumask_t *mask = &spe_pmu->supported_cpus;
  940. /* Make sure we probe the hardware on a relevant CPU */
  941. ret = smp_call_function_any(mask, __arm_spe_pmu_dev_probe, spe_pmu, 1);
  942. if (ret || !(spe_pmu->features & SPE_PMU_FEAT_DEV_PROBED))
  943. return -ENXIO;
  944. /* Request our PPIs (note that the IRQ is still disabled) */
  945. ret = request_percpu_irq(spe_pmu->irq, arm_spe_pmu_irq_handler, DRVNAME,
  946. spe_pmu->handle);
  947. if (ret)
  948. return ret;
  949. /*
  950. * Register our hotplug notifier now so we don't miss any events.
  951. * This will enable the IRQ for any supported CPUs that are already
  952. * up.
  953. */
  954. ret = cpuhp_state_add_instance(arm_spe_pmu_online,
  955. &spe_pmu->hotplug_node);
  956. if (ret)
  957. free_percpu_irq(spe_pmu->irq, spe_pmu->handle);
  958. return ret;
  959. }
  960. static void arm_spe_pmu_dev_teardown(struct arm_spe_pmu *spe_pmu)
  961. {
  962. cpuhp_state_remove_instance(arm_spe_pmu_online, &spe_pmu->hotplug_node);
  963. free_percpu_irq(spe_pmu->irq, spe_pmu->handle);
  964. }
  965. /* Driver and device probing */
  966. static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu)
  967. {
  968. struct platform_device *pdev = spe_pmu->pdev;
  969. int irq = platform_get_irq(pdev, 0);
  970. if (irq < 0)
  971. return -ENXIO;
  972. if (!irq_is_percpu(irq)) {
  973. dev_err(&pdev->dev, "expected PPI but got SPI (%d)\n", irq);
  974. return -EINVAL;
  975. }
  976. if (irq_get_percpu_devid_partition(irq, &spe_pmu->supported_cpus)) {
  977. dev_err(&pdev->dev, "failed to get PPI partition (%d)\n", irq);
  978. return -EINVAL;
  979. }
  980. spe_pmu->irq = irq;
  981. return 0;
  982. }
  983. static const struct of_device_id arm_spe_pmu_of_match[] = {
  984. { .compatible = "arm,statistical-profiling-extension-v1", .data = (void *)1 },
  985. { /* Sentinel */ },
  986. };
  987. MODULE_DEVICE_TABLE(of, arm_spe_pmu_of_match);
  988. static const struct platform_device_id arm_spe_match[] = {
  989. { ARMV8_SPE_PDEV_NAME, 0},
  990. { }
  991. };
  992. MODULE_DEVICE_TABLE(platform, arm_spe_match);
  993. static int arm_spe_pmu_device_probe(struct platform_device *pdev)
  994. {
  995. int ret;
  996. struct arm_spe_pmu *spe_pmu;
  997. struct device *dev = &pdev->dev;
  998. /*
  999. * If kernelspace is unmapped when running at EL0, then the SPE
  1000. * buffer will fault and prematurely terminate the AUX session.
  1001. */
  1002. if (arm64_kernel_unmapped_at_el0()) {
  1003. dev_warn_once(dev, "profiling buffer inaccessible. Try passing \"kpti=off\" on the kernel command line\n");
  1004. return -EPERM;
  1005. }
  1006. spe_pmu = devm_kzalloc(dev, sizeof(*spe_pmu), GFP_KERNEL);
  1007. if (!spe_pmu)
  1008. return -ENOMEM;
  1009. spe_pmu->handle = alloc_percpu(typeof(*spe_pmu->handle));
  1010. if (!spe_pmu->handle)
  1011. return -ENOMEM;
  1012. spe_pmu->pdev = pdev;
  1013. platform_set_drvdata(pdev, spe_pmu);
  1014. ret = arm_spe_pmu_irq_probe(spe_pmu);
  1015. if (ret)
  1016. goto out_free_handle;
  1017. ret = arm_spe_pmu_dev_init(spe_pmu);
  1018. if (ret)
  1019. goto out_free_handle;
  1020. ret = arm_spe_pmu_perf_init(spe_pmu);
  1021. if (ret)
  1022. goto out_teardown_dev;
  1023. return 0;
  1024. out_teardown_dev:
  1025. arm_spe_pmu_dev_teardown(spe_pmu);
  1026. out_free_handle:
  1027. free_percpu(spe_pmu->handle);
  1028. return ret;
  1029. }
  1030. static int arm_spe_pmu_device_remove(struct platform_device *pdev)
  1031. {
  1032. struct arm_spe_pmu *spe_pmu = platform_get_drvdata(pdev);
  1033. arm_spe_pmu_perf_destroy(spe_pmu);
  1034. arm_spe_pmu_dev_teardown(spe_pmu);
  1035. free_percpu(spe_pmu->handle);
  1036. return 0;
  1037. }
  1038. static struct platform_driver arm_spe_pmu_driver = {
  1039. .id_table = arm_spe_match,
  1040. .driver = {
  1041. .name = DRVNAME,
  1042. .of_match_table = of_match_ptr(arm_spe_pmu_of_match),
  1043. .suppress_bind_attrs = true,
  1044. },
  1045. .probe = arm_spe_pmu_device_probe,
  1046. .remove = arm_spe_pmu_device_remove,
  1047. };
  1048. static int __init arm_spe_pmu_init(void)
  1049. {
  1050. int ret;
  1051. ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
  1052. arm_spe_pmu_cpu_startup,
  1053. arm_spe_pmu_cpu_teardown);
  1054. if (ret < 0)
  1055. return ret;
  1056. arm_spe_pmu_online = ret;
  1057. ret = platform_driver_register(&arm_spe_pmu_driver);
  1058. if (ret)
  1059. cpuhp_remove_multi_state(arm_spe_pmu_online);
  1060. return ret;
  1061. }
  1062. static void __exit arm_spe_pmu_exit(void)
  1063. {
  1064. platform_driver_unregister(&arm_spe_pmu_driver);
  1065. cpuhp_remove_multi_state(arm_spe_pmu_online);
  1066. }
  1067. module_init(arm_spe_pmu_init);
  1068. module_exit(arm_spe_pmu_exit);
  1069. MODULE_DESCRIPTION("Perf driver for the ARMv8.2 Statistical Profiling Extension");
  1070. MODULE_AUTHOR("Will Deacon <[email protected]>");
  1071. MODULE_LICENSE("GPL v2");