arm_dsu_pmu.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ARM DynamIQ Shared Unit (DSU) PMU driver
  4. *
  5. * Copyright (C) ARM Limited, 2017.
  6. *
  7. * Based on ARM CCI-PMU, ARMv8 PMU-v3 drivers.
  8. */
  9. #define PMUNAME "arm_dsu"
  10. #define DRVNAME PMUNAME "_pmu"
  11. #define pr_fmt(fmt) DRVNAME ": " fmt
  12. #include <linux/acpi.h>
  13. #include <linux/bitmap.h>
  14. #include <linux/bitops.h>
  15. #include <linux/bug.h>
  16. #include <linux/cpumask.h>
  17. #include <linux/device.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/of_device.h>
  22. #include <linux/perf_event.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/smp.h>
  26. #include <linux/sysfs.h>
  27. #include <linux/types.h>
  28. #include <asm/arm_dsu_pmu.h>
  29. #include <asm/local64.h>
  30. /* PMU event codes */
  31. #define DSU_PMU_EVT_CYCLES 0x11
  32. #define DSU_PMU_EVT_CHAIN 0x1e
  33. #define DSU_PMU_MAX_COMMON_EVENTS 0x40
  34. #define DSU_PMU_MAX_HW_CNTRS 32
  35. #define DSU_PMU_HW_COUNTER_MASK (DSU_PMU_MAX_HW_CNTRS - 1)
  36. #define CLUSTERPMCR_E BIT(0)
  37. #define CLUSTERPMCR_P BIT(1)
  38. #define CLUSTERPMCR_C BIT(2)
  39. #define CLUSTERPMCR_N_SHIFT 11
  40. #define CLUSTERPMCR_N_MASK 0x1f
  41. #define CLUSTERPMCR_IDCODE_SHIFT 16
  42. #define CLUSTERPMCR_IDCODE_MASK 0xff
  43. #define CLUSTERPMCR_IMP_SHIFT 24
  44. #define CLUSTERPMCR_IMP_MASK 0xff
  45. #define CLUSTERPMCR_RES_MASK 0x7e8
  46. #define CLUSTERPMCR_RES_VAL 0x40
  47. #define DSU_ACTIVE_CPU_MASK 0x0
  48. #define DSU_ASSOCIATED_CPU_MASK 0x1
  49. /*
  50. * We use the index of the counters as they appear in the counter
  51. * bit maps in the PMU registers (e.g CLUSTERPMSELR).
  52. * i.e,
  53. * counter 0 - Bit 0
  54. * counter 1 - Bit 1
  55. * ...
  56. * Cycle counter - Bit 31
  57. */
  58. #define DSU_PMU_IDX_CYCLE_COUNTER 31
  59. /* All event counters are 32bit, with a 64bit Cycle counter */
  60. #define DSU_PMU_COUNTER_WIDTH(idx) \
  61. (((idx) == DSU_PMU_IDX_CYCLE_COUNTER) ? 64 : 32)
  62. #define DSU_PMU_COUNTER_MASK(idx) \
  63. GENMASK_ULL((DSU_PMU_COUNTER_WIDTH((idx)) - 1), 0)
  64. #define DSU_EXT_ATTR(_name, _func, _config) \
  65. (&((struct dev_ext_attribute[]) { \
  66. { \
  67. .attr = __ATTR(_name, 0444, _func, NULL), \
  68. .var = (void *)_config \
  69. } \
  70. })[0].attr.attr)
  71. #define DSU_EVENT_ATTR(_name, _config) \
  72. DSU_EXT_ATTR(_name, dsu_pmu_sysfs_event_show, (unsigned long)_config)
  73. #define DSU_FORMAT_ATTR(_name, _config) \
  74. DSU_EXT_ATTR(_name, dsu_pmu_sysfs_format_show, (char *)_config)
  75. #define DSU_CPUMASK_ATTR(_name, _config) \
  76. DSU_EXT_ATTR(_name, dsu_pmu_cpumask_show, (unsigned long)_config)
  77. struct dsu_hw_events {
  78. DECLARE_BITMAP(used_mask, DSU_PMU_MAX_HW_CNTRS);
  79. struct perf_event *events[DSU_PMU_MAX_HW_CNTRS];
  80. };
  81. /*
  82. * struct dsu_pmu - DSU PMU descriptor
  83. *
  84. * @pmu_lock : Protects accesses to DSU PMU register from normal vs
  85. * interrupt handler contexts.
  86. * @hw_events : Holds the event counter state.
  87. * @associated_cpus : CPUs attached to the DSU.
  88. * @active_cpu : CPU to which the PMU is bound for accesses.
  89. * @cpuhp_node : Node for CPU hotplug notifier link.
  90. * @num_counters : Number of event counters implemented by the PMU,
  91. * excluding the cycle counter.
  92. * @irq : Interrupt line for counter overflow.
  93. * @cpmceid_bitmap : Bitmap for the availability of architected common
  94. * events (event_code < 0x40).
  95. */
  96. struct dsu_pmu {
  97. struct pmu pmu;
  98. struct device *dev;
  99. raw_spinlock_t pmu_lock;
  100. struct dsu_hw_events hw_events;
  101. cpumask_t associated_cpus;
  102. cpumask_t active_cpu;
  103. struct hlist_node cpuhp_node;
  104. s8 num_counters;
  105. int irq;
  106. DECLARE_BITMAP(cpmceid_bitmap, DSU_PMU_MAX_COMMON_EVENTS);
  107. };
  108. static unsigned long dsu_pmu_cpuhp_state;
  109. static inline struct dsu_pmu *to_dsu_pmu(struct pmu *pmu)
  110. {
  111. return container_of(pmu, struct dsu_pmu, pmu);
  112. }
  113. static ssize_t dsu_pmu_sysfs_event_show(struct device *dev,
  114. struct device_attribute *attr,
  115. char *buf)
  116. {
  117. struct dev_ext_attribute *eattr = container_of(attr,
  118. struct dev_ext_attribute, attr);
  119. return sysfs_emit(buf, "event=0x%lx\n", (unsigned long)eattr->var);
  120. }
  121. static ssize_t dsu_pmu_sysfs_format_show(struct device *dev,
  122. struct device_attribute *attr,
  123. char *buf)
  124. {
  125. struct dev_ext_attribute *eattr = container_of(attr,
  126. struct dev_ext_attribute, attr);
  127. return sysfs_emit(buf, "%s\n", (char *)eattr->var);
  128. }
  129. static ssize_t dsu_pmu_cpumask_show(struct device *dev,
  130. struct device_attribute *attr,
  131. char *buf)
  132. {
  133. struct pmu *pmu = dev_get_drvdata(dev);
  134. struct dsu_pmu *dsu_pmu = to_dsu_pmu(pmu);
  135. struct dev_ext_attribute *eattr = container_of(attr,
  136. struct dev_ext_attribute, attr);
  137. unsigned long mask_id = (unsigned long)eattr->var;
  138. const cpumask_t *cpumask;
  139. switch (mask_id) {
  140. case DSU_ACTIVE_CPU_MASK:
  141. cpumask = &dsu_pmu->active_cpu;
  142. break;
  143. case DSU_ASSOCIATED_CPU_MASK:
  144. cpumask = &dsu_pmu->associated_cpus;
  145. break;
  146. default:
  147. return 0;
  148. }
  149. return cpumap_print_to_pagebuf(true, buf, cpumask);
  150. }
  151. static struct attribute *dsu_pmu_format_attrs[] = {
  152. DSU_FORMAT_ATTR(event, "config:0-31"),
  153. NULL,
  154. };
  155. static const struct attribute_group dsu_pmu_format_attr_group = {
  156. .name = "format",
  157. .attrs = dsu_pmu_format_attrs,
  158. };
  159. static struct attribute *dsu_pmu_event_attrs[] = {
  160. DSU_EVENT_ATTR(cycles, 0x11),
  161. DSU_EVENT_ATTR(bus_access, 0x19),
  162. DSU_EVENT_ATTR(memory_error, 0x1a),
  163. DSU_EVENT_ATTR(bus_cycles, 0x1d),
  164. DSU_EVENT_ATTR(l3d_cache_allocate, 0x29),
  165. DSU_EVENT_ATTR(l3d_cache_refill, 0x2a),
  166. DSU_EVENT_ATTR(l3d_cache, 0x2b),
  167. DSU_EVENT_ATTR(l3d_cache_wb, 0x2c),
  168. NULL,
  169. };
  170. static umode_t
  171. dsu_pmu_event_attr_is_visible(struct kobject *kobj, struct attribute *attr,
  172. int unused)
  173. {
  174. struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj));
  175. struct dsu_pmu *dsu_pmu = to_dsu_pmu(pmu);
  176. struct dev_ext_attribute *eattr = container_of(attr,
  177. struct dev_ext_attribute, attr.attr);
  178. unsigned long evt = (unsigned long)eattr->var;
  179. return test_bit(evt, dsu_pmu->cpmceid_bitmap) ? attr->mode : 0;
  180. }
  181. static const struct attribute_group dsu_pmu_events_attr_group = {
  182. .name = "events",
  183. .attrs = dsu_pmu_event_attrs,
  184. .is_visible = dsu_pmu_event_attr_is_visible,
  185. };
  186. static struct attribute *dsu_pmu_cpumask_attrs[] = {
  187. DSU_CPUMASK_ATTR(cpumask, DSU_ACTIVE_CPU_MASK),
  188. DSU_CPUMASK_ATTR(associated_cpus, DSU_ASSOCIATED_CPU_MASK),
  189. NULL,
  190. };
  191. static const struct attribute_group dsu_pmu_cpumask_attr_group = {
  192. .attrs = dsu_pmu_cpumask_attrs,
  193. };
  194. static const struct attribute_group *dsu_pmu_attr_groups[] = {
  195. &dsu_pmu_cpumask_attr_group,
  196. &dsu_pmu_events_attr_group,
  197. &dsu_pmu_format_attr_group,
  198. NULL,
  199. };
  200. static int dsu_pmu_get_online_cpu_any_but(struct dsu_pmu *dsu_pmu, int cpu)
  201. {
  202. struct cpumask online_supported;
  203. cpumask_and(&online_supported,
  204. &dsu_pmu->associated_cpus, cpu_online_mask);
  205. return cpumask_any_but(&online_supported, cpu);
  206. }
  207. static inline bool dsu_pmu_counter_valid(struct dsu_pmu *dsu_pmu, u32 idx)
  208. {
  209. return (idx < dsu_pmu->num_counters) ||
  210. (idx == DSU_PMU_IDX_CYCLE_COUNTER);
  211. }
  212. static inline u64 dsu_pmu_read_counter(struct perf_event *event)
  213. {
  214. u64 val;
  215. unsigned long flags;
  216. struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
  217. int idx = event->hw.idx;
  218. if (WARN_ON(!cpumask_test_cpu(smp_processor_id(),
  219. &dsu_pmu->associated_cpus)))
  220. return 0;
  221. if (!dsu_pmu_counter_valid(dsu_pmu, idx)) {
  222. dev_err(event->pmu->dev,
  223. "Trying reading invalid counter %d\n", idx);
  224. return 0;
  225. }
  226. raw_spin_lock_irqsave(&dsu_pmu->pmu_lock, flags);
  227. if (idx == DSU_PMU_IDX_CYCLE_COUNTER)
  228. val = __dsu_pmu_read_pmccntr();
  229. else
  230. val = __dsu_pmu_read_counter(idx);
  231. raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags);
  232. return val;
  233. }
  234. static void dsu_pmu_write_counter(struct perf_event *event, u64 val)
  235. {
  236. unsigned long flags;
  237. struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
  238. int idx = event->hw.idx;
  239. if (WARN_ON(!cpumask_test_cpu(smp_processor_id(),
  240. &dsu_pmu->associated_cpus)))
  241. return;
  242. if (!dsu_pmu_counter_valid(dsu_pmu, idx)) {
  243. dev_err(event->pmu->dev,
  244. "writing to invalid counter %d\n", idx);
  245. return;
  246. }
  247. raw_spin_lock_irqsave(&dsu_pmu->pmu_lock, flags);
  248. if (idx == DSU_PMU_IDX_CYCLE_COUNTER)
  249. __dsu_pmu_write_pmccntr(val);
  250. else
  251. __dsu_pmu_write_counter(idx, val);
  252. raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags);
  253. }
  254. static int dsu_pmu_get_event_idx(struct dsu_hw_events *hw_events,
  255. struct perf_event *event)
  256. {
  257. int idx;
  258. unsigned long evtype = event->attr.config;
  259. struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
  260. unsigned long *used_mask = hw_events->used_mask;
  261. if (evtype == DSU_PMU_EVT_CYCLES) {
  262. if (test_and_set_bit(DSU_PMU_IDX_CYCLE_COUNTER, used_mask))
  263. return -EAGAIN;
  264. return DSU_PMU_IDX_CYCLE_COUNTER;
  265. }
  266. idx = find_first_zero_bit(used_mask, dsu_pmu->num_counters);
  267. if (idx >= dsu_pmu->num_counters)
  268. return -EAGAIN;
  269. set_bit(idx, hw_events->used_mask);
  270. return idx;
  271. }
  272. static void dsu_pmu_enable_counter(struct dsu_pmu *dsu_pmu, int idx)
  273. {
  274. __dsu_pmu_counter_interrupt_enable(idx);
  275. __dsu_pmu_enable_counter(idx);
  276. }
  277. static void dsu_pmu_disable_counter(struct dsu_pmu *dsu_pmu, int idx)
  278. {
  279. __dsu_pmu_disable_counter(idx);
  280. __dsu_pmu_counter_interrupt_disable(idx);
  281. }
  282. static inline void dsu_pmu_set_event(struct dsu_pmu *dsu_pmu,
  283. struct perf_event *event)
  284. {
  285. int idx = event->hw.idx;
  286. unsigned long flags;
  287. if (!dsu_pmu_counter_valid(dsu_pmu, idx)) {
  288. dev_err(event->pmu->dev,
  289. "Trying to set invalid counter %d\n", idx);
  290. return;
  291. }
  292. raw_spin_lock_irqsave(&dsu_pmu->pmu_lock, flags);
  293. __dsu_pmu_set_event(idx, event->hw.config_base);
  294. raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags);
  295. }
  296. static void dsu_pmu_event_update(struct perf_event *event)
  297. {
  298. struct hw_perf_event *hwc = &event->hw;
  299. u64 delta, prev_count, new_count;
  300. do {
  301. /* We may also be called from the irq handler */
  302. prev_count = local64_read(&hwc->prev_count);
  303. new_count = dsu_pmu_read_counter(event);
  304. } while (local64_cmpxchg(&hwc->prev_count, prev_count, new_count) !=
  305. prev_count);
  306. delta = (new_count - prev_count) & DSU_PMU_COUNTER_MASK(hwc->idx);
  307. local64_add(delta, &event->count);
  308. }
  309. static void dsu_pmu_read(struct perf_event *event)
  310. {
  311. dsu_pmu_event_update(event);
  312. }
  313. static inline u32 dsu_pmu_get_reset_overflow(void)
  314. {
  315. return __dsu_pmu_get_reset_overflow();
  316. }
  317. /**
  318. * dsu_pmu_set_event_period: Set the period for the counter.
  319. *
  320. * All DSU PMU event counters, except the cycle counter are 32bit
  321. * counters. To handle cases of extreme interrupt latency, we program
  322. * the counter with half of the max count for the counters.
  323. */
  324. static void dsu_pmu_set_event_period(struct perf_event *event)
  325. {
  326. int idx = event->hw.idx;
  327. u64 val = DSU_PMU_COUNTER_MASK(idx) >> 1;
  328. local64_set(&event->hw.prev_count, val);
  329. dsu_pmu_write_counter(event, val);
  330. }
  331. static irqreturn_t dsu_pmu_handle_irq(int irq_num, void *dev)
  332. {
  333. int i;
  334. bool handled = false;
  335. struct dsu_pmu *dsu_pmu = dev;
  336. struct dsu_hw_events *hw_events = &dsu_pmu->hw_events;
  337. unsigned long overflow;
  338. overflow = dsu_pmu_get_reset_overflow();
  339. if (!overflow)
  340. return IRQ_NONE;
  341. for_each_set_bit(i, &overflow, DSU_PMU_MAX_HW_CNTRS) {
  342. struct perf_event *event = hw_events->events[i];
  343. if (!event)
  344. continue;
  345. dsu_pmu_event_update(event);
  346. dsu_pmu_set_event_period(event);
  347. handled = true;
  348. }
  349. return IRQ_RETVAL(handled);
  350. }
  351. static void dsu_pmu_start(struct perf_event *event, int pmu_flags)
  352. {
  353. struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
  354. /* We always reprogram the counter */
  355. if (pmu_flags & PERF_EF_RELOAD)
  356. WARN_ON(!(event->hw.state & PERF_HES_UPTODATE));
  357. dsu_pmu_set_event_period(event);
  358. if (event->hw.idx != DSU_PMU_IDX_CYCLE_COUNTER)
  359. dsu_pmu_set_event(dsu_pmu, event);
  360. event->hw.state = 0;
  361. dsu_pmu_enable_counter(dsu_pmu, event->hw.idx);
  362. }
  363. static void dsu_pmu_stop(struct perf_event *event, int pmu_flags)
  364. {
  365. struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
  366. if (event->hw.state & PERF_HES_STOPPED)
  367. return;
  368. dsu_pmu_disable_counter(dsu_pmu, event->hw.idx);
  369. dsu_pmu_event_update(event);
  370. event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
  371. }
  372. static int dsu_pmu_add(struct perf_event *event, int flags)
  373. {
  374. struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
  375. struct dsu_hw_events *hw_events = &dsu_pmu->hw_events;
  376. struct hw_perf_event *hwc = &event->hw;
  377. int idx;
  378. if (WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(),
  379. &dsu_pmu->associated_cpus)))
  380. return -ENOENT;
  381. idx = dsu_pmu_get_event_idx(hw_events, event);
  382. if (idx < 0)
  383. return idx;
  384. hwc->idx = idx;
  385. hw_events->events[idx] = event;
  386. hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
  387. if (flags & PERF_EF_START)
  388. dsu_pmu_start(event, PERF_EF_RELOAD);
  389. perf_event_update_userpage(event);
  390. return 0;
  391. }
  392. static void dsu_pmu_del(struct perf_event *event, int flags)
  393. {
  394. struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
  395. struct dsu_hw_events *hw_events = &dsu_pmu->hw_events;
  396. struct hw_perf_event *hwc = &event->hw;
  397. int idx = hwc->idx;
  398. dsu_pmu_stop(event, PERF_EF_UPDATE);
  399. hw_events->events[idx] = NULL;
  400. clear_bit(idx, hw_events->used_mask);
  401. perf_event_update_userpage(event);
  402. }
  403. static void dsu_pmu_enable(struct pmu *pmu)
  404. {
  405. u32 pmcr;
  406. unsigned long flags;
  407. struct dsu_pmu *dsu_pmu = to_dsu_pmu(pmu);
  408. /* If no counters are added, skip enabling the PMU */
  409. if (bitmap_empty(dsu_pmu->hw_events.used_mask, DSU_PMU_MAX_HW_CNTRS))
  410. return;
  411. raw_spin_lock_irqsave(&dsu_pmu->pmu_lock, flags);
  412. pmcr = __dsu_pmu_read_pmcr();
  413. pmcr |= CLUSTERPMCR_E;
  414. __dsu_pmu_write_pmcr(pmcr);
  415. raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags);
  416. }
  417. static void dsu_pmu_disable(struct pmu *pmu)
  418. {
  419. u32 pmcr;
  420. unsigned long flags;
  421. struct dsu_pmu *dsu_pmu = to_dsu_pmu(pmu);
  422. raw_spin_lock_irqsave(&dsu_pmu->pmu_lock, flags);
  423. pmcr = __dsu_pmu_read_pmcr();
  424. pmcr &= ~CLUSTERPMCR_E;
  425. __dsu_pmu_write_pmcr(pmcr);
  426. raw_spin_unlock_irqrestore(&dsu_pmu->pmu_lock, flags);
  427. }
  428. static bool dsu_pmu_validate_event(struct pmu *pmu,
  429. struct dsu_hw_events *hw_events,
  430. struct perf_event *event)
  431. {
  432. if (is_software_event(event))
  433. return true;
  434. /* Reject groups spanning multiple HW PMUs. */
  435. if (event->pmu != pmu)
  436. return false;
  437. return dsu_pmu_get_event_idx(hw_events, event) >= 0;
  438. }
  439. /*
  440. * Make sure the group of events can be scheduled at once
  441. * on the PMU.
  442. */
  443. static bool dsu_pmu_validate_group(struct perf_event *event)
  444. {
  445. struct perf_event *sibling, *leader = event->group_leader;
  446. struct dsu_hw_events fake_hw;
  447. if (event->group_leader == event)
  448. return true;
  449. memset(fake_hw.used_mask, 0, sizeof(fake_hw.used_mask));
  450. if (!dsu_pmu_validate_event(event->pmu, &fake_hw, leader))
  451. return false;
  452. for_each_sibling_event(sibling, leader) {
  453. if (!dsu_pmu_validate_event(event->pmu, &fake_hw, sibling))
  454. return false;
  455. }
  456. return dsu_pmu_validate_event(event->pmu, &fake_hw, event);
  457. }
  458. static int dsu_pmu_event_init(struct perf_event *event)
  459. {
  460. struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
  461. if (event->attr.type != event->pmu->type)
  462. return -ENOENT;
  463. /* We don't support sampling */
  464. if (is_sampling_event(event)) {
  465. dev_dbg(dsu_pmu->pmu.dev, "Can't support sampling events\n");
  466. return -EOPNOTSUPP;
  467. }
  468. /* We cannot support task bound events */
  469. if (event->cpu < 0 || event->attach_state & PERF_ATTACH_TASK) {
  470. dev_dbg(dsu_pmu->pmu.dev, "Can't support per-task counters\n");
  471. return -EINVAL;
  472. }
  473. if (has_branch_stack(event)) {
  474. dev_dbg(dsu_pmu->pmu.dev, "Can't support filtering\n");
  475. return -EINVAL;
  476. }
  477. if (!cpumask_test_cpu(event->cpu, &dsu_pmu->associated_cpus)) {
  478. dev_dbg(dsu_pmu->pmu.dev,
  479. "Requested cpu is not associated with the DSU\n");
  480. return -EINVAL;
  481. }
  482. /*
  483. * Choose the current active CPU to read the events. We don't want
  484. * to migrate the event contexts, irq handling etc to the requested
  485. * CPU. As long as the requested CPU is within the same DSU, we
  486. * are fine.
  487. */
  488. event->cpu = cpumask_first(&dsu_pmu->active_cpu);
  489. if (event->cpu >= nr_cpu_ids)
  490. return -EINVAL;
  491. if (!dsu_pmu_validate_group(event))
  492. return -EINVAL;
  493. event->hw.config_base = event->attr.config;
  494. return 0;
  495. }
  496. static struct dsu_pmu *dsu_pmu_alloc(struct platform_device *pdev)
  497. {
  498. struct dsu_pmu *dsu_pmu;
  499. dsu_pmu = devm_kzalloc(&pdev->dev, sizeof(*dsu_pmu), GFP_KERNEL);
  500. if (!dsu_pmu)
  501. return ERR_PTR(-ENOMEM);
  502. raw_spin_lock_init(&dsu_pmu->pmu_lock);
  503. /*
  504. * Initialise the number of counters to -1, until we probe
  505. * the real number on a connected CPU.
  506. */
  507. dsu_pmu->num_counters = -1;
  508. return dsu_pmu;
  509. }
  510. /**
  511. * dsu_pmu_dt_get_cpus: Get the list of CPUs in the cluster
  512. * from device tree.
  513. */
  514. static int dsu_pmu_dt_get_cpus(struct device *dev, cpumask_t *mask)
  515. {
  516. int i = 0, n, cpu;
  517. struct device_node *cpu_node;
  518. n = of_count_phandle_with_args(dev->of_node, "cpus", NULL);
  519. if (n <= 0)
  520. return -ENODEV;
  521. for (; i < n; i++) {
  522. cpu_node = of_parse_phandle(dev->of_node, "cpus", i);
  523. if (!cpu_node)
  524. break;
  525. cpu = of_cpu_node_to_id(cpu_node);
  526. of_node_put(cpu_node);
  527. /*
  528. * We have to ignore the failures here and continue scanning
  529. * the list to handle cases where the nr_cpus could be capped
  530. * in the running kernel.
  531. */
  532. if (cpu < 0)
  533. continue;
  534. cpumask_set_cpu(cpu, mask);
  535. }
  536. return 0;
  537. }
  538. /**
  539. * dsu_pmu_acpi_get_cpus: Get the list of CPUs in the cluster
  540. * from ACPI.
  541. */
  542. static int dsu_pmu_acpi_get_cpus(struct device *dev, cpumask_t *mask)
  543. {
  544. #ifdef CONFIG_ACPI
  545. struct acpi_device *parent_adev = acpi_dev_parent(ACPI_COMPANION(dev));
  546. int cpu;
  547. /*
  548. * A dsu pmu node is inside a cluster parent node along with cpu nodes.
  549. * We need to find out all cpus that have the same parent with this pmu.
  550. */
  551. for_each_possible_cpu(cpu) {
  552. struct acpi_device *acpi_dev;
  553. struct device *cpu_dev = get_cpu_device(cpu);
  554. if (!cpu_dev)
  555. continue;
  556. acpi_dev = ACPI_COMPANION(cpu_dev);
  557. if (acpi_dev && acpi_dev_parent(acpi_dev) == parent_adev)
  558. cpumask_set_cpu(cpu, mask);
  559. }
  560. #endif
  561. return 0;
  562. }
  563. /*
  564. * dsu_pmu_probe_pmu: Probe the PMU details on a CPU in the cluster.
  565. */
  566. static void dsu_pmu_probe_pmu(struct dsu_pmu *dsu_pmu)
  567. {
  568. u64 num_counters;
  569. u32 cpmceid[2];
  570. num_counters = (__dsu_pmu_read_pmcr() >> CLUSTERPMCR_N_SHIFT) &
  571. CLUSTERPMCR_N_MASK;
  572. /* We can only support up to 31 independent counters */
  573. if (WARN_ON(num_counters > 31))
  574. num_counters = 31;
  575. dsu_pmu->num_counters = num_counters;
  576. if (!dsu_pmu->num_counters)
  577. return;
  578. cpmceid[0] = __dsu_pmu_read_pmceid(0);
  579. cpmceid[1] = __dsu_pmu_read_pmceid(1);
  580. bitmap_from_arr32(dsu_pmu->cpmceid_bitmap, cpmceid,
  581. DSU_PMU_MAX_COMMON_EVENTS);
  582. }
  583. static void dsu_pmu_set_active_cpu(int cpu, struct dsu_pmu *dsu_pmu)
  584. {
  585. cpumask_set_cpu(cpu, &dsu_pmu->active_cpu);
  586. if (irq_set_affinity(dsu_pmu->irq, &dsu_pmu->active_cpu))
  587. pr_warn("Failed to set irq affinity to %d\n", cpu);
  588. }
  589. /*
  590. * dsu_pmu_init_pmu: Initialise the DSU PMU configurations if
  591. * we haven't done it already.
  592. */
  593. static void dsu_pmu_init_pmu(struct dsu_pmu *dsu_pmu)
  594. {
  595. if (dsu_pmu->num_counters == -1)
  596. dsu_pmu_probe_pmu(dsu_pmu);
  597. /* Reset the interrupt overflow mask */
  598. dsu_pmu_get_reset_overflow();
  599. }
  600. static int dsu_pmu_device_probe(struct platform_device *pdev)
  601. {
  602. int irq, rc;
  603. struct dsu_pmu *dsu_pmu;
  604. struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev);
  605. char *name;
  606. static atomic_t pmu_idx = ATOMIC_INIT(-1);
  607. dsu_pmu = dsu_pmu_alloc(pdev);
  608. if (IS_ERR(dsu_pmu))
  609. return PTR_ERR(dsu_pmu);
  610. if (is_of_node(fwnode))
  611. rc = dsu_pmu_dt_get_cpus(&pdev->dev, &dsu_pmu->associated_cpus);
  612. else if (is_acpi_device_node(fwnode))
  613. rc = dsu_pmu_acpi_get_cpus(&pdev->dev, &dsu_pmu->associated_cpus);
  614. else
  615. return -ENOENT;
  616. if (rc) {
  617. dev_warn(&pdev->dev, "Failed to parse the CPUs\n");
  618. return rc;
  619. }
  620. irq = platform_get_irq(pdev, 0);
  621. if (irq < 0)
  622. return -EINVAL;
  623. name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_%d",
  624. PMUNAME, atomic_inc_return(&pmu_idx));
  625. if (!name)
  626. return -ENOMEM;
  627. rc = devm_request_irq(&pdev->dev, irq, dsu_pmu_handle_irq,
  628. IRQF_NOBALANCING, name, dsu_pmu);
  629. if (rc) {
  630. dev_warn(&pdev->dev, "Failed to request IRQ %d\n", irq);
  631. return rc;
  632. }
  633. dsu_pmu->irq = irq;
  634. platform_set_drvdata(pdev, dsu_pmu);
  635. rc = cpuhp_state_add_instance(dsu_pmu_cpuhp_state,
  636. &dsu_pmu->cpuhp_node);
  637. if (rc)
  638. return rc;
  639. dsu_pmu->pmu = (struct pmu) {
  640. .task_ctx_nr = perf_invalid_context,
  641. .module = THIS_MODULE,
  642. .pmu_enable = dsu_pmu_enable,
  643. .pmu_disable = dsu_pmu_disable,
  644. .event_init = dsu_pmu_event_init,
  645. .add = dsu_pmu_add,
  646. .del = dsu_pmu_del,
  647. .start = dsu_pmu_start,
  648. .stop = dsu_pmu_stop,
  649. .read = dsu_pmu_read,
  650. .attr_groups = dsu_pmu_attr_groups,
  651. .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
  652. };
  653. rc = perf_pmu_register(&dsu_pmu->pmu, name, -1);
  654. if (rc) {
  655. cpuhp_state_remove_instance(dsu_pmu_cpuhp_state,
  656. &dsu_pmu->cpuhp_node);
  657. }
  658. return rc;
  659. }
  660. static int dsu_pmu_device_remove(struct platform_device *pdev)
  661. {
  662. struct dsu_pmu *dsu_pmu = platform_get_drvdata(pdev);
  663. perf_pmu_unregister(&dsu_pmu->pmu);
  664. cpuhp_state_remove_instance(dsu_pmu_cpuhp_state, &dsu_pmu->cpuhp_node);
  665. return 0;
  666. }
  667. static const struct of_device_id dsu_pmu_of_match[] = {
  668. { .compatible = "arm,dsu-pmu", },
  669. {},
  670. };
  671. MODULE_DEVICE_TABLE(of, dsu_pmu_of_match);
  672. #ifdef CONFIG_ACPI
  673. static const struct acpi_device_id dsu_pmu_acpi_match[] = {
  674. { "ARMHD500", 0},
  675. {},
  676. };
  677. MODULE_DEVICE_TABLE(acpi, dsu_pmu_acpi_match);
  678. #endif
  679. static struct platform_driver dsu_pmu_driver = {
  680. .driver = {
  681. .name = DRVNAME,
  682. .of_match_table = of_match_ptr(dsu_pmu_of_match),
  683. .acpi_match_table = ACPI_PTR(dsu_pmu_acpi_match),
  684. .suppress_bind_attrs = true,
  685. },
  686. .probe = dsu_pmu_device_probe,
  687. .remove = dsu_pmu_device_remove,
  688. };
  689. static int dsu_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
  690. {
  691. struct dsu_pmu *dsu_pmu = hlist_entry_safe(node, struct dsu_pmu,
  692. cpuhp_node);
  693. if (!cpumask_test_cpu(cpu, &dsu_pmu->associated_cpus))
  694. return 0;
  695. /* If the PMU is already managed, there is nothing to do */
  696. if (!cpumask_empty(&dsu_pmu->active_cpu))
  697. return 0;
  698. dsu_pmu_init_pmu(dsu_pmu);
  699. dsu_pmu_set_active_cpu(cpu, dsu_pmu);
  700. return 0;
  701. }
  702. static int dsu_pmu_cpu_teardown(unsigned int cpu, struct hlist_node *node)
  703. {
  704. int dst;
  705. struct dsu_pmu *dsu_pmu = hlist_entry_safe(node, struct dsu_pmu,
  706. cpuhp_node);
  707. if (!cpumask_test_and_clear_cpu(cpu, &dsu_pmu->active_cpu))
  708. return 0;
  709. dst = dsu_pmu_get_online_cpu_any_but(dsu_pmu, cpu);
  710. /* If there are no active CPUs in the DSU, leave IRQ disabled */
  711. if (dst >= nr_cpu_ids)
  712. return 0;
  713. perf_pmu_migrate_context(&dsu_pmu->pmu, cpu, dst);
  714. dsu_pmu_set_active_cpu(dst, dsu_pmu);
  715. return 0;
  716. }
  717. static int __init dsu_pmu_init(void)
  718. {
  719. int ret;
  720. ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
  721. DRVNAME,
  722. dsu_pmu_cpu_online,
  723. dsu_pmu_cpu_teardown);
  724. if (ret < 0)
  725. return ret;
  726. dsu_pmu_cpuhp_state = ret;
  727. ret = platform_driver_register(&dsu_pmu_driver);
  728. if (ret)
  729. cpuhp_remove_multi_state(dsu_pmu_cpuhp_state);
  730. return ret;
  731. }
  732. static void __exit dsu_pmu_exit(void)
  733. {
  734. platform_driver_unregister(&dsu_pmu_driver);
  735. cpuhp_remove_multi_state(dsu_pmu_cpuhp_state);
  736. }
  737. module_init(dsu_pmu_init);
  738. module_exit(dsu_pmu_exit);
  739. MODULE_DESCRIPTION("Perf driver for ARM DynamIQ Shared Unit");
  740. MODULE_AUTHOR("Suzuki K Poulose <[email protected]>");
  741. MODULE_LICENSE("GPL v2");