123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211 |
- # SPDX-License-Identifier: GPL-2.0-only
- #
- # Performance Monitor Drivers
- #
- menu "Performance monitor support"
- depends on PERF_EVENTS
- config ARM_CCI_PMU
- tristate "ARM CCI PMU driver"
- depends on (ARM && CPU_V7) || ARM64
- select ARM_CCI
- help
- Support for PMU events monitoring on the ARM CCI (Cache Coherent
- Interconnect) family of products.
- If compiled as a module, it will be called arm-cci.
- config ARM_CCI400_PMU
- bool "support CCI-400"
- default y
- depends on ARM_CCI_PMU
- select ARM_CCI400_COMMON
- help
- CCI-400 provides 4 independent event counters counting events related
- to the connected slave/master interfaces, plus a cycle counter.
- config ARM_CCI5xx_PMU
- bool "support CCI-500/CCI-550"
- default y
- depends on ARM_CCI_PMU
- help
- CCI-500/CCI-550 both provide 8 independent event counters, which can
- count events pertaining to the slave/master interfaces as well as the
- internal events to the CCI.
- config ARM_CCN
- tristate "ARM CCN driver support"
- depends on ARM || ARM64 || COMPILE_TEST
- help
- PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
- interconnect.
- config ARM_CMN
- tristate "Arm CMN-600 PMU support"
- depends on ARM64 || COMPILE_TEST
- help
- Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
- Network interconnect.
- config ARM_PMU
- depends on ARM || ARM64
- bool "ARM PMU framework"
- default y
- help
- Say y if you want to use CPU performance monitors on ARM-based
- systems.
- config RISCV_PMU
- depends on RISCV
- bool "RISC-V PMU framework"
- default y
- help
- Say y if you want to use CPU performance monitors on RISCV-based
- systems. This provides the core PMU framework that abstracts common
- PMU functionalities in a core library so that different PMU drivers
- can reuse it.
- config RISCV_PMU_LEGACY
- depends on RISCV_PMU
- bool "RISC-V legacy PMU implementation"
- default y
- help
- Say y if you want to use the legacy CPU performance monitor
- implementation on RISC-V based systems. This only allows counting
- of cycle/instruction counter and doesn't support counter overflow,
- or programmable counters. It will be removed in future.
- config RISCV_PMU_SBI
- depends on RISCV_PMU && RISCV_SBI
- bool "RISC-V PMU based on SBI PMU extension"
- default y
- help
- Say y if you want to use the CPU performance monitor
- using SBI PMU extension on RISC-V based systems. This option provides
- full perf feature support i.e. counter overflow, privilege mode
- filtering, counter configuration.
- config ARM_PMU_ACPI
- depends on ARM_PMU && ACPI
- def_bool y
- config ARM_SMMU_V3_PMU
- tristate "ARM SMMUv3 Performance Monitors Extension"
- depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT)
- depends on GENERIC_MSI_IRQ_DOMAIN
- help
- Provides support for the ARM SMMUv3 Performance Monitor Counter
- Groups (PMCG), which provide monitoring of transactions passing
- through the SMMU and allow the resulting information to be filtered
- based on the Stream ID of the corresponding master.
- config ARM_DSU_PMU
- tristate "ARM DynamIQ Shared Unit (DSU) PMU"
- depends on ARM64
- help
- Provides support for performance monitor unit in ARM DynamIQ Shared
- Unit (DSU). The DSU integrates one or more cores with an L3 memory
- system, control logic. The PMU allows counting various events related
- to DSU.
- config FSL_IMX8_DDR_PMU
- tristate "Freescale i.MX8 DDR perf monitor"
- depends on ARCH_MXC || COMPILE_TEST
- help
- Provides support for the DDR performance monitor in i.MX8, which
- can give information about memory throughput and other related
- events.
- config QCOM_L2_PMU
- bool "Qualcomm Technologies L2-cache PMU"
- depends on ARCH_QCOM && ARM64 && ACPI
- select QCOM_KRYO_L2_ACCESSORS
- help
- Provides support for the L2 cache performance monitor unit (PMU)
- in Qualcomm Technologies processors.
- Adds the L2 cache PMU into the perf events subsystem for
- monitoring L2 cache events.
- config QCOM_L3_PMU
- bool "Qualcomm Technologies L3-cache PMU"
- depends on ARCH_QCOM && ARM64 && ACPI
- select QCOM_IRQ_COMBINER
- help
- Provides support for the L3 cache performance monitor unit (PMU)
- in Qualcomm Technologies processors.
- Adds the L3 cache PMU into the perf events subsystem for
- monitoring L3 cache events.
- config QCOM_LLCC_PMU
- tristate "Qualcomm Technologies LLCC PMU"
- depends on ARCH_QCOM && ARM64
- help
- Provides support for the LLCC performance monitor unit (PMU) in
- Qualcomm Technologies processors.
- Adds the LLCC PMU into the perf events subsystem for monitoring
- LLCC miss events.
- config THUNDERX2_PMU
- tristate "Cavium ThunderX2 SoC PMU UNCORE"
- depends on ARCH_THUNDER2 || COMPILE_TEST
- depends on NUMA && ACPI
- default m
- help
- Provides support for ThunderX2 UNCORE events.
- The SoC has PMU support in its L3 cache controller (L3C) and
- in the DDR4 Memory Controller (DMC).
- config XGENE_PMU
- depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
- bool "APM X-Gene SoC PMU"
- default n
- help
- Say y if you want to use APM X-Gene SoC performance monitors.
- config ARM_SPE_PMU
- tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
- depends on ARM64
- help
- Enable perf support for the ARMv8.2 Statistical Profiling
- Extension, which provides periodic sampling of operations in
- the CPU pipeline and reports this via the perf AUX interface.
- config ARM_DMC620_PMU
- tristate "Enable PMU support for the ARM DMC-620 memory controller"
- depends on (ARM64 && ACPI) || COMPILE_TEST
- help
- Support for PMU events monitoring on the ARM DMC-620 memory
- controller.
- config MARVELL_CN10K_TAD_PMU
- tristate "Marvell CN10K LLC-TAD PMU"
- depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
- help
- Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
- performance monitors on CN10K family silicons.
- config APPLE_M1_CPU_PMU
- bool "Apple M1 CPU PMU support"
- depends on ARM_PMU && ARCH_APPLE
- help
- Provides support for the non-architectural CPU PMUs present on
- the Apple M1 SoCs and derivatives.
- config ALIBABA_UNCORE_DRW_PMU
- tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
- depends on (ARM64 && ACPI) || COMPILE_TEST
- help
- Support for Driveway PMU events monitoring on Yitian 710 DDR
- Sub-system.
- source "drivers/perf/hisilicon/Kconfig"
- config MARVELL_CN10K_DDR_PMU
- tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
- depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
- help
- Enable perf support for Marvell DDR Performance monitoring
- event on CN10K platform.
- endmenu
|