yenta_socket.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Regular cardbus driver ("yenta_socket")
  4. *
  5. * (C) Copyright 1999, 2000 Linus Torvalds
  6. *
  7. * Changelog:
  8. * Aug 2002: Manfred Spraul <[email protected]>
  9. * Dynamically adjust the size of the bridge resource
  10. *
  11. * May 2003: Dominik Brodowski <[email protected]>
  12. * Merge pci_socket.c and yenta.c into one file
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/workqueue.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/delay.h>
  19. #include <linux/module.h>
  20. #include <linux/io.h>
  21. #include <linux/slab.h>
  22. #include <pcmcia/ss.h>
  23. #include "yenta_socket.h"
  24. #include "i82365.h"
  25. static bool disable_clkrun;
  26. module_param(disable_clkrun, bool, 0444);
  27. MODULE_PARM_DESC(disable_clkrun,
  28. "If PC card doesn't function properly, please try this option (TI and Ricoh bridges only)");
  29. static bool isa_probe = 1;
  30. module_param(isa_probe, bool, 0444);
  31. MODULE_PARM_DESC(isa_probe, "If set ISA interrupts are probed (default). Set to N to disable probing");
  32. static bool pwr_irqs_off;
  33. module_param(pwr_irqs_off, bool, 0644);
  34. MODULE_PARM_DESC(pwr_irqs_off, "Force IRQs off during power-on of slot. Use only when seeing IRQ storms!");
  35. static char o2_speedup[] = "default";
  36. module_param_string(o2_speedup, o2_speedup, sizeof(o2_speedup), 0444);
  37. MODULE_PARM_DESC(o2_speedup, "Use prefetch/burst for O2-bridges: 'on', 'off' "
  38. "or 'default' (uses recommended behaviour for the detected bridge)");
  39. /*
  40. * Only probe "regular" interrupts, don't
  41. * touch dangerous spots like the mouse irq,
  42. * because there are mice that apparently
  43. * get really confused if they get fondled
  44. * too intimately.
  45. *
  46. * Default to 11, 10, 9, 7, 6, 5, 4, 3.
  47. */
  48. static u32 isa_interrupts = 0x0ef8;
  49. #define debug(x, s, args...) dev_dbg(&s->dev->dev, x, ##args)
  50. /* Don't ask.. */
  51. #define to_cycles(ns) ((ns)/120)
  52. #define to_ns(cycles) ((cycles)*120)
  53. /*
  54. * yenta PCI irq probing.
  55. * currently only used in the TI/EnE initialization code
  56. */
  57. #ifdef CONFIG_YENTA_TI
  58. static int yenta_probe_cb_irq(struct yenta_socket *socket);
  59. static unsigned int yenta_probe_irq(struct yenta_socket *socket,
  60. u32 isa_irq_mask);
  61. #endif
  62. static unsigned int override_bios;
  63. module_param(override_bios, uint, 0000);
  64. MODULE_PARM_DESC(override_bios, "yenta ignore bios resource allocation");
  65. /*
  66. * Generate easy-to-use ways of reading a cardbus sockets
  67. * regular memory space ("cb_xxx"), configuration space
  68. * ("config_xxx") and compatibility space ("exca_xxxx")
  69. */
  70. static inline u32 cb_readl(struct yenta_socket *socket, unsigned reg)
  71. {
  72. u32 val = readl(socket->base + reg);
  73. debug("%04x %08x\n", socket, reg, val);
  74. return val;
  75. }
  76. static inline void cb_writel(struct yenta_socket *socket, unsigned reg, u32 val)
  77. {
  78. debug("%04x %08x\n", socket, reg, val);
  79. writel(val, socket->base + reg);
  80. readl(socket->base + reg); /* avoid problems with PCI write posting */
  81. }
  82. static inline u8 config_readb(struct yenta_socket *socket, unsigned offset)
  83. {
  84. u8 val;
  85. pci_read_config_byte(socket->dev, offset, &val);
  86. debug("%04x %02x\n", socket, offset, val);
  87. return val;
  88. }
  89. static inline u16 config_readw(struct yenta_socket *socket, unsigned offset)
  90. {
  91. u16 val;
  92. pci_read_config_word(socket->dev, offset, &val);
  93. debug("%04x %04x\n", socket, offset, val);
  94. return val;
  95. }
  96. static inline u32 config_readl(struct yenta_socket *socket, unsigned offset)
  97. {
  98. u32 val;
  99. pci_read_config_dword(socket->dev, offset, &val);
  100. debug("%04x %08x\n", socket, offset, val);
  101. return val;
  102. }
  103. static inline void config_writeb(struct yenta_socket *socket, unsigned offset, u8 val)
  104. {
  105. debug("%04x %02x\n", socket, offset, val);
  106. pci_write_config_byte(socket->dev, offset, val);
  107. }
  108. static inline void config_writew(struct yenta_socket *socket, unsigned offset, u16 val)
  109. {
  110. debug("%04x %04x\n", socket, offset, val);
  111. pci_write_config_word(socket->dev, offset, val);
  112. }
  113. static inline void config_writel(struct yenta_socket *socket, unsigned offset, u32 val)
  114. {
  115. debug("%04x %08x\n", socket, offset, val);
  116. pci_write_config_dword(socket->dev, offset, val);
  117. }
  118. static inline u8 exca_readb(struct yenta_socket *socket, unsigned reg)
  119. {
  120. u8 val = readb(socket->base + 0x800 + reg);
  121. debug("%04x %02x\n", socket, reg, val);
  122. return val;
  123. }
  124. /*
  125. static inline u8 exca_readw(struct yenta_socket *socket, unsigned reg)
  126. {
  127. u16 val;
  128. val = readb(socket->base + 0x800 + reg);
  129. val |= readb(socket->base + 0x800 + reg + 1) << 8;
  130. debug("%04x %04x\n", socket, reg, val);
  131. return val;
  132. }
  133. */
  134. static inline void exca_writeb(struct yenta_socket *socket, unsigned reg, u8 val)
  135. {
  136. debug("%04x %02x\n", socket, reg, val);
  137. writeb(val, socket->base + 0x800 + reg);
  138. readb(socket->base + 0x800 + reg); /* PCI write posting... */
  139. }
  140. static void exca_writew(struct yenta_socket *socket, unsigned reg, u16 val)
  141. {
  142. debug("%04x %04x\n", socket, reg, val);
  143. writeb(val, socket->base + 0x800 + reg);
  144. writeb(val >> 8, socket->base + 0x800 + reg + 1);
  145. /* PCI write posting... */
  146. readb(socket->base + 0x800 + reg);
  147. readb(socket->base + 0x800 + reg + 1);
  148. }
  149. static ssize_t show_yenta_registers(struct device *yentadev, struct device_attribute *attr, char *buf)
  150. {
  151. struct yenta_socket *socket = dev_get_drvdata(yentadev);
  152. int offset = 0, i;
  153. offset = sysfs_emit(buf, "CB registers:");
  154. for (i = 0; i < 0x24; i += 4) {
  155. unsigned val;
  156. if (!(i & 15))
  157. offset += sysfs_emit_at(buf, offset, "\n%02x:", i);
  158. val = cb_readl(socket, i);
  159. offset += sysfs_emit_at(buf, offset, " %08x", val);
  160. }
  161. offset += sysfs_emit_at(buf, offset, "\n\nExCA registers:");
  162. for (i = 0; i < 0x45; i++) {
  163. unsigned char val;
  164. if (!(i & 7)) {
  165. if (i & 8) {
  166. memcpy(buf + offset, " -", 2);
  167. offset += 2;
  168. } else
  169. offset += sysfs_emit_at(buf, offset, "\n%02x:", i);
  170. }
  171. val = exca_readb(socket, i);
  172. offset += sysfs_emit_at(buf, offset, " %02x", val);
  173. }
  174. sysfs_emit_at(buf, offset, "\n");
  175. return offset;
  176. }
  177. static DEVICE_ATTR(yenta_registers, S_IRUSR, show_yenta_registers, NULL);
  178. /*
  179. * Ugh, mixed-mode cardbus and 16-bit pccard state: things depend
  180. * on what kind of card is inserted..
  181. */
  182. static int yenta_get_status(struct pcmcia_socket *sock, unsigned int *value)
  183. {
  184. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  185. unsigned int val;
  186. u32 state = cb_readl(socket, CB_SOCKET_STATE);
  187. val = (state & CB_3VCARD) ? SS_3VCARD : 0;
  188. val |= (state & CB_XVCARD) ? SS_XVCARD : 0;
  189. val |= (state & (CB_5VCARD | CB_3VCARD | CB_XVCARD | CB_YVCARD)) ? 0 : SS_PENDING;
  190. val |= (state & (CB_CDETECT1 | CB_CDETECT2)) ? SS_PENDING : 0;
  191. if (state & CB_CBCARD) {
  192. val |= SS_CARDBUS;
  193. val |= (state & CB_CARDSTS) ? SS_STSCHG : 0;
  194. val |= (state & (CB_CDETECT1 | CB_CDETECT2)) ? 0 : SS_DETECT;
  195. val |= (state & CB_PWRCYCLE) ? SS_POWERON | SS_READY : 0;
  196. } else if (state & CB_16BITCARD) {
  197. u8 status = exca_readb(socket, I365_STATUS);
  198. val |= ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
  199. if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) {
  200. val |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
  201. } else {
  202. val |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
  203. val |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
  204. }
  205. val |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
  206. val |= (status & I365_CS_READY) ? SS_READY : 0;
  207. val |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
  208. }
  209. *value = val;
  210. return 0;
  211. }
  212. static void yenta_set_power(struct yenta_socket *socket, socket_state_t *state)
  213. {
  214. /* some birdges require to use the ExCA registers to power 16bit cards */
  215. if (!(cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) &&
  216. (socket->flags & YENTA_16BIT_POWER_EXCA)) {
  217. u8 reg, old;
  218. reg = old = exca_readb(socket, I365_POWER);
  219. reg &= ~(I365_VCC_MASK | I365_VPP1_MASK | I365_VPP2_MASK);
  220. /* i82365SL-DF style */
  221. if (socket->flags & YENTA_16BIT_POWER_DF) {
  222. switch (state->Vcc) {
  223. case 33:
  224. reg |= I365_VCC_3V;
  225. break;
  226. case 50:
  227. reg |= I365_VCC_5V;
  228. break;
  229. default:
  230. reg = 0;
  231. break;
  232. }
  233. switch (state->Vpp) {
  234. case 33:
  235. case 50:
  236. reg |= I365_VPP1_5V;
  237. break;
  238. case 120:
  239. reg |= I365_VPP1_12V;
  240. break;
  241. }
  242. } else {
  243. /* i82365SL-B style */
  244. switch (state->Vcc) {
  245. case 50:
  246. reg |= I365_VCC_5V;
  247. break;
  248. default:
  249. reg = 0;
  250. break;
  251. }
  252. switch (state->Vpp) {
  253. case 50:
  254. reg |= I365_VPP1_5V | I365_VPP2_5V;
  255. break;
  256. case 120:
  257. reg |= I365_VPP1_12V | I365_VPP2_12V;
  258. break;
  259. }
  260. }
  261. if (reg != old)
  262. exca_writeb(socket, I365_POWER, reg);
  263. } else {
  264. u32 reg = 0; /* CB_SC_STPCLK? */
  265. switch (state->Vcc) {
  266. case 33:
  267. reg = CB_SC_VCC_3V;
  268. break;
  269. case 50:
  270. reg = CB_SC_VCC_5V;
  271. break;
  272. default:
  273. reg = 0;
  274. break;
  275. }
  276. switch (state->Vpp) {
  277. case 33:
  278. reg |= CB_SC_VPP_3V;
  279. break;
  280. case 50:
  281. reg |= CB_SC_VPP_5V;
  282. break;
  283. case 120:
  284. reg |= CB_SC_VPP_12V;
  285. break;
  286. }
  287. if (reg != cb_readl(socket, CB_SOCKET_CONTROL))
  288. cb_writel(socket, CB_SOCKET_CONTROL, reg);
  289. }
  290. }
  291. static int yenta_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
  292. {
  293. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  294. u16 bridge;
  295. /* if powering down: do it immediately */
  296. if (state->Vcc == 0)
  297. yenta_set_power(socket, state);
  298. socket->io_irq = state->io_irq;
  299. bridge = config_readw(socket, CB_BRIDGE_CONTROL) & ~(CB_BRIDGE_CRST | CB_BRIDGE_INTR);
  300. if (cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) {
  301. u8 intr;
  302. bridge |= (state->flags & SS_RESET) ? CB_BRIDGE_CRST : 0;
  303. /* ISA interrupt control? */
  304. intr = exca_readb(socket, I365_INTCTL);
  305. intr = (intr & ~0xf);
  306. if (!socket->dev->irq) {
  307. intr |= socket->cb_irq ? socket->cb_irq : state->io_irq;
  308. bridge |= CB_BRIDGE_INTR;
  309. }
  310. exca_writeb(socket, I365_INTCTL, intr);
  311. } else {
  312. u8 reg;
  313. reg = exca_readb(socket, I365_INTCTL) & (I365_RING_ENA | I365_INTR_ENA);
  314. reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
  315. reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
  316. if (state->io_irq != socket->dev->irq) {
  317. reg |= state->io_irq;
  318. bridge |= CB_BRIDGE_INTR;
  319. }
  320. exca_writeb(socket, I365_INTCTL, reg);
  321. reg = exca_readb(socket, I365_POWER) & (I365_VCC_MASK|I365_VPP1_MASK);
  322. reg |= I365_PWR_NORESET;
  323. if (state->flags & SS_PWR_AUTO)
  324. reg |= I365_PWR_AUTO;
  325. if (state->flags & SS_OUTPUT_ENA)
  326. reg |= I365_PWR_OUT;
  327. if (exca_readb(socket, I365_POWER) != reg)
  328. exca_writeb(socket, I365_POWER, reg);
  329. /* CSC interrupt: no ISA irq for CSC */
  330. reg = exca_readb(socket, I365_CSCINT);
  331. reg &= I365_CSC_IRQ_MASK;
  332. reg |= I365_CSC_DETECT;
  333. if (state->flags & SS_IOCARD) {
  334. if (state->csc_mask & SS_STSCHG)
  335. reg |= I365_CSC_STSCHG;
  336. } else {
  337. if (state->csc_mask & SS_BATDEAD)
  338. reg |= I365_CSC_BVD1;
  339. if (state->csc_mask & SS_BATWARN)
  340. reg |= I365_CSC_BVD2;
  341. if (state->csc_mask & SS_READY)
  342. reg |= I365_CSC_READY;
  343. }
  344. exca_writeb(socket, I365_CSCINT, reg);
  345. exca_readb(socket, I365_CSC);
  346. if (sock->zoom_video)
  347. sock->zoom_video(sock, state->flags & SS_ZVCARD);
  348. }
  349. config_writew(socket, CB_BRIDGE_CONTROL, bridge);
  350. /* Socket event mask: get card insert/remove events.. */
  351. cb_writel(socket, CB_SOCKET_EVENT, -1);
  352. cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK);
  353. /* if powering up: do it as the last step when the socket is configured */
  354. if (state->Vcc != 0)
  355. yenta_set_power(socket, state);
  356. return 0;
  357. }
  358. static int yenta_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
  359. {
  360. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  361. int map;
  362. unsigned char ioctl, addr, enable;
  363. map = io->map;
  364. if (map > 1)
  365. return -EINVAL;
  366. enable = I365_ENA_IO(map);
  367. addr = exca_readb(socket, I365_ADDRWIN);
  368. /* Disable the window before changing it.. */
  369. if (addr & enable) {
  370. addr &= ~enable;
  371. exca_writeb(socket, I365_ADDRWIN, addr);
  372. }
  373. exca_writew(socket, I365_IO(map)+I365_W_START, io->start);
  374. exca_writew(socket, I365_IO(map)+I365_W_STOP, io->stop);
  375. ioctl = exca_readb(socket, I365_IOCTL) & ~I365_IOCTL_MASK(map);
  376. if (io->flags & MAP_0WS)
  377. ioctl |= I365_IOCTL_0WS(map);
  378. if (io->flags & MAP_16BIT)
  379. ioctl |= I365_IOCTL_16BIT(map);
  380. if (io->flags & MAP_AUTOSZ)
  381. ioctl |= I365_IOCTL_IOCS16(map);
  382. exca_writeb(socket, I365_IOCTL, ioctl);
  383. if (io->flags & MAP_ACTIVE)
  384. exca_writeb(socket, I365_ADDRWIN, addr | enable);
  385. return 0;
  386. }
  387. static int yenta_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
  388. {
  389. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  390. struct pci_bus_region region;
  391. int map;
  392. unsigned char addr, enable;
  393. unsigned int start, stop, card_start;
  394. unsigned short word;
  395. pcibios_resource_to_bus(socket->dev->bus, &region, mem->res);
  396. map = mem->map;
  397. start = region.start;
  398. stop = region.end;
  399. card_start = mem->card_start;
  400. if (map > 4 || start > stop || ((start ^ stop) >> 24) ||
  401. (card_start >> 26) || mem->speed > 1000)
  402. return -EINVAL;
  403. enable = I365_ENA_MEM(map);
  404. addr = exca_readb(socket, I365_ADDRWIN);
  405. if (addr & enable) {
  406. addr &= ~enable;
  407. exca_writeb(socket, I365_ADDRWIN, addr);
  408. }
  409. exca_writeb(socket, CB_MEM_PAGE(map), start >> 24);
  410. word = (start >> 12) & 0x0fff;
  411. if (mem->flags & MAP_16BIT)
  412. word |= I365_MEM_16BIT;
  413. if (mem->flags & MAP_0WS)
  414. word |= I365_MEM_0WS;
  415. exca_writew(socket, I365_MEM(map) + I365_W_START, word);
  416. word = (stop >> 12) & 0x0fff;
  417. switch (to_cycles(mem->speed)) {
  418. case 0:
  419. break;
  420. case 1:
  421. word |= I365_MEM_WS0;
  422. break;
  423. case 2:
  424. word |= I365_MEM_WS1;
  425. break;
  426. default:
  427. word |= I365_MEM_WS1 | I365_MEM_WS0;
  428. break;
  429. }
  430. exca_writew(socket, I365_MEM(map) + I365_W_STOP, word);
  431. word = ((card_start - start) >> 12) & 0x3fff;
  432. if (mem->flags & MAP_WRPROT)
  433. word |= I365_MEM_WRPROT;
  434. if (mem->flags & MAP_ATTRIB)
  435. word |= I365_MEM_REG;
  436. exca_writew(socket, I365_MEM(map) + I365_W_OFF, word);
  437. if (mem->flags & MAP_ACTIVE)
  438. exca_writeb(socket, I365_ADDRWIN, addr | enable);
  439. return 0;
  440. }
  441. static irqreturn_t yenta_interrupt(int irq, void *dev_id)
  442. {
  443. unsigned int events;
  444. struct yenta_socket *socket = (struct yenta_socket *) dev_id;
  445. u8 csc;
  446. u32 cb_event;
  447. /* Clear interrupt status for the event */
  448. cb_event = cb_readl(socket, CB_SOCKET_EVENT);
  449. cb_writel(socket, CB_SOCKET_EVENT, cb_event);
  450. csc = exca_readb(socket, I365_CSC);
  451. if (!(cb_event || csc))
  452. return IRQ_NONE;
  453. events = (cb_event & (CB_CD1EVENT | CB_CD2EVENT)) ? SS_DETECT : 0 ;
  454. events |= (csc & I365_CSC_DETECT) ? SS_DETECT : 0;
  455. if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) {
  456. events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
  457. } else {
  458. events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
  459. events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
  460. events |= (csc & I365_CSC_READY) ? SS_READY : 0;
  461. }
  462. if (events)
  463. pcmcia_parse_events(&socket->socket, events);
  464. return IRQ_HANDLED;
  465. }
  466. static void yenta_interrupt_wrapper(struct timer_list *t)
  467. {
  468. struct yenta_socket *socket = from_timer(socket, t, poll_timer);
  469. yenta_interrupt(0, (void *)socket);
  470. socket->poll_timer.expires = jiffies + HZ;
  471. add_timer(&socket->poll_timer);
  472. }
  473. static void yenta_clear_maps(struct yenta_socket *socket)
  474. {
  475. int i;
  476. struct resource res = { .start = 0, .end = 0x0fff };
  477. pccard_io_map io = { 0, 0, 0, 0, 1 };
  478. pccard_mem_map mem = { .res = &res, };
  479. yenta_set_socket(&socket->socket, &dead_socket);
  480. for (i = 0; i < 2; i++) {
  481. io.map = i;
  482. yenta_set_io_map(&socket->socket, &io);
  483. }
  484. for (i = 0; i < 5; i++) {
  485. mem.map = i;
  486. yenta_set_mem_map(&socket->socket, &mem);
  487. }
  488. }
  489. /* redoes voltage interrogation if required */
  490. static void yenta_interrogate(struct yenta_socket *socket)
  491. {
  492. u32 state;
  493. state = cb_readl(socket, CB_SOCKET_STATE);
  494. if (!(state & (CB_5VCARD | CB_3VCARD | CB_XVCARD | CB_YVCARD)) ||
  495. (state & (CB_CDETECT1 | CB_CDETECT2 | CB_NOTACARD | CB_BADVCCREQ)) ||
  496. ((state & (CB_16BITCARD | CB_CBCARD)) == (CB_16BITCARD | CB_CBCARD)))
  497. cb_writel(socket, CB_SOCKET_FORCE, CB_CVSTEST);
  498. }
  499. /* Called at resume and initialization events */
  500. static int yenta_sock_init(struct pcmcia_socket *sock)
  501. {
  502. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  503. exca_writeb(socket, I365_GBLCTL, 0x00);
  504. exca_writeb(socket, I365_GENCTL, 0x00);
  505. /* Redo card voltage interrogation */
  506. yenta_interrogate(socket);
  507. yenta_clear_maps(socket);
  508. if (socket->type && socket->type->sock_init)
  509. socket->type->sock_init(socket);
  510. /* Re-enable CSC interrupts */
  511. cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK);
  512. return 0;
  513. }
  514. static int yenta_sock_suspend(struct pcmcia_socket *sock)
  515. {
  516. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  517. /* Disable CSC interrupts */
  518. cb_writel(socket, CB_SOCKET_MASK, 0x0);
  519. return 0;
  520. }
  521. /*
  522. * Use an adaptive allocation for the memory resource,
  523. * sometimes the memory behind pci bridges is limited:
  524. * 1/8 of the size of the io window of the parent.
  525. * max 4 MB, min 16 kB. We try very hard to not get below
  526. * the "ACC" values, though.
  527. */
  528. #define BRIDGE_MEM_MAX (4*1024*1024)
  529. #define BRIDGE_MEM_ACC (128*1024)
  530. #define BRIDGE_MEM_MIN (16*1024)
  531. #define BRIDGE_IO_MAX 512
  532. #define BRIDGE_IO_ACC 256
  533. #define BRIDGE_IO_MIN 32
  534. #ifndef PCIBIOS_MIN_CARDBUS_IO
  535. #define PCIBIOS_MIN_CARDBUS_IO PCIBIOS_MIN_IO
  536. #endif
  537. static int yenta_search_one_res(struct resource *root, struct resource *res,
  538. u32 min)
  539. {
  540. u32 align, size, start, end;
  541. if (res->flags & IORESOURCE_IO) {
  542. align = 1024;
  543. size = BRIDGE_IO_MAX;
  544. start = PCIBIOS_MIN_CARDBUS_IO;
  545. end = ~0U;
  546. } else {
  547. unsigned long avail = root->end - root->start;
  548. int i;
  549. size = BRIDGE_MEM_MAX;
  550. if (size > avail/8) {
  551. size = (avail+1)/8;
  552. /* round size down to next power of 2 */
  553. i = 0;
  554. while ((size /= 2) != 0)
  555. i++;
  556. size = 1 << i;
  557. }
  558. if (size < min)
  559. size = min;
  560. align = size;
  561. start = PCIBIOS_MIN_MEM;
  562. end = ~0U;
  563. }
  564. do {
  565. if (allocate_resource(root, res, size, start, end, align,
  566. NULL, NULL) == 0) {
  567. return 1;
  568. }
  569. size = size/2;
  570. align = size;
  571. } while (size >= min);
  572. return 0;
  573. }
  574. static int yenta_search_res(struct yenta_socket *socket, struct resource *res,
  575. u32 min)
  576. {
  577. struct resource *root;
  578. int i;
  579. pci_bus_for_each_resource(socket->dev->bus, root, i) {
  580. if (!root)
  581. continue;
  582. if ((res->flags ^ root->flags) &
  583. (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH))
  584. continue; /* Wrong type */
  585. if (yenta_search_one_res(root, res, min))
  586. return 1;
  587. }
  588. return 0;
  589. }
  590. static int yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned type, int addr_start, int addr_end)
  591. {
  592. struct pci_dev *dev = socket->dev;
  593. struct resource *res;
  594. struct pci_bus_region region;
  595. unsigned mask;
  596. res = &dev->resource[nr];
  597. /* Already allocated? */
  598. if (res->parent)
  599. return 0;
  600. /* The granularity of the memory limit is 4kB, on IO it's 4 bytes */
  601. mask = ~0xfff;
  602. if (type & IORESOURCE_IO)
  603. mask = ~3;
  604. res->name = dev->subordinate->name;
  605. res->flags = type;
  606. region.start = config_readl(socket, addr_start) & mask;
  607. region.end = config_readl(socket, addr_end) | ~mask;
  608. if (region.start && region.end > region.start && !override_bios) {
  609. pcibios_bus_to_resource(dev->bus, res, &region);
  610. if (pci_claim_resource(dev, nr) == 0)
  611. return 0;
  612. dev_info(&dev->dev,
  613. "Preassigned resource %d busy or not available, reconfiguring...\n",
  614. nr);
  615. }
  616. if (type & IORESOURCE_IO) {
  617. if ((yenta_search_res(socket, res, BRIDGE_IO_MAX)) ||
  618. (yenta_search_res(socket, res, BRIDGE_IO_ACC)) ||
  619. (yenta_search_res(socket, res, BRIDGE_IO_MIN)))
  620. return 1;
  621. } else {
  622. if (type & IORESOURCE_PREFETCH) {
  623. if ((yenta_search_res(socket, res, BRIDGE_MEM_MAX)) ||
  624. (yenta_search_res(socket, res, BRIDGE_MEM_ACC)) ||
  625. (yenta_search_res(socket, res, BRIDGE_MEM_MIN)))
  626. return 1;
  627. /* Approximating prefetchable by non-prefetchable */
  628. res->flags = IORESOURCE_MEM;
  629. }
  630. if ((yenta_search_res(socket, res, BRIDGE_MEM_MAX)) ||
  631. (yenta_search_res(socket, res, BRIDGE_MEM_ACC)) ||
  632. (yenta_search_res(socket, res, BRIDGE_MEM_MIN)))
  633. return 1;
  634. }
  635. dev_info(&dev->dev,
  636. "no resource of type %x available, trying to continue...\n",
  637. type);
  638. res->start = res->end = res->flags = 0;
  639. return 0;
  640. }
  641. static void yenta_free_res(struct yenta_socket *socket, int nr)
  642. {
  643. struct pci_dev *dev = socket->dev;
  644. struct resource *res;
  645. res = &dev->resource[nr];
  646. if (res->start != 0 && res->end != 0)
  647. release_resource(res);
  648. res->start = res->end = res->flags = 0;
  649. }
  650. /*
  651. * Allocate the bridge mappings for the device..
  652. */
  653. static void yenta_allocate_resources(struct yenta_socket *socket)
  654. {
  655. int program = 0;
  656. program += yenta_allocate_res(socket, PCI_CB_BRIDGE_IO_0_WINDOW,
  657. IORESOURCE_IO,
  658. PCI_CB_IO_BASE_0, PCI_CB_IO_LIMIT_0);
  659. program += yenta_allocate_res(socket, PCI_CB_BRIDGE_IO_1_WINDOW,
  660. IORESOURCE_IO,
  661. PCI_CB_IO_BASE_1, PCI_CB_IO_LIMIT_1);
  662. program += yenta_allocate_res(socket, PCI_CB_BRIDGE_MEM_0_WINDOW,
  663. IORESOURCE_MEM | IORESOURCE_PREFETCH,
  664. PCI_CB_MEMORY_BASE_0, PCI_CB_MEMORY_LIMIT_0);
  665. program += yenta_allocate_res(socket, PCI_CB_BRIDGE_MEM_1_WINDOW,
  666. IORESOURCE_MEM,
  667. PCI_CB_MEMORY_BASE_1, PCI_CB_MEMORY_LIMIT_1);
  668. if (program)
  669. pci_setup_cardbus(socket->dev->subordinate);
  670. }
  671. /*
  672. * Free the bridge mappings for the device..
  673. */
  674. static void yenta_free_resources(struct yenta_socket *socket)
  675. {
  676. yenta_free_res(socket, PCI_CB_BRIDGE_IO_0_WINDOW);
  677. yenta_free_res(socket, PCI_CB_BRIDGE_IO_1_WINDOW);
  678. yenta_free_res(socket, PCI_CB_BRIDGE_MEM_0_WINDOW);
  679. yenta_free_res(socket, PCI_CB_BRIDGE_MEM_1_WINDOW);
  680. }
  681. /*
  682. * Close it down - release our resources and go home..
  683. */
  684. static void yenta_close(struct pci_dev *dev)
  685. {
  686. struct yenta_socket *sock = pci_get_drvdata(dev);
  687. /* Remove the register attributes */
  688. device_remove_file(&dev->dev, &dev_attr_yenta_registers);
  689. /* we don't want a dying socket registered */
  690. pcmcia_unregister_socket(&sock->socket);
  691. /* Disable all events so we don't die in an IRQ storm */
  692. cb_writel(sock, CB_SOCKET_MASK, 0x0);
  693. exca_writeb(sock, I365_CSCINT, 0);
  694. if (sock->cb_irq)
  695. free_irq(sock->cb_irq, sock);
  696. else
  697. del_timer_sync(&sock->poll_timer);
  698. iounmap(sock->base);
  699. yenta_free_resources(sock);
  700. pci_release_regions(dev);
  701. pci_disable_device(dev);
  702. pci_set_drvdata(dev, NULL);
  703. kfree(sock);
  704. }
  705. static struct pccard_operations yenta_socket_operations = {
  706. .init = yenta_sock_init,
  707. .suspend = yenta_sock_suspend,
  708. .get_status = yenta_get_status,
  709. .set_socket = yenta_set_socket,
  710. .set_io_map = yenta_set_io_map,
  711. .set_mem_map = yenta_set_mem_map,
  712. };
  713. #ifdef CONFIG_YENTA_TI
  714. #include "ti113x.h"
  715. #endif
  716. #ifdef CONFIG_YENTA_RICOH
  717. #include "ricoh.h"
  718. #endif
  719. #ifdef CONFIG_YENTA_TOSHIBA
  720. #include "topic.h"
  721. #endif
  722. #ifdef CONFIG_YENTA_O2
  723. #include "o2micro.h"
  724. #endif
  725. enum {
  726. CARDBUS_TYPE_DEFAULT = -1,
  727. CARDBUS_TYPE_TI,
  728. CARDBUS_TYPE_TI113X,
  729. CARDBUS_TYPE_TI12XX,
  730. CARDBUS_TYPE_TI1250,
  731. CARDBUS_TYPE_RICOH,
  732. CARDBUS_TYPE_TOPIC95,
  733. CARDBUS_TYPE_TOPIC97,
  734. CARDBUS_TYPE_O2MICRO,
  735. CARDBUS_TYPE_ENE,
  736. };
  737. /*
  738. * Different cardbus controllers have slightly different
  739. * initialization sequences etc details. List them here..
  740. */
  741. static struct cardbus_type cardbus_type[] = {
  742. #ifdef CONFIG_YENTA_TI
  743. [CARDBUS_TYPE_TI] = {
  744. .override = ti_override,
  745. .save_state = ti_save_state,
  746. .restore_state = ti_restore_state,
  747. .sock_init = ti_init,
  748. },
  749. [CARDBUS_TYPE_TI113X] = {
  750. .override = ti113x_override,
  751. .save_state = ti_save_state,
  752. .restore_state = ti_restore_state,
  753. .sock_init = ti_init,
  754. },
  755. [CARDBUS_TYPE_TI12XX] = {
  756. .override = ti12xx_override,
  757. .save_state = ti_save_state,
  758. .restore_state = ti_restore_state,
  759. .sock_init = ti_init,
  760. },
  761. [CARDBUS_TYPE_TI1250] = {
  762. .override = ti1250_override,
  763. .save_state = ti_save_state,
  764. .restore_state = ti_restore_state,
  765. .sock_init = ti_init,
  766. },
  767. [CARDBUS_TYPE_ENE] = {
  768. .override = ene_override,
  769. .save_state = ti_save_state,
  770. .restore_state = ti_restore_state,
  771. .sock_init = ti_init,
  772. },
  773. #endif
  774. #ifdef CONFIG_YENTA_RICOH
  775. [CARDBUS_TYPE_RICOH] = {
  776. .override = ricoh_override,
  777. .save_state = ricoh_save_state,
  778. .restore_state = ricoh_restore_state,
  779. },
  780. #endif
  781. #ifdef CONFIG_YENTA_TOSHIBA
  782. [CARDBUS_TYPE_TOPIC95] = {
  783. .override = topic95_override,
  784. },
  785. [CARDBUS_TYPE_TOPIC97] = {
  786. .override = topic97_override,
  787. },
  788. #endif
  789. #ifdef CONFIG_YENTA_O2
  790. [CARDBUS_TYPE_O2MICRO] = {
  791. .override = o2micro_override,
  792. .restore_state = o2micro_restore_state,
  793. },
  794. #endif
  795. };
  796. static unsigned int yenta_probe_irq(struct yenta_socket *socket, u32 isa_irq_mask)
  797. {
  798. int i;
  799. unsigned long val;
  800. u32 mask;
  801. u8 reg;
  802. /*
  803. * Probe for usable interrupts using the force
  804. * register to generate bogus card status events.
  805. */
  806. cb_writel(socket, CB_SOCKET_EVENT, -1);
  807. cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
  808. reg = exca_readb(socket, I365_CSCINT);
  809. exca_writeb(socket, I365_CSCINT, 0);
  810. val = probe_irq_on() & isa_irq_mask;
  811. for (i = 1; i < 16; i++) {
  812. if (!((val >> i) & 1))
  813. continue;
  814. exca_writeb(socket, I365_CSCINT, I365_CSC_STSCHG | (i << 4));
  815. cb_writel(socket, CB_SOCKET_FORCE, CB_FCARDSTS);
  816. udelay(100);
  817. cb_writel(socket, CB_SOCKET_EVENT, -1);
  818. }
  819. cb_writel(socket, CB_SOCKET_MASK, 0);
  820. exca_writeb(socket, I365_CSCINT, reg);
  821. mask = probe_irq_mask(val) & 0xffff;
  822. return mask;
  823. }
  824. /*
  825. * yenta PCI irq probing.
  826. * currently only used in the TI/EnE initialization code
  827. */
  828. #ifdef CONFIG_YENTA_TI
  829. /* interrupt handler, only used during probing */
  830. static irqreturn_t yenta_probe_handler(int irq, void *dev_id)
  831. {
  832. struct yenta_socket *socket = (struct yenta_socket *) dev_id;
  833. u8 csc;
  834. u32 cb_event;
  835. /* Clear interrupt status for the event */
  836. cb_event = cb_readl(socket, CB_SOCKET_EVENT);
  837. cb_writel(socket, CB_SOCKET_EVENT, -1);
  838. csc = exca_readb(socket, I365_CSC);
  839. if (cb_event || csc) {
  840. socket->probe_status = 1;
  841. return IRQ_HANDLED;
  842. }
  843. return IRQ_NONE;
  844. }
  845. /* probes the PCI interrupt, use only on override functions */
  846. static int yenta_probe_cb_irq(struct yenta_socket *socket)
  847. {
  848. u8 reg = 0;
  849. if (!socket->cb_irq)
  850. return -1;
  851. socket->probe_status = 0;
  852. if (request_irq(socket->cb_irq, yenta_probe_handler, IRQF_SHARED, "yenta", socket)) {
  853. dev_warn(&socket->dev->dev,
  854. "request_irq() in yenta_probe_cb_irq() failed!\n");
  855. return -1;
  856. }
  857. /* generate interrupt, wait */
  858. if (!socket->dev->irq)
  859. reg = exca_readb(socket, I365_CSCINT);
  860. exca_writeb(socket, I365_CSCINT, reg | I365_CSC_STSCHG);
  861. cb_writel(socket, CB_SOCKET_EVENT, -1);
  862. cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
  863. cb_writel(socket, CB_SOCKET_FORCE, CB_FCARDSTS);
  864. msleep(100);
  865. /* disable interrupts */
  866. cb_writel(socket, CB_SOCKET_MASK, 0);
  867. exca_writeb(socket, I365_CSCINT, reg);
  868. cb_writel(socket, CB_SOCKET_EVENT, -1);
  869. exca_readb(socket, I365_CSC);
  870. free_irq(socket->cb_irq, socket);
  871. return (int) socket->probe_status;
  872. }
  873. #endif /* CONFIG_YENTA_TI */
  874. /*
  875. * Set static data that doesn't need re-initializing..
  876. */
  877. static void yenta_get_socket_capabilities(struct yenta_socket *socket, u32 isa_irq_mask)
  878. {
  879. socket->socket.pci_irq = socket->cb_irq;
  880. if (isa_probe)
  881. socket->socket.irq_mask = yenta_probe_irq(socket, isa_irq_mask);
  882. else
  883. socket->socket.irq_mask = 0;
  884. dev_info(&socket->dev->dev, "ISA IRQ mask 0x%04x, PCI irq %d\n",
  885. socket->socket.irq_mask, socket->cb_irq);
  886. }
  887. /*
  888. * Initialize the standard cardbus registers
  889. */
  890. static void yenta_config_init(struct yenta_socket *socket)
  891. {
  892. u16 bridge;
  893. struct pci_dev *dev = socket->dev;
  894. struct pci_bus_region region;
  895. pcibios_resource_to_bus(socket->dev->bus, &region, &dev->resource[0]);
  896. config_writel(socket, CB_LEGACY_MODE_BASE, 0);
  897. config_writel(socket, PCI_BASE_ADDRESS_0, region.start);
  898. config_writew(socket, PCI_COMMAND,
  899. PCI_COMMAND_IO |
  900. PCI_COMMAND_MEMORY |
  901. PCI_COMMAND_MASTER |
  902. PCI_COMMAND_WAIT);
  903. /* MAGIC NUMBERS! Fixme */
  904. config_writeb(socket, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES / 4);
  905. config_writeb(socket, PCI_LATENCY_TIMER, 168);
  906. config_writel(socket, PCI_PRIMARY_BUS,
  907. (176 << 24) | /* sec. latency timer */
  908. ((unsigned int)dev->subordinate->busn_res.end << 16) | /* subordinate bus */
  909. ((unsigned int)dev->subordinate->busn_res.start << 8) | /* secondary bus */
  910. dev->subordinate->primary); /* primary bus */
  911. /*
  912. * Set up the bridging state:
  913. * - enable write posting.
  914. * - memory window 0 prefetchable, window 1 non-prefetchable
  915. * - PCI interrupts enabled if a PCI interrupt exists..
  916. */
  917. bridge = config_readw(socket, CB_BRIDGE_CONTROL);
  918. bridge &= ~(CB_BRIDGE_CRST | CB_BRIDGE_PREFETCH1 | CB_BRIDGE_ISAEN | CB_BRIDGE_VGAEN);
  919. bridge |= CB_BRIDGE_PREFETCH0 | CB_BRIDGE_POSTEN;
  920. config_writew(socket, CB_BRIDGE_CONTROL, bridge);
  921. }
  922. /**
  923. * yenta_fixup_parent_bridge - Fix subordinate bus# of the parent bridge
  924. * @cardbus_bridge: The PCI bus which the CardBus bridge bridges to
  925. *
  926. * Checks if devices on the bus which the CardBus bridge bridges to would be
  927. * invisible during PCI scans because of a misconfigured subordinate number
  928. * of the parent brige - some BIOSes seem to be too lazy to set it right.
  929. * Does the fixup carefully by checking how far it can go without conflicts.
  930. * See http://bugzilla.kernel.org/show_bug.cgi?id=2944 for more information.
  931. */
  932. static void yenta_fixup_parent_bridge(struct pci_bus *cardbus_bridge)
  933. {
  934. struct pci_bus *sibling;
  935. unsigned char upper_limit;
  936. /*
  937. * We only check and fix the parent bridge: All systems which need
  938. * this fixup that have been reviewed are laptops and the only bridge
  939. * which needed fixing was the parent bridge of the CardBus bridge:
  940. */
  941. struct pci_bus *bridge_to_fix = cardbus_bridge->parent;
  942. /* Check bus numbers are already set up correctly: */
  943. if (bridge_to_fix->busn_res.end >= cardbus_bridge->busn_res.end)
  944. return; /* The subordinate number is ok, nothing to do */
  945. if (!bridge_to_fix->parent)
  946. return; /* Root bridges are ok */
  947. /* stay within the limits of the bus range of the parent: */
  948. upper_limit = bridge_to_fix->parent->busn_res.end;
  949. /* check the bus ranges of all sibling bridges to prevent overlap */
  950. list_for_each_entry(sibling, &bridge_to_fix->parent->children,
  951. node) {
  952. /*
  953. * If the sibling has a higher secondary bus number
  954. * and it's secondary is equal or smaller than our
  955. * current upper limit, set the new upper limit to
  956. * the bus number below the sibling's range:
  957. */
  958. if (sibling->busn_res.start > bridge_to_fix->busn_res.end
  959. && sibling->busn_res.start <= upper_limit)
  960. upper_limit = sibling->busn_res.start - 1;
  961. }
  962. /* Show that the wanted subordinate number is not possible: */
  963. if (cardbus_bridge->busn_res.end > upper_limit)
  964. dev_warn(&cardbus_bridge->dev,
  965. "Upper limit for fixing this bridge's parent bridge: #%02x\n",
  966. upper_limit);
  967. /* If we have room to increase the bridge's subordinate number, */
  968. if (bridge_to_fix->busn_res.end < upper_limit) {
  969. /* use the highest number of the hidden bus, within limits */
  970. unsigned char subordinate_to_assign =
  971. min_t(int, cardbus_bridge->busn_res.end, upper_limit);
  972. dev_info(&bridge_to_fix->dev,
  973. "Raising subordinate bus# of parent bus (#%02x) from #%02x to #%02x\n",
  974. bridge_to_fix->number,
  975. (int)bridge_to_fix->busn_res.end,
  976. subordinate_to_assign);
  977. /* Save the new subordinate in the bus struct of the bridge */
  978. bridge_to_fix->busn_res.end = subordinate_to_assign;
  979. /* and update the PCI config space with the new subordinate */
  980. pci_write_config_byte(bridge_to_fix->self,
  981. PCI_SUBORDINATE_BUS, bridge_to_fix->busn_res.end);
  982. }
  983. }
  984. /*
  985. * Initialize a cardbus controller. Make sure we have a usable
  986. * interrupt, and that we can map the cardbus area. Fill in the
  987. * socket information structure..
  988. */
  989. static int yenta_probe(struct pci_dev *dev, const struct pci_device_id *id)
  990. {
  991. struct yenta_socket *socket;
  992. int ret;
  993. /*
  994. * If we failed to assign proper bus numbers for this cardbus
  995. * controller during PCI probe, its subordinate pci_bus is NULL.
  996. * Bail out if so.
  997. */
  998. if (!dev->subordinate) {
  999. dev_err(&dev->dev, "no bus associated! (try 'pci=assign-busses')\n");
  1000. return -ENODEV;
  1001. }
  1002. socket = kzalloc(sizeof(struct yenta_socket), GFP_KERNEL);
  1003. if (!socket)
  1004. return -ENOMEM;
  1005. /* prepare pcmcia_socket */
  1006. socket->socket.ops = &yenta_socket_operations;
  1007. socket->socket.resource_ops = &pccard_nonstatic_ops;
  1008. socket->socket.dev.parent = &dev->dev;
  1009. socket->socket.driver_data = socket;
  1010. socket->socket.owner = THIS_MODULE;
  1011. socket->socket.features = SS_CAP_PAGE_REGS | SS_CAP_PCCARD;
  1012. socket->socket.map_size = 0x1000;
  1013. socket->socket.cb_dev = dev;
  1014. /* prepare struct yenta_socket */
  1015. socket->dev = dev;
  1016. pci_set_drvdata(dev, socket);
  1017. /*
  1018. * Do some basic sanity checking..
  1019. */
  1020. if (pci_enable_device(dev)) {
  1021. ret = -EBUSY;
  1022. goto free;
  1023. }
  1024. ret = pci_request_regions(dev, "yenta_socket");
  1025. if (ret)
  1026. goto disable;
  1027. if (!pci_resource_start(dev, 0)) {
  1028. dev_err(&dev->dev, "No cardbus resource!\n");
  1029. ret = -ENODEV;
  1030. goto release;
  1031. }
  1032. /*
  1033. * Ok, start setup.. Map the cardbus registers,
  1034. * and request the IRQ.
  1035. */
  1036. socket->base = ioremap(pci_resource_start(dev, 0), 0x1000);
  1037. if (!socket->base) {
  1038. ret = -ENOMEM;
  1039. goto release;
  1040. }
  1041. /*
  1042. * report the subsystem vendor and device for help debugging
  1043. * the irq stuff...
  1044. */
  1045. dev_info(&dev->dev, "CardBus bridge found [%04x:%04x]\n",
  1046. dev->subsystem_vendor, dev->subsystem_device);
  1047. yenta_config_init(socket);
  1048. /* Disable all events */
  1049. cb_writel(socket, CB_SOCKET_MASK, 0x0);
  1050. /* Set up the bridge regions.. */
  1051. yenta_allocate_resources(socket);
  1052. socket->cb_irq = dev->irq;
  1053. /* Do we have special options for the device? */
  1054. if (id->driver_data != CARDBUS_TYPE_DEFAULT &&
  1055. id->driver_data < ARRAY_SIZE(cardbus_type)) {
  1056. socket->type = &cardbus_type[id->driver_data];
  1057. ret = socket->type->override(socket);
  1058. if (ret < 0)
  1059. goto unmap;
  1060. }
  1061. /* We must finish initialization here */
  1062. if (!socket->cb_irq || request_irq(socket->cb_irq, yenta_interrupt, IRQF_SHARED, "yenta", socket)) {
  1063. /* No IRQ or request_irq failed. Poll */
  1064. socket->cb_irq = 0; /* But zero is a valid IRQ number. */
  1065. timer_setup(&socket->poll_timer, yenta_interrupt_wrapper, 0);
  1066. mod_timer(&socket->poll_timer, jiffies + HZ);
  1067. dev_info(&dev->dev,
  1068. "no PCI IRQ, CardBus support disabled for this socket.\n");
  1069. dev_info(&dev->dev,
  1070. "check your BIOS CardBus, BIOS IRQ or ACPI settings.\n");
  1071. } else {
  1072. socket->socket.features |= SS_CAP_CARDBUS;
  1073. }
  1074. /* Figure out what the dang thing can do for the PCMCIA layer... */
  1075. yenta_interrogate(socket);
  1076. yenta_get_socket_capabilities(socket, isa_interrupts);
  1077. dev_info(&dev->dev, "Socket status: %08x\n",
  1078. cb_readl(socket, CB_SOCKET_STATE));
  1079. yenta_fixup_parent_bridge(dev->subordinate);
  1080. /* Register it with the pcmcia layer.. */
  1081. ret = pcmcia_register_socket(&socket->socket);
  1082. if (ret)
  1083. goto free_irq;
  1084. /* Add the yenta register attributes */
  1085. ret = device_create_file(&dev->dev, &dev_attr_yenta_registers);
  1086. if (ret)
  1087. goto unregister_socket;
  1088. return ret;
  1089. /* error path... */
  1090. unregister_socket:
  1091. pcmcia_unregister_socket(&socket->socket);
  1092. free_irq:
  1093. if (socket->cb_irq)
  1094. free_irq(socket->cb_irq, socket);
  1095. else
  1096. del_timer_sync(&socket->poll_timer);
  1097. unmap:
  1098. iounmap(socket->base);
  1099. yenta_free_resources(socket);
  1100. release:
  1101. pci_release_regions(dev);
  1102. disable:
  1103. pci_disable_device(dev);
  1104. free:
  1105. pci_set_drvdata(dev, NULL);
  1106. kfree(socket);
  1107. return ret;
  1108. }
  1109. #ifdef CONFIG_PM_SLEEP
  1110. static int yenta_dev_suspend_noirq(struct device *dev)
  1111. {
  1112. struct pci_dev *pdev = to_pci_dev(dev);
  1113. struct yenta_socket *socket = pci_get_drvdata(pdev);
  1114. if (!socket)
  1115. return 0;
  1116. if (socket->type && socket->type->save_state)
  1117. socket->type->save_state(socket);
  1118. pci_save_state(pdev);
  1119. pci_read_config_dword(pdev, 16*4, &socket->saved_state[0]);
  1120. pci_read_config_dword(pdev, 17*4, &socket->saved_state[1]);
  1121. pci_disable_device(pdev);
  1122. return 0;
  1123. }
  1124. static int yenta_dev_resume_noirq(struct device *dev)
  1125. {
  1126. struct pci_dev *pdev = to_pci_dev(dev);
  1127. struct yenta_socket *socket = pci_get_drvdata(pdev);
  1128. int ret;
  1129. if (!socket)
  1130. return 0;
  1131. pci_write_config_dword(pdev, 16*4, socket->saved_state[0]);
  1132. pci_write_config_dword(pdev, 17*4, socket->saved_state[1]);
  1133. ret = pci_enable_device(pdev);
  1134. if (ret)
  1135. return ret;
  1136. pci_set_master(pdev);
  1137. if (socket->type && socket->type->restore_state)
  1138. socket->type->restore_state(socket);
  1139. return 0;
  1140. }
  1141. static const struct dev_pm_ops yenta_pm_ops = {
  1142. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(yenta_dev_suspend_noirq, yenta_dev_resume_noirq)
  1143. };
  1144. #define YENTA_PM_OPS (&yenta_pm_ops)
  1145. #else
  1146. #define YENTA_PM_OPS NULL
  1147. #endif
  1148. #define CB_ID(vend, dev, type) \
  1149. { \
  1150. .vendor = vend, \
  1151. .device = dev, \
  1152. .subvendor = PCI_ANY_ID, \
  1153. .subdevice = PCI_ANY_ID, \
  1154. .class = PCI_CLASS_BRIDGE_CARDBUS << 8, \
  1155. .class_mask = ~0, \
  1156. .driver_data = CARDBUS_TYPE_##type, \
  1157. }
  1158. static const struct pci_device_id yenta_table[] = {
  1159. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1031, TI),
  1160. /*
  1161. * TBD: Check if these TI variants can use more
  1162. * advanced overrides instead. (I can't get the
  1163. * data sheets for these devices. --rmk)
  1164. */
  1165. #ifdef CONFIG_YENTA_TI
  1166. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1210, TI),
  1167. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1130, TI113X),
  1168. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1131, TI113X),
  1169. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1211, TI12XX),
  1170. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1220, TI12XX),
  1171. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1221, TI12XX),
  1172. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1225, TI12XX),
  1173. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1251A, TI12XX),
  1174. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1251B, TI12XX),
  1175. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, TI12XX),
  1176. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1450, TI12XX),
  1177. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1451A, TI12XX),
  1178. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510, TI12XX),
  1179. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520, TI12XX),
  1180. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1620, TI12XX),
  1181. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_4410, TI12XX),
  1182. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_4450, TI12XX),
  1183. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_4451, TI12XX),
  1184. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_4510, TI12XX),
  1185. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_4520, TI12XX),
  1186. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1250, TI1250),
  1187. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1410, TI1250),
  1188. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XX21_XX11, TI12XX),
  1189. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_X515, TI12XX),
  1190. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XX12, TI12XX),
  1191. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_X420, TI12XX),
  1192. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_X620, TI12XX),
  1193. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_7410, TI12XX),
  1194. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_7510, TI12XX),
  1195. CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_7610, TI12XX),
  1196. CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_710, ENE),
  1197. CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_712, ENE),
  1198. CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_720, ENE),
  1199. CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_722, ENE),
  1200. CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1211, ENE),
  1201. CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1225, ENE),
  1202. CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1410, ENE),
  1203. CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1420, ENE),
  1204. #endif /* CONFIG_YENTA_TI */
  1205. #ifdef CONFIG_YENTA_RICOH
  1206. CB_ID(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C465, RICOH),
  1207. CB_ID(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C466, RICOH),
  1208. CB_ID(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C475, RICOH),
  1209. CB_ID(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, RICOH),
  1210. CB_ID(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C478, RICOH),
  1211. #endif
  1212. #ifdef CONFIG_YENTA_TOSHIBA
  1213. CB_ID(PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC95, TOPIC95),
  1214. CB_ID(PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC97, TOPIC97),
  1215. CB_ID(PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC100, TOPIC97),
  1216. #endif
  1217. #ifdef CONFIG_YENTA_O2
  1218. CB_ID(PCI_VENDOR_ID_O2, PCI_ANY_ID, O2MICRO),
  1219. #endif
  1220. /* match any cardbus bridge */
  1221. CB_ID(PCI_ANY_ID, PCI_ANY_ID, DEFAULT),
  1222. { /* all zeroes */ }
  1223. };
  1224. MODULE_DEVICE_TABLE(pci, yenta_table);
  1225. static struct pci_driver yenta_cardbus_driver = {
  1226. .name = "yenta_cardbus",
  1227. .id_table = yenta_table,
  1228. .probe = yenta_probe,
  1229. .remove = yenta_close,
  1230. .driver.pm = YENTA_PM_OPS,
  1231. };
  1232. module_pci_driver(yenta_cardbus_driver);
  1233. MODULE_LICENSE("GPL");