parport_pc.c 86 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Low-level parallel-port routines for 8255-based PC-style hardware.
  3. *
  4. * Authors: Phil Blundell <[email protected]>
  5. * Tim Waugh <[email protected]>
  6. * Jose Renau <[email protected]>
  7. * David Campbell
  8. * Andrea Arcangeli
  9. *
  10. * based on work by Grant Guenther <[email protected]> and Phil Blundell.
  11. *
  12. * Cleaned up include files - Russell King <[email protected]>
  13. * DMA support - Bert De Jonghe <[email protected]>
  14. * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
  15. * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
  16. * Various hacks, Fred Barnes, 04/2001
  17. * Updated probing logic - Adam Belay <[email protected]>
  18. */
  19. /* This driver should work with any hardware that is broadly compatible
  20. * with that in the IBM PC. This applies to the majority of integrated
  21. * I/O chipsets that are commonly available. The expected register
  22. * layout is:
  23. *
  24. * base+0 data
  25. * base+1 status
  26. * base+2 control
  27. *
  28. * In addition, there are some optional registers:
  29. *
  30. * base+3 EPP address
  31. * base+4 EPP data
  32. * base+0x400 ECP config A
  33. * base+0x401 ECP config B
  34. * base+0x402 ECP control
  35. *
  36. * All registers are 8 bits wide and read/write. If your hardware differs
  37. * only in register addresses (eg because your registers are on 32-bit
  38. * word boundaries) then you can alter the constants in parport_pc.h to
  39. * accommodate this.
  40. *
  41. * Note that the ECP registers may not start at offset 0x400 for PCI cards,
  42. * but rather will start at port->base_hi.
  43. */
  44. #include <linux/module.h>
  45. #include <linux/init.h>
  46. #include <linux/sched/signal.h>
  47. #include <linux/delay.h>
  48. #include <linux/errno.h>
  49. #include <linux/interrupt.h>
  50. #include <linux/ioport.h>
  51. #include <linux/kernel.h>
  52. #include <linux/slab.h>
  53. #include <linux/dma-mapping.h>
  54. #include <linux/pci.h>
  55. #include <linux/pnp.h>
  56. #include <linux/platform_device.h>
  57. #include <linux/sysctl.h>
  58. #include <linux/io.h>
  59. #include <linux/uaccess.h>
  60. #include <asm/dma.h>
  61. #include <linux/parport.h>
  62. #include <linux/parport_pc.h>
  63. #include <linux/via.h>
  64. #include <asm/parport.h>
  65. #define PARPORT_PC_MAX_PORTS PARPORT_MAX
  66. #ifdef CONFIG_ISA_DMA_API
  67. #define HAS_DMA
  68. #endif
  69. /* ECR modes */
  70. #define ECR_SPP 00
  71. #define ECR_PS2 01
  72. #define ECR_PPF 02
  73. #define ECR_ECP 03
  74. #define ECR_EPP 04
  75. #define ECR_VND 05
  76. #define ECR_TST 06
  77. #define ECR_CNF 07
  78. #define ECR_MODE_MASK 0xe0
  79. #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
  80. #undef DEBUG
  81. #define NR_SUPERIOS 3
  82. static struct superio_struct { /* For Super-IO chips autodetection */
  83. int io;
  84. int irq;
  85. int dma;
  86. } superios[NR_SUPERIOS] = { {0,},};
  87. static int user_specified;
  88. #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
  89. (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
  90. static int verbose_probing;
  91. #endif
  92. static int pci_registered_parport;
  93. static int pnp_registered_parport;
  94. /* frob_control, but for ECR */
  95. static void frob_econtrol(struct parport *pb, unsigned char m,
  96. unsigned char v)
  97. {
  98. unsigned char ectr = 0;
  99. if (m != 0xff)
  100. ectr = inb(ECONTROL(pb));
  101. pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n",
  102. m, v, ectr, (ectr & ~m) ^ v);
  103. outb((ectr & ~m) ^ v, ECONTROL(pb));
  104. }
  105. static inline void frob_set_mode(struct parport *p, int mode)
  106. {
  107. frob_econtrol(p, ECR_MODE_MASK, mode << 5);
  108. }
  109. #ifdef CONFIG_PARPORT_PC_FIFO
  110. /* Safely change the mode bits in the ECR
  111. Returns:
  112. 0 : Success
  113. -EBUSY: Could not drain FIFO in some finite amount of time,
  114. mode not changed!
  115. */
  116. static int change_mode(struct parport *p, int m)
  117. {
  118. const struct parport_pc_private *priv = p->physport->private_data;
  119. unsigned char oecr;
  120. int mode;
  121. pr_debug("parport change_mode ECP-ISA to mode 0x%02x\n", m);
  122. if (!priv->ecr) {
  123. printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
  124. return 0;
  125. }
  126. /* Bits <7:5> contain the mode. */
  127. oecr = inb(ECONTROL(p));
  128. mode = (oecr >> 5) & 0x7;
  129. if (mode == m)
  130. return 0;
  131. if (mode >= 2 && !(priv->ctr & 0x20)) {
  132. /* This mode resets the FIFO, so we may
  133. * have to wait for it to drain first. */
  134. unsigned long expire = jiffies + p->physport->cad->timeout;
  135. int counter;
  136. switch (mode) {
  137. case ECR_PPF: /* Parallel Port FIFO mode */
  138. case ECR_ECP: /* ECP Parallel Port mode */
  139. /* Busy wait for 200us */
  140. for (counter = 0; counter < 40; counter++) {
  141. if (inb(ECONTROL(p)) & 0x01)
  142. break;
  143. if (signal_pending(current))
  144. break;
  145. udelay(5);
  146. }
  147. /* Poll slowly. */
  148. while (!(inb(ECONTROL(p)) & 0x01)) {
  149. if (time_after_eq(jiffies, expire))
  150. /* The FIFO is stuck. */
  151. return -EBUSY;
  152. schedule_timeout_interruptible(
  153. msecs_to_jiffies(10));
  154. if (signal_pending(current))
  155. break;
  156. }
  157. }
  158. }
  159. if (mode >= 2 && m >= 2) {
  160. /* We have to go through mode 001 */
  161. oecr &= ~(7 << 5);
  162. oecr |= ECR_PS2 << 5;
  163. ECR_WRITE(p, oecr);
  164. }
  165. /* Set the mode. */
  166. oecr &= ~(7 << 5);
  167. oecr |= m << 5;
  168. ECR_WRITE(p, oecr);
  169. return 0;
  170. }
  171. #endif /* FIFO support */
  172. /*
  173. * Clear TIMEOUT BIT in EPP MODE
  174. *
  175. * This is also used in SPP detection.
  176. */
  177. static int clear_epp_timeout(struct parport *pb)
  178. {
  179. unsigned char r;
  180. if (!(parport_pc_read_status(pb) & 0x01))
  181. return 1;
  182. /* To clear timeout some chips require double read */
  183. parport_pc_read_status(pb);
  184. r = parport_pc_read_status(pb);
  185. outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
  186. outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
  187. r = parport_pc_read_status(pb);
  188. return !(r & 0x01);
  189. }
  190. /*
  191. * Access functions.
  192. *
  193. * Most of these aren't static because they may be used by the
  194. * parport_xxx_yyy macros. extern __inline__ versions of several
  195. * of these are in parport_pc.h.
  196. */
  197. static void parport_pc_init_state(struct pardevice *dev,
  198. struct parport_state *s)
  199. {
  200. s->u.pc.ctr = 0xc;
  201. if (dev->irq_func &&
  202. dev->port->irq != PARPORT_IRQ_NONE)
  203. /* Set ackIntEn */
  204. s->u.pc.ctr |= 0x10;
  205. s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
  206. * D.Gruszka VScom */
  207. }
  208. static void parport_pc_save_state(struct parport *p, struct parport_state *s)
  209. {
  210. const struct parport_pc_private *priv = p->physport->private_data;
  211. s->u.pc.ctr = priv->ctr;
  212. if (priv->ecr)
  213. s->u.pc.ecr = inb(ECONTROL(p));
  214. }
  215. static void parport_pc_restore_state(struct parport *p,
  216. struct parport_state *s)
  217. {
  218. struct parport_pc_private *priv = p->physport->private_data;
  219. register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
  220. outb(c, CONTROL(p));
  221. priv->ctr = c;
  222. if (priv->ecr)
  223. ECR_WRITE(p, s->u.pc.ecr);
  224. }
  225. #ifdef CONFIG_PARPORT_1284
  226. static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
  227. size_t length, int flags)
  228. {
  229. size_t got = 0;
  230. if (flags & PARPORT_W91284PIC) {
  231. unsigned char status;
  232. size_t left = length;
  233. /* use knowledge about data lines..:
  234. * nFault is 0 if there is at least 1 byte in the Warp's FIFO
  235. * pError is 1 if there are 16 bytes in the Warp's FIFO
  236. */
  237. status = inb(STATUS(port));
  238. while (!(status & 0x08) && got < length) {
  239. if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
  240. /* can grab 16 bytes from warp fifo */
  241. if (!((long)buf & 0x03))
  242. insl(EPPDATA(port), buf, 4);
  243. else
  244. insb(EPPDATA(port), buf, 16);
  245. buf += 16;
  246. got += 16;
  247. left -= 16;
  248. } else {
  249. /* grab single byte from the warp fifo */
  250. *((char *)buf) = inb(EPPDATA(port));
  251. buf++;
  252. got++;
  253. left--;
  254. }
  255. status = inb(STATUS(port));
  256. if (status & 0x01) {
  257. /* EPP timeout should never occur... */
  258. printk(KERN_DEBUG "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n",
  259. port->name);
  260. clear_epp_timeout(port);
  261. }
  262. }
  263. return got;
  264. }
  265. if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
  266. if (!(((long)buf | length) & 0x03))
  267. insl(EPPDATA(port), buf, (length >> 2));
  268. else
  269. insb(EPPDATA(port), buf, length);
  270. if (inb(STATUS(port)) & 0x01) {
  271. clear_epp_timeout(port);
  272. return -EIO;
  273. }
  274. return length;
  275. }
  276. for (; got < length; got++) {
  277. *((char *)buf) = inb(EPPDATA(port));
  278. buf++;
  279. if (inb(STATUS(port)) & 0x01) {
  280. /* EPP timeout */
  281. clear_epp_timeout(port);
  282. break;
  283. }
  284. }
  285. return got;
  286. }
  287. static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
  288. size_t length, int flags)
  289. {
  290. size_t written = 0;
  291. if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
  292. if (!(((long)buf | length) & 0x03))
  293. outsl(EPPDATA(port), buf, (length >> 2));
  294. else
  295. outsb(EPPDATA(port), buf, length);
  296. if (inb(STATUS(port)) & 0x01) {
  297. clear_epp_timeout(port);
  298. return -EIO;
  299. }
  300. return length;
  301. }
  302. for (; written < length; written++) {
  303. outb(*((char *)buf), EPPDATA(port));
  304. buf++;
  305. if (inb(STATUS(port)) & 0x01) {
  306. clear_epp_timeout(port);
  307. break;
  308. }
  309. }
  310. return written;
  311. }
  312. static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
  313. size_t length, int flags)
  314. {
  315. size_t got = 0;
  316. if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
  317. insb(EPPADDR(port), buf, length);
  318. if (inb(STATUS(port)) & 0x01) {
  319. clear_epp_timeout(port);
  320. return -EIO;
  321. }
  322. return length;
  323. }
  324. for (; got < length; got++) {
  325. *((char *)buf) = inb(EPPADDR(port));
  326. buf++;
  327. if (inb(STATUS(port)) & 0x01) {
  328. clear_epp_timeout(port);
  329. break;
  330. }
  331. }
  332. return got;
  333. }
  334. static size_t parport_pc_epp_write_addr(struct parport *port,
  335. const void *buf, size_t length,
  336. int flags)
  337. {
  338. size_t written = 0;
  339. if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
  340. outsb(EPPADDR(port), buf, length);
  341. if (inb(STATUS(port)) & 0x01) {
  342. clear_epp_timeout(port);
  343. return -EIO;
  344. }
  345. return length;
  346. }
  347. for (; written < length; written++) {
  348. outb(*((char *)buf), EPPADDR(port));
  349. buf++;
  350. if (inb(STATUS(port)) & 0x01) {
  351. clear_epp_timeout(port);
  352. break;
  353. }
  354. }
  355. return written;
  356. }
  357. static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
  358. size_t length, int flags)
  359. {
  360. size_t got;
  361. frob_set_mode(port, ECR_EPP);
  362. parport_pc_data_reverse(port);
  363. parport_pc_write_control(port, 0x4);
  364. got = parport_pc_epp_read_data(port, buf, length, flags);
  365. frob_set_mode(port, ECR_PS2);
  366. return got;
  367. }
  368. static size_t parport_pc_ecpepp_write_data(struct parport *port,
  369. const void *buf, size_t length,
  370. int flags)
  371. {
  372. size_t written;
  373. frob_set_mode(port, ECR_EPP);
  374. parport_pc_write_control(port, 0x4);
  375. parport_pc_data_forward(port);
  376. written = parport_pc_epp_write_data(port, buf, length, flags);
  377. frob_set_mode(port, ECR_PS2);
  378. return written;
  379. }
  380. static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
  381. size_t length, int flags)
  382. {
  383. size_t got;
  384. frob_set_mode(port, ECR_EPP);
  385. parport_pc_data_reverse(port);
  386. parport_pc_write_control(port, 0x4);
  387. got = parport_pc_epp_read_addr(port, buf, length, flags);
  388. frob_set_mode(port, ECR_PS2);
  389. return got;
  390. }
  391. static size_t parport_pc_ecpepp_write_addr(struct parport *port,
  392. const void *buf, size_t length,
  393. int flags)
  394. {
  395. size_t written;
  396. frob_set_mode(port, ECR_EPP);
  397. parport_pc_write_control(port, 0x4);
  398. parport_pc_data_forward(port);
  399. written = parport_pc_epp_write_addr(port, buf, length, flags);
  400. frob_set_mode(port, ECR_PS2);
  401. return written;
  402. }
  403. #endif /* IEEE 1284 support */
  404. #ifdef CONFIG_PARPORT_PC_FIFO
  405. static size_t parport_pc_fifo_write_block_pio(struct parport *port,
  406. const void *buf, size_t length)
  407. {
  408. int ret = 0;
  409. const unsigned char *bufp = buf;
  410. size_t left = length;
  411. unsigned long expire = jiffies + port->physport->cad->timeout;
  412. const unsigned long fifo = FIFO(port);
  413. int poll_for = 8; /* 80 usecs */
  414. const struct parport_pc_private *priv = port->physport->private_data;
  415. const int fifo_depth = priv->fifo_depth;
  416. port = port->physport;
  417. /* We don't want to be interrupted every character. */
  418. parport_pc_disable_irq(port);
  419. /* set nErrIntrEn and serviceIntr */
  420. frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
  421. /* Forward mode. */
  422. parport_pc_data_forward(port); /* Must be in PS2 mode */
  423. while (left) {
  424. unsigned char byte;
  425. unsigned char ecrval = inb(ECONTROL(port));
  426. int i = 0;
  427. if (need_resched() && time_before(jiffies, expire))
  428. /* Can't yield the port. */
  429. schedule();
  430. /* Anyone else waiting for the port? */
  431. if (port->waithead) {
  432. printk(KERN_DEBUG "Somebody wants the port\n");
  433. break;
  434. }
  435. if (ecrval & 0x02) {
  436. /* FIFO is full. Wait for interrupt. */
  437. /* Clear serviceIntr */
  438. ECR_WRITE(port, ecrval & ~(1<<2));
  439. false_alarm:
  440. ret = parport_wait_event(port, HZ);
  441. if (ret < 0)
  442. break;
  443. ret = 0;
  444. if (!time_before(jiffies, expire)) {
  445. /* Timed out. */
  446. printk(KERN_DEBUG "FIFO write timed out\n");
  447. break;
  448. }
  449. ecrval = inb(ECONTROL(port));
  450. if (!(ecrval & (1<<2))) {
  451. if (need_resched() &&
  452. time_before(jiffies, expire))
  453. schedule();
  454. goto false_alarm;
  455. }
  456. continue;
  457. }
  458. /* Can't fail now. */
  459. expire = jiffies + port->cad->timeout;
  460. poll:
  461. if (signal_pending(current))
  462. break;
  463. if (ecrval & 0x01) {
  464. /* FIFO is empty. Blast it full. */
  465. const int n = left < fifo_depth ? left : fifo_depth;
  466. outsb(fifo, bufp, n);
  467. bufp += n;
  468. left -= n;
  469. /* Adjust the poll time. */
  470. if (i < (poll_for - 2))
  471. poll_for--;
  472. continue;
  473. } else if (i++ < poll_for) {
  474. udelay(10);
  475. ecrval = inb(ECONTROL(port));
  476. goto poll;
  477. }
  478. /* Half-full(call me an optimist) */
  479. byte = *bufp++;
  480. outb(byte, fifo);
  481. left--;
  482. }
  483. dump_parport_state("leave fifo_write_block_pio", port);
  484. return length - left;
  485. }
  486. #ifdef HAS_DMA
  487. static size_t parport_pc_fifo_write_block_dma(struct parport *port,
  488. const void *buf, size_t length)
  489. {
  490. int ret = 0;
  491. unsigned long dmaflag;
  492. size_t left = length;
  493. const struct parport_pc_private *priv = port->physport->private_data;
  494. struct device *dev = port->physport->dev;
  495. dma_addr_t dma_addr, dma_handle;
  496. size_t maxlen = 0x10000; /* max 64k per DMA transfer */
  497. unsigned long start = (unsigned long) buf;
  498. unsigned long end = (unsigned long) buf + length - 1;
  499. dump_parport_state("enter fifo_write_block_dma", port);
  500. if (end < MAX_DMA_ADDRESS) {
  501. /* If it would cross a 64k boundary, cap it at the end. */
  502. if ((start ^ end) & ~0xffffUL)
  503. maxlen = 0x10000 - (start & 0xffff);
  504. dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
  505. DMA_TO_DEVICE);
  506. } else {
  507. /* above 16 MB we use a bounce buffer as ISA-DMA
  508. is not possible */
  509. maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
  510. dma_addr = priv->dma_handle;
  511. dma_handle = 0;
  512. }
  513. port = port->physport;
  514. /* We don't want to be interrupted every character. */
  515. parport_pc_disable_irq(port);
  516. /* set nErrIntrEn and serviceIntr */
  517. frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
  518. /* Forward mode. */
  519. parport_pc_data_forward(port); /* Must be in PS2 mode */
  520. while (left) {
  521. unsigned long expire = jiffies + port->physport->cad->timeout;
  522. size_t count = left;
  523. if (count > maxlen)
  524. count = maxlen;
  525. if (!dma_handle) /* bounce buffer ! */
  526. memcpy(priv->dma_buf, buf, count);
  527. dmaflag = claim_dma_lock();
  528. disable_dma(port->dma);
  529. clear_dma_ff(port->dma);
  530. set_dma_mode(port->dma, DMA_MODE_WRITE);
  531. set_dma_addr(port->dma, dma_addr);
  532. set_dma_count(port->dma, count);
  533. /* Set DMA mode */
  534. frob_econtrol(port, 1<<3, 1<<3);
  535. /* Clear serviceIntr */
  536. frob_econtrol(port, 1<<2, 0);
  537. enable_dma(port->dma);
  538. release_dma_lock(dmaflag);
  539. /* assume DMA will be successful */
  540. left -= count;
  541. buf += count;
  542. if (dma_handle)
  543. dma_addr += count;
  544. /* Wait for interrupt. */
  545. false_alarm:
  546. ret = parport_wait_event(port, HZ);
  547. if (ret < 0)
  548. break;
  549. ret = 0;
  550. if (!time_before(jiffies, expire)) {
  551. /* Timed out. */
  552. printk(KERN_DEBUG "DMA write timed out\n");
  553. break;
  554. }
  555. /* Is serviceIntr set? */
  556. if (!(inb(ECONTROL(port)) & (1<<2))) {
  557. cond_resched();
  558. goto false_alarm;
  559. }
  560. dmaflag = claim_dma_lock();
  561. disable_dma(port->dma);
  562. clear_dma_ff(port->dma);
  563. count = get_dma_residue(port->dma);
  564. release_dma_lock(dmaflag);
  565. cond_resched(); /* Can't yield the port. */
  566. /* Anyone else waiting for the port? */
  567. if (port->waithead) {
  568. printk(KERN_DEBUG "Somebody wants the port\n");
  569. break;
  570. }
  571. /* update for possible DMA residue ! */
  572. buf -= count;
  573. left += count;
  574. if (dma_handle)
  575. dma_addr -= count;
  576. }
  577. /* Maybe got here through break, so adjust for DMA residue! */
  578. dmaflag = claim_dma_lock();
  579. disable_dma(port->dma);
  580. clear_dma_ff(port->dma);
  581. left += get_dma_residue(port->dma);
  582. release_dma_lock(dmaflag);
  583. /* Turn off DMA mode */
  584. frob_econtrol(port, 1<<3, 0);
  585. if (dma_handle)
  586. dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
  587. dump_parport_state("leave fifo_write_block_dma", port);
  588. return length - left;
  589. }
  590. #endif
  591. static inline size_t parport_pc_fifo_write_block(struct parport *port,
  592. const void *buf, size_t length)
  593. {
  594. #ifdef HAS_DMA
  595. if (port->dma != PARPORT_DMA_NONE)
  596. return parport_pc_fifo_write_block_dma(port, buf, length);
  597. #endif
  598. return parport_pc_fifo_write_block_pio(port, buf, length);
  599. }
  600. /* Parallel Port FIFO mode (ECP chipsets) */
  601. static size_t parport_pc_compat_write_block_pio(struct parport *port,
  602. const void *buf, size_t length,
  603. int flags)
  604. {
  605. size_t written;
  606. int r;
  607. unsigned long expire;
  608. const struct parport_pc_private *priv = port->physport->private_data;
  609. /* Special case: a timeout of zero means we cannot call schedule().
  610. * Also if O_NONBLOCK is set then use the default implementation. */
  611. if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
  612. return parport_ieee1284_write_compat(port, buf,
  613. length, flags);
  614. /* Set up parallel port FIFO mode.*/
  615. parport_pc_data_forward(port); /* Must be in PS2 mode */
  616. parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
  617. r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
  618. if (r)
  619. printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
  620. port->name);
  621. port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
  622. /* Write the data to the FIFO. */
  623. written = parport_pc_fifo_write_block(port, buf, length);
  624. /* Finish up. */
  625. /* For some hardware we don't want to touch the mode until
  626. * the FIFO is empty, so allow 4 seconds for each position
  627. * in the fifo.
  628. */
  629. expire = jiffies + (priv->fifo_depth * HZ * 4);
  630. do {
  631. /* Wait for the FIFO to empty */
  632. r = change_mode(port, ECR_PS2);
  633. if (r != -EBUSY)
  634. break;
  635. } while (time_before(jiffies, expire));
  636. if (r == -EBUSY) {
  637. printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
  638. /* Prevent further data transfer. */
  639. frob_set_mode(port, ECR_TST);
  640. /* Adjust for the contents of the FIFO. */
  641. for (written -= priv->fifo_depth; ; written++) {
  642. if (inb(ECONTROL(port)) & 0x2) {
  643. /* Full up. */
  644. break;
  645. }
  646. outb(0, FIFO(port));
  647. }
  648. /* Reset the FIFO and return to PS2 mode. */
  649. frob_set_mode(port, ECR_PS2);
  650. }
  651. r = parport_wait_peripheral(port,
  652. PARPORT_STATUS_BUSY,
  653. PARPORT_STATUS_BUSY);
  654. if (r)
  655. printk(KERN_DEBUG "%s: BUSY timeout (%d) in compat_write_block_pio\n",
  656. port->name, r);
  657. port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
  658. return written;
  659. }
  660. /* ECP */
  661. #ifdef CONFIG_PARPORT_1284
  662. static size_t parport_pc_ecp_write_block_pio(struct parport *port,
  663. const void *buf, size_t length,
  664. int flags)
  665. {
  666. size_t written;
  667. int r;
  668. unsigned long expire;
  669. const struct parport_pc_private *priv = port->physport->private_data;
  670. /* Special case: a timeout of zero means we cannot call schedule().
  671. * Also if O_NONBLOCK is set then use the default implementation. */
  672. if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
  673. return parport_ieee1284_ecp_write_data(port, buf,
  674. length, flags);
  675. /* Switch to forward mode if necessary. */
  676. if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
  677. /* Event 47: Set nInit high. */
  678. parport_frob_control(port,
  679. PARPORT_CONTROL_INIT
  680. | PARPORT_CONTROL_AUTOFD,
  681. PARPORT_CONTROL_INIT
  682. | PARPORT_CONTROL_AUTOFD);
  683. /* Event 49: PError goes high. */
  684. r = parport_wait_peripheral(port,
  685. PARPORT_STATUS_PAPEROUT,
  686. PARPORT_STATUS_PAPEROUT);
  687. if (r) {
  688. printk(KERN_DEBUG "%s: PError timeout (%d) in ecp_write_block_pio\n",
  689. port->name, r);
  690. }
  691. }
  692. /* Set up ECP parallel port mode.*/
  693. parport_pc_data_forward(port); /* Must be in PS2 mode */
  694. parport_pc_frob_control(port,
  695. PARPORT_CONTROL_STROBE |
  696. PARPORT_CONTROL_AUTOFD,
  697. 0);
  698. r = change_mode(port, ECR_ECP); /* ECP FIFO */
  699. if (r)
  700. printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
  701. port->name);
  702. port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
  703. /* Write the data to the FIFO. */
  704. written = parport_pc_fifo_write_block(port, buf, length);
  705. /* Finish up. */
  706. /* For some hardware we don't want to touch the mode until
  707. * the FIFO is empty, so allow 4 seconds for each position
  708. * in the fifo.
  709. */
  710. expire = jiffies + (priv->fifo_depth * (HZ * 4));
  711. do {
  712. /* Wait for the FIFO to empty */
  713. r = change_mode(port, ECR_PS2);
  714. if (r != -EBUSY)
  715. break;
  716. } while (time_before(jiffies, expire));
  717. if (r == -EBUSY) {
  718. printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
  719. /* Prevent further data transfer. */
  720. frob_set_mode(port, ECR_TST);
  721. /* Adjust for the contents of the FIFO. */
  722. for (written -= priv->fifo_depth; ; written++) {
  723. if (inb(ECONTROL(port)) & 0x2) {
  724. /* Full up. */
  725. break;
  726. }
  727. outb(0, FIFO(port));
  728. }
  729. /* Reset the FIFO and return to PS2 mode. */
  730. frob_set_mode(port, ECR_PS2);
  731. /* Host transfer recovery. */
  732. parport_pc_data_reverse(port); /* Must be in PS2 mode */
  733. udelay(5);
  734. parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
  735. r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
  736. if (r)
  737. printk(KERN_DEBUG "%s: PE,1 timeout (%d) in ecp_write_block_pio\n",
  738. port->name, r);
  739. parport_frob_control(port,
  740. PARPORT_CONTROL_INIT,
  741. PARPORT_CONTROL_INIT);
  742. r = parport_wait_peripheral(port,
  743. PARPORT_STATUS_PAPEROUT,
  744. PARPORT_STATUS_PAPEROUT);
  745. if (r)
  746. printk(KERN_DEBUG "%s: PE,2 timeout (%d) in ecp_write_block_pio\n",
  747. port->name, r);
  748. }
  749. r = parport_wait_peripheral(port,
  750. PARPORT_STATUS_BUSY,
  751. PARPORT_STATUS_BUSY);
  752. if (r)
  753. printk(KERN_DEBUG "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
  754. port->name, r);
  755. port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
  756. return written;
  757. }
  758. #endif /* IEEE 1284 support */
  759. #endif /* Allowed to use FIFO/DMA */
  760. /*
  761. * ******************************************
  762. * INITIALISATION AND MODULE STUFF BELOW HERE
  763. * ******************************************
  764. */
  765. /* GCC is not inlining extern inline function later overwritten to non-inline,
  766. so we use outlined_ variants here. */
  767. static const struct parport_operations parport_pc_ops = {
  768. .write_data = parport_pc_write_data,
  769. .read_data = parport_pc_read_data,
  770. .write_control = parport_pc_write_control,
  771. .read_control = parport_pc_read_control,
  772. .frob_control = parport_pc_frob_control,
  773. .read_status = parport_pc_read_status,
  774. .enable_irq = parport_pc_enable_irq,
  775. .disable_irq = parport_pc_disable_irq,
  776. .data_forward = parport_pc_data_forward,
  777. .data_reverse = parport_pc_data_reverse,
  778. .init_state = parport_pc_init_state,
  779. .save_state = parport_pc_save_state,
  780. .restore_state = parport_pc_restore_state,
  781. .epp_write_data = parport_ieee1284_epp_write_data,
  782. .epp_read_data = parport_ieee1284_epp_read_data,
  783. .epp_write_addr = parport_ieee1284_epp_write_addr,
  784. .epp_read_addr = parport_ieee1284_epp_read_addr,
  785. .ecp_write_data = parport_ieee1284_ecp_write_data,
  786. .ecp_read_data = parport_ieee1284_ecp_read_data,
  787. .ecp_write_addr = parport_ieee1284_ecp_write_addr,
  788. .compat_write_data = parport_ieee1284_write_compat,
  789. .nibble_read_data = parport_ieee1284_read_nibble,
  790. .byte_read_data = parport_ieee1284_read_byte,
  791. .owner = THIS_MODULE,
  792. };
  793. #ifdef CONFIG_PARPORT_PC_SUPERIO
  794. static struct superio_struct *find_free_superio(void)
  795. {
  796. int i;
  797. for (i = 0; i < NR_SUPERIOS; i++)
  798. if (superios[i].io == 0)
  799. return &superios[i];
  800. return NULL;
  801. }
  802. /* Super-IO chipset detection, Winbond, SMSC */
  803. static void show_parconfig_smsc37c669(int io, int key)
  804. {
  805. int cr1, cr4, cra, cr23, cr26, cr27;
  806. struct superio_struct *s;
  807. static const char *const modes[] = {
  808. "SPP and Bidirectional (PS/2)",
  809. "EPP and SPP",
  810. "ECP",
  811. "ECP and EPP" };
  812. outb(key, io);
  813. outb(key, io);
  814. outb(1, io);
  815. cr1 = inb(io + 1);
  816. outb(4, io);
  817. cr4 = inb(io + 1);
  818. outb(0x0a, io);
  819. cra = inb(io + 1);
  820. outb(0x23, io);
  821. cr23 = inb(io + 1);
  822. outb(0x26, io);
  823. cr26 = inb(io + 1);
  824. outb(0x27, io);
  825. cr27 = inb(io + 1);
  826. outb(0xaa, io);
  827. if (verbose_probing) {
  828. pr_info("SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
  829. cr1, cr4, cra, cr23, cr26, cr27);
  830. /* The documentation calls DMA and IRQ-Lines by letters, so
  831. the board maker can/will wire them
  832. appropriately/randomly... G=reserved H=IDE-irq, */
  833. pr_info("SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
  834. cr23 * 4,
  835. (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
  836. (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
  837. cra & 0x0f);
  838. pr_info("SMSC LPT Config: enabled=%s power=%s\n",
  839. (cr23 * 4 >= 0x100) ? "yes" : "no",
  840. (cr1 & 4) ? "yes" : "no");
  841. pr_info("SMSC LPT Config: Port mode=%s, EPP version =%s\n",
  842. (cr1 & 0x08) ? "Standard mode only (SPP)"
  843. : modes[cr4 & 0x03],
  844. (cr4 & 0x40) ? "1.7" : "1.9");
  845. }
  846. /* Heuristics ! BIOS setup for this mainboard device limits
  847. the choices to standard settings, i.e. io-address and IRQ
  848. are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
  849. DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
  850. if (cr23 * 4 >= 0x100) { /* if active */
  851. s = find_free_superio();
  852. if (s == NULL)
  853. pr_info("Super-IO: too many chips!\n");
  854. else {
  855. int d;
  856. switch (cr23 * 4) {
  857. case 0x3bc:
  858. s->io = 0x3bc;
  859. s->irq = 7;
  860. break;
  861. case 0x378:
  862. s->io = 0x378;
  863. s->irq = 7;
  864. break;
  865. case 0x278:
  866. s->io = 0x278;
  867. s->irq = 5;
  868. }
  869. d = (cr26 & 0x0f);
  870. if (d == 1 || d == 3)
  871. s->dma = d;
  872. else
  873. s->dma = PARPORT_DMA_NONE;
  874. }
  875. }
  876. }
  877. static void show_parconfig_winbond(int io, int key)
  878. {
  879. int cr30, cr60, cr61, cr70, cr74, crf0;
  880. struct superio_struct *s;
  881. static const char *const modes[] = {
  882. "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
  883. "EPP-1.9 and SPP",
  884. "ECP",
  885. "ECP and EPP-1.9",
  886. "Standard (SPP)",
  887. "EPP-1.7 and SPP", /* 5 */
  888. "undefined!",
  889. "ECP and EPP-1.7" };
  890. static char *const irqtypes[] = {
  891. "pulsed low, high-Z",
  892. "follows nACK" };
  893. /* The registers are called compatible-PnP because the
  894. register layout is modelled after ISA-PnP, the access
  895. method is just another ... */
  896. outb(key, io);
  897. outb(key, io);
  898. outb(0x07, io); /* Register 7: Select Logical Device */
  899. outb(0x01, io + 1); /* LD1 is Parallel Port */
  900. outb(0x30, io);
  901. cr30 = inb(io + 1);
  902. outb(0x60, io);
  903. cr60 = inb(io + 1);
  904. outb(0x61, io);
  905. cr61 = inb(io + 1);
  906. outb(0x70, io);
  907. cr70 = inb(io + 1);
  908. outb(0x74, io);
  909. cr74 = inb(io + 1);
  910. outb(0xf0, io);
  911. crf0 = inb(io + 1);
  912. outb(0xaa, io);
  913. if (verbose_probing) {
  914. pr_info("Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
  915. cr30, cr60, cr61, cr70, cr74, crf0);
  916. pr_info("Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
  917. (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
  918. if ((cr74 & 0x07) > 3)
  919. pr_cont("dma=none\n");
  920. else
  921. pr_cont("dma=%d\n", cr74 & 0x07);
  922. pr_info("Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
  923. irqtypes[crf0 >> 7], (crf0 >> 3) & 0x0f);
  924. pr_info("Winbond LPT Config: Port mode=%s\n",
  925. modes[crf0 & 0x07]);
  926. }
  927. if (cr30 & 0x01) { /* the settings can be interrogated later ... */
  928. s = find_free_superio();
  929. if (s == NULL)
  930. pr_info("Super-IO: too many chips!\n");
  931. else {
  932. s->io = (cr60 << 8) | cr61;
  933. s->irq = cr70 & 0x0f;
  934. s->dma = (((cr74 & 0x07) > 3) ?
  935. PARPORT_DMA_NONE : (cr74 & 0x07));
  936. }
  937. }
  938. }
  939. static void decode_winbond(int efer, int key, int devid, int devrev, int oldid)
  940. {
  941. const char *type = "unknown";
  942. int id, progif = 2;
  943. if (devid == devrev)
  944. /* simple heuristics, we happened to read some
  945. non-winbond register */
  946. return;
  947. id = (devid << 8) | devrev;
  948. /* Values are from public data sheets pdf files, I can just
  949. confirm 83977TF is correct :-) */
  950. if (id == 0x9771)
  951. type = "83977F/AF";
  952. else if (id == 0x9773)
  953. type = "83977TF / SMSC 97w33x/97w34x";
  954. else if (id == 0x9774)
  955. type = "83977ATF";
  956. else if ((id & ~0x0f) == 0x5270)
  957. type = "83977CTF / SMSC 97w36x";
  958. else if ((id & ~0x0f) == 0x52f0)
  959. type = "83977EF / SMSC 97w35x";
  960. else if ((id & ~0x0f) == 0x5210)
  961. type = "83627";
  962. else if ((id & ~0x0f) == 0x6010)
  963. type = "83697HF";
  964. else if ((oldid & 0x0f) == 0x0a) {
  965. type = "83877F";
  966. progif = 1;
  967. } else if ((oldid & 0x0f) == 0x0b) {
  968. type = "83877AF";
  969. progif = 1;
  970. } else if ((oldid & 0x0f) == 0x0c) {
  971. type = "83877TF";
  972. progif = 1;
  973. } else if ((oldid & 0x0f) == 0x0d) {
  974. type = "83877ATF";
  975. progif = 1;
  976. } else
  977. progif = 0;
  978. if (verbose_probing)
  979. pr_info("Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x oldid=%02x type=%s\n",
  980. efer, key, devid, devrev, oldid, type);
  981. if (progif == 2)
  982. show_parconfig_winbond(efer, key);
  983. }
  984. static void decode_smsc(int efer, int key, int devid, int devrev)
  985. {
  986. const char *type = "unknown";
  987. void (*func)(int io, int key);
  988. int id;
  989. if (devid == devrev)
  990. /* simple heuristics, we happened to read some
  991. non-smsc register */
  992. return;
  993. func = NULL;
  994. id = (devid << 8) | devrev;
  995. if (id == 0x0302) {
  996. type = "37c669";
  997. func = show_parconfig_smsc37c669;
  998. } else if (id == 0x6582)
  999. type = "37c665IR";
  1000. else if (devid == 0x65)
  1001. type = "37c665GT";
  1002. else if (devid == 0x66)
  1003. type = "37c666GT";
  1004. if (verbose_probing)
  1005. pr_info("SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x type=%s\n",
  1006. efer, key, devid, devrev, type);
  1007. if (func)
  1008. func(efer, key);
  1009. }
  1010. static void winbond_check(int io, int key)
  1011. {
  1012. int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
  1013. if (!request_region(io, 3, __func__))
  1014. return;
  1015. origval = inb(io); /* Save original value */
  1016. /* First probe without key */
  1017. outb(0x20, io);
  1018. x_devid = inb(io + 1);
  1019. outb(0x21, io);
  1020. x_devrev = inb(io + 1);
  1021. outb(0x09, io);
  1022. x_oldid = inb(io + 1);
  1023. outb(key, io);
  1024. outb(key, io); /* Write Magic Sequence to EFER, extended
  1025. function enable register */
  1026. outb(0x20, io); /* Write EFIR, extended function index register */
  1027. devid = inb(io + 1); /* Read EFDR, extended function data register */
  1028. outb(0x21, io);
  1029. devrev = inb(io + 1);
  1030. outb(0x09, io);
  1031. oldid = inb(io + 1);
  1032. outb(0xaa, io); /* Magic Seal */
  1033. outb(origval, io); /* in case we poked some entirely different hardware */
  1034. if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
  1035. goto out; /* protection against false positives */
  1036. decode_winbond(io, key, devid, devrev, oldid);
  1037. out:
  1038. release_region(io, 3);
  1039. }
  1040. static void winbond_check2(int io, int key)
  1041. {
  1042. int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
  1043. if (!request_region(io, 3, __func__))
  1044. return;
  1045. origval[0] = inb(io); /* Save original values */
  1046. origval[1] = inb(io + 1);
  1047. origval[2] = inb(io + 2);
  1048. /* First probe without the key */
  1049. outb(0x20, io + 2);
  1050. x_devid = inb(io + 2);
  1051. outb(0x21, io + 1);
  1052. x_devrev = inb(io + 2);
  1053. outb(0x09, io + 1);
  1054. x_oldid = inb(io + 2);
  1055. outb(key, io); /* Write Magic Byte to EFER, extended
  1056. function enable register */
  1057. outb(0x20, io + 2); /* Write EFIR, extended function index register */
  1058. devid = inb(io + 2); /* Read EFDR, extended function data register */
  1059. outb(0x21, io + 1);
  1060. devrev = inb(io + 2);
  1061. outb(0x09, io + 1);
  1062. oldid = inb(io + 2);
  1063. outb(0xaa, io); /* Magic Seal */
  1064. outb(origval[0], io); /* in case we poked some entirely different hardware */
  1065. outb(origval[1], io + 1);
  1066. outb(origval[2], io + 2);
  1067. if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
  1068. goto out; /* protection against false positives */
  1069. decode_winbond(io, key, devid, devrev, oldid);
  1070. out:
  1071. release_region(io, 3);
  1072. }
  1073. static void smsc_check(int io, int key)
  1074. {
  1075. int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
  1076. if (!request_region(io, 3, __func__))
  1077. return;
  1078. origval = inb(io); /* Save original value */
  1079. /* First probe without the key */
  1080. outb(0x0d, io);
  1081. x_oldid = inb(io + 1);
  1082. outb(0x0e, io);
  1083. x_oldrev = inb(io + 1);
  1084. outb(0x20, io);
  1085. x_id = inb(io + 1);
  1086. outb(0x21, io);
  1087. x_rev = inb(io + 1);
  1088. outb(key, io);
  1089. outb(key, io); /* Write Magic Sequence to EFER, extended
  1090. function enable register */
  1091. outb(0x0d, io); /* Write EFIR, extended function index register */
  1092. oldid = inb(io + 1); /* Read EFDR, extended function data register */
  1093. outb(0x0e, io);
  1094. oldrev = inb(io + 1);
  1095. outb(0x20, io);
  1096. id = inb(io + 1);
  1097. outb(0x21, io);
  1098. rev = inb(io + 1);
  1099. outb(0xaa, io); /* Magic Seal */
  1100. outb(origval, io); /* in case we poked some entirely different hardware */
  1101. if (x_id == id && x_oldrev == oldrev &&
  1102. x_oldid == oldid && x_rev == rev)
  1103. goto out; /* protection against false positives */
  1104. decode_smsc(io, key, oldid, oldrev);
  1105. out:
  1106. release_region(io, 3);
  1107. }
  1108. static void detect_and_report_winbond(void)
  1109. {
  1110. if (verbose_probing)
  1111. printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
  1112. winbond_check(0x3f0, 0x87);
  1113. winbond_check(0x370, 0x87);
  1114. winbond_check(0x2e , 0x87);
  1115. winbond_check(0x4e , 0x87);
  1116. winbond_check(0x3f0, 0x86);
  1117. winbond_check2(0x250, 0x88);
  1118. winbond_check2(0x250, 0x89);
  1119. }
  1120. static void detect_and_report_smsc(void)
  1121. {
  1122. if (verbose_probing)
  1123. printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
  1124. smsc_check(0x3f0, 0x55);
  1125. smsc_check(0x370, 0x55);
  1126. smsc_check(0x3f0, 0x44);
  1127. smsc_check(0x370, 0x44);
  1128. }
  1129. static void detect_and_report_it87(void)
  1130. {
  1131. u16 dev;
  1132. u8 origval, r;
  1133. if (verbose_probing)
  1134. printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
  1135. if (!request_muxed_region(0x2e, 2, __func__))
  1136. return;
  1137. origval = inb(0x2e); /* Save original value */
  1138. outb(0x87, 0x2e);
  1139. outb(0x01, 0x2e);
  1140. outb(0x55, 0x2e);
  1141. outb(0x55, 0x2e);
  1142. outb(0x20, 0x2e);
  1143. dev = inb(0x2f) << 8;
  1144. outb(0x21, 0x2e);
  1145. dev |= inb(0x2f);
  1146. if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
  1147. dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
  1148. pr_info("IT%04X SuperIO detected\n", dev);
  1149. outb(0x07, 0x2E); /* Parallel Port */
  1150. outb(0x03, 0x2F);
  1151. outb(0xF0, 0x2E); /* BOOT 0x80 off */
  1152. r = inb(0x2f);
  1153. outb(0xF0, 0x2E);
  1154. outb(r | 8, 0x2F);
  1155. outb(0x02, 0x2E); /* Lock */
  1156. outb(0x02, 0x2F);
  1157. } else {
  1158. outb(origval, 0x2e); /* Oops, sorry to disturb */
  1159. }
  1160. release_region(0x2e, 2);
  1161. }
  1162. #endif /* CONFIG_PARPORT_PC_SUPERIO */
  1163. static struct superio_struct *find_superio(struct parport *p)
  1164. {
  1165. int i;
  1166. for (i = 0; i < NR_SUPERIOS; i++)
  1167. if (superios[i].io == p->base)
  1168. return &superios[i];
  1169. return NULL;
  1170. }
  1171. static int get_superio_dma(struct parport *p)
  1172. {
  1173. struct superio_struct *s = find_superio(p);
  1174. if (s)
  1175. return s->dma;
  1176. return PARPORT_DMA_NONE;
  1177. }
  1178. static int get_superio_irq(struct parport *p)
  1179. {
  1180. struct superio_struct *s = find_superio(p);
  1181. if (s)
  1182. return s->irq;
  1183. return PARPORT_IRQ_NONE;
  1184. }
  1185. /* --- Mode detection ------------------------------------- */
  1186. /*
  1187. * Checks for port existence, all ports support SPP MODE
  1188. * Returns:
  1189. * 0 : No parallel port at this address
  1190. * PARPORT_MODE_PCSPP : SPP port detected
  1191. * (if the user specified an ioport himself,
  1192. * this shall always be the case!)
  1193. *
  1194. */
  1195. static int parport_SPP_supported(struct parport *pb)
  1196. {
  1197. unsigned char r, w;
  1198. /*
  1199. * first clear an eventually pending EPP timeout
  1200. * I ([email protected]) have an SMSC chipset
  1201. * that does not even respond to SPP cycles if an EPP
  1202. * timeout is pending
  1203. */
  1204. clear_epp_timeout(pb);
  1205. /* Do a simple read-write test to make sure the port exists. */
  1206. w = 0xc;
  1207. outb(w, CONTROL(pb));
  1208. /* Is there a control register that we can read from? Some
  1209. * ports don't allow reads, so read_control just returns a
  1210. * software copy. Some ports _do_ allow reads, so bypass the
  1211. * software copy here. In addition, some bits aren't
  1212. * writable. */
  1213. r = inb(CONTROL(pb));
  1214. if ((r & 0xf) == w) {
  1215. w = 0xe;
  1216. outb(w, CONTROL(pb));
  1217. r = inb(CONTROL(pb));
  1218. outb(0xc, CONTROL(pb));
  1219. if ((r & 0xf) == w)
  1220. return PARPORT_MODE_PCSPP;
  1221. }
  1222. if (user_specified)
  1223. /* That didn't work, but the user thinks there's a
  1224. * port here. */
  1225. pr_info("parport 0x%lx (WARNING): CTR: wrote 0x%02x, read 0x%02x\n",
  1226. pb->base, w, r);
  1227. /* Try the data register. The data lines aren't tri-stated at
  1228. * this stage, so we expect back what we wrote. */
  1229. w = 0xaa;
  1230. parport_pc_write_data(pb, w);
  1231. r = parport_pc_read_data(pb);
  1232. if (r == w) {
  1233. w = 0x55;
  1234. parport_pc_write_data(pb, w);
  1235. r = parport_pc_read_data(pb);
  1236. if (r == w)
  1237. return PARPORT_MODE_PCSPP;
  1238. }
  1239. if (user_specified) {
  1240. /* Didn't work, but the user is convinced this is the
  1241. * place. */
  1242. pr_info("parport 0x%lx (WARNING): DATA: wrote 0x%02x, read 0x%02x\n",
  1243. pb->base, w, r);
  1244. pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n",
  1245. pb->base);
  1246. }
  1247. /* It's possible that we can't read the control register or
  1248. * the data register. In that case just believe the user. */
  1249. if (user_specified)
  1250. return PARPORT_MODE_PCSPP;
  1251. return 0;
  1252. }
  1253. /* Check for ECR
  1254. *
  1255. * Old style XT ports alias io ports every 0x400, hence accessing ECR
  1256. * on these cards actually accesses the CTR.
  1257. *
  1258. * Modern cards don't do this but reading from ECR will return 0xff
  1259. * regardless of what is written here if the card does NOT support
  1260. * ECP.
  1261. *
  1262. * We first check to see if ECR is the same as CTR. If not, the low
  1263. * two bits of ECR aren't writable, so we check by writing ECR and
  1264. * reading it back to see if it's what we expect.
  1265. */
  1266. static int parport_ECR_present(struct parport *pb)
  1267. {
  1268. struct parport_pc_private *priv = pb->private_data;
  1269. unsigned char r = 0xc;
  1270. outb(r, CONTROL(pb));
  1271. if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
  1272. outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
  1273. r = inb(CONTROL(pb));
  1274. if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
  1275. goto no_reg; /* Sure that no ECR register exists */
  1276. }
  1277. if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
  1278. goto no_reg;
  1279. ECR_WRITE(pb, 0x34);
  1280. if (inb(ECONTROL(pb)) != 0x35)
  1281. goto no_reg;
  1282. priv->ecr = 1;
  1283. outb(0xc, CONTROL(pb));
  1284. /* Go to mode 000 */
  1285. frob_set_mode(pb, ECR_SPP);
  1286. return 1;
  1287. no_reg:
  1288. outb(0xc, CONTROL(pb));
  1289. return 0;
  1290. }
  1291. #ifdef CONFIG_PARPORT_1284
  1292. /* Detect PS/2 support.
  1293. *
  1294. * Bit 5 (0x20) sets the PS/2 data direction; setting this high
  1295. * allows us to read data from the data lines. In theory we would get back
  1296. * 0xff but any peripheral attached to the port may drag some or all of the
  1297. * lines down to zero. So if we get back anything that isn't the contents
  1298. * of the data register we deem PS/2 support to be present.
  1299. *
  1300. * Some SPP ports have "half PS/2" ability - you can't turn off the line
  1301. * drivers, but an external peripheral with sufficiently beefy drivers of
  1302. * its own can overpower them and assert its own levels onto the bus, from
  1303. * where they can then be read back as normal. Ports with this property
  1304. * and the right type of device attached are likely to fail the SPP test,
  1305. * (as they will appear to have stuck bits) and so the fact that they might
  1306. * be misdetected here is rather academic.
  1307. */
  1308. static int parport_PS2_supported(struct parport *pb)
  1309. {
  1310. int ok = 0;
  1311. clear_epp_timeout(pb);
  1312. /* try to tri-state the buffer */
  1313. parport_pc_data_reverse(pb);
  1314. parport_pc_write_data(pb, 0x55);
  1315. if (parport_pc_read_data(pb) != 0x55)
  1316. ok++;
  1317. parport_pc_write_data(pb, 0xaa);
  1318. if (parport_pc_read_data(pb) != 0xaa)
  1319. ok++;
  1320. /* cancel input mode */
  1321. parport_pc_data_forward(pb);
  1322. if (ok) {
  1323. pb->modes |= PARPORT_MODE_TRISTATE;
  1324. } else {
  1325. struct parport_pc_private *priv = pb->private_data;
  1326. priv->ctr_writable &= ~0x20;
  1327. }
  1328. return ok;
  1329. }
  1330. #ifdef CONFIG_PARPORT_PC_FIFO
  1331. static int parport_ECP_supported(struct parport *pb)
  1332. {
  1333. int i;
  1334. int config, configb;
  1335. int pword;
  1336. struct parport_pc_private *priv = pb->private_data;
  1337. /* Translate ECP intrLine to ISA irq value */
  1338. static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
  1339. /* If there is no ECR, we have no hope of supporting ECP. */
  1340. if (!priv->ecr)
  1341. return 0;
  1342. /* Find out FIFO depth */
  1343. ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
  1344. ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
  1345. for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
  1346. outb(0xaa, FIFO(pb));
  1347. /*
  1348. * Using LGS chipset it uses ECR register, but
  1349. * it doesn't support ECP or FIFO MODE
  1350. */
  1351. if (i == 1024) {
  1352. ECR_WRITE(pb, ECR_SPP << 5);
  1353. return 0;
  1354. }
  1355. priv->fifo_depth = i;
  1356. if (verbose_probing)
  1357. printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
  1358. /* Find out writeIntrThreshold */
  1359. frob_econtrol(pb, 1<<2, 1<<2);
  1360. frob_econtrol(pb, 1<<2, 0);
  1361. for (i = 1; i <= priv->fifo_depth; i++) {
  1362. inb(FIFO(pb));
  1363. udelay(50);
  1364. if (inb(ECONTROL(pb)) & (1<<2))
  1365. break;
  1366. }
  1367. if (i <= priv->fifo_depth) {
  1368. if (verbose_probing)
  1369. printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
  1370. pb->base, i);
  1371. } else
  1372. /* Number of bytes we know we can write if we get an
  1373. interrupt. */
  1374. i = 0;
  1375. priv->writeIntrThreshold = i;
  1376. /* Find out readIntrThreshold */
  1377. frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
  1378. parport_pc_data_reverse(pb); /* Must be in PS2 mode */
  1379. frob_set_mode(pb, ECR_TST); /* Test FIFO */
  1380. frob_econtrol(pb, 1<<2, 1<<2);
  1381. frob_econtrol(pb, 1<<2, 0);
  1382. for (i = 1; i <= priv->fifo_depth; i++) {
  1383. outb(0xaa, FIFO(pb));
  1384. if (inb(ECONTROL(pb)) & (1<<2))
  1385. break;
  1386. }
  1387. if (i <= priv->fifo_depth) {
  1388. if (verbose_probing)
  1389. pr_info("0x%lx: readIntrThreshold is %d\n",
  1390. pb->base, i);
  1391. } else
  1392. /* Number of bytes we can read if we get an interrupt. */
  1393. i = 0;
  1394. priv->readIntrThreshold = i;
  1395. ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
  1396. ECR_WRITE(pb, 0xf4); /* Configuration mode */
  1397. config = inb(CONFIGA(pb));
  1398. pword = (config >> 4) & 0x7;
  1399. switch (pword) {
  1400. case 0:
  1401. pword = 2;
  1402. pr_warn("0x%lx: Unsupported pword size!\n", pb->base);
  1403. break;
  1404. case 2:
  1405. pword = 4;
  1406. pr_warn("0x%lx: Unsupported pword size!\n", pb->base);
  1407. break;
  1408. default:
  1409. pr_warn("0x%lx: Unknown implementation ID\n", pb->base);
  1410. fallthrough; /* Assume 1 */
  1411. case 1:
  1412. pword = 1;
  1413. }
  1414. priv->pword = pword;
  1415. if (verbose_probing) {
  1416. printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
  1417. pb->base, 8 * pword);
  1418. printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n",
  1419. pb->base, config & 0x80 ? "Level" : "Pulses");
  1420. configb = inb(CONFIGB(pb));
  1421. printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
  1422. pb->base, config, configb);
  1423. printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
  1424. if ((configb >> 3) & 0x07)
  1425. pr_cont("%d", intrline[(configb >> 3) & 0x07]);
  1426. else
  1427. pr_cont("<none or set by other means>");
  1428. pr_cont(" dma=");
  1429. if ((configb & 0x03) == 0x00)
  1430. pr_cont("<none or set by other means>\n");
  1431. else
  1432. pr_cont("%d\n", configb & 0x07);
  1433. }
  1434. /* Go back to mode 000 */
  1435. frob_set_mode(pb, ECR_SPP);
  1436. return 1;
  1437. }
  1438. #endif
  1439. #ifdef CONFIG_X86_32
  1440. static int intel_bug_present_check_epp(struct parport *pb)
  1441. {
  1442. const struct parport_pc_private *priv = pb->private_data;
  1443. int bug_present = 0;
  1444. if (priv->ecr) {
  1445. /* store value of ECR */
  1446. unsigned char ecr = inb(ECONTROL(pb));
  1447. unsigned char i;
  1448. for (i = 0x00; i < 0x80; i += 0x20) {
  1449. ECR_WRITE(pb, i);
  1450. if (clear_epp_timeout(pb)) {
  1451. /* Phony EPP in ECP. */
  1452. bug_present = 1;
  1453. break;
  1454. }
  1455. }
  1456. /* return ECR into the inital state */
  1457. ECR_WRITE(pb, ecr);
  1458. }
  1459. return bug_present;
  1460. }
  1461. static int intel_bug_present(struct parport *pb)
  1462. {
  1463. /* Check whether the device is legacy, not PCI or PCMCIA. Only legacy is known to be affected. */
  1464. if (pb->dev != NULL) {
  1465. return 0;
  1466. }
  1467. return intel_bug_present_check_epp(pb);
  1468. }
  1469. #else
  1470. static int intel_bug_present(struct parport *pb)
  1471. {
  1472. return 0;
  1473. }
  1474. #endif /* CONFIG_X86_32 */
  1475. static int parport_ECPPS2_supported(struct parport *pb)
  1476. {
  1477. const struct parport_pc_private *priv = pb->private_data;
  1478. int result;
  1479. unsigned char oecr;
  1480. if (!priv->ecr)
  1481. return 0;
  1482. oecr = inb(ECONTROL(pb));
  1483. ECR_WRITE(pb, ECR_PS2 << 5);
  1484. result = parport_PS2_supported(pb);
  1485. ECR_WRITE(pb, oecr);
  1486. return result;
  1487. }
  1488. /* EPP mode detection */
  1489. static int parport_EPP_supported(struct parport *pb)
  1490. {
  1491. /*
  1492. * Theory:
  1493. * Bit 0 of STR is the EPP timeout bit, this bit is 0
  1494. * when EPP is possible and is set high when an EPP timeout
  1495. * occurs (EPP uses the HALT line to stop the CPU while it does
  1496. * the byte transfer, an EPP timeout occurs if the attached
  1497. * device fails to respond after 10 micro seconds).
  1498. *
  1499. * This bit is cleared by either reading it (National Semi)
  1500. * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
  1501. * This bit is always high in non EPP modes.
  1502. */
  1503. /* If EPP timeout bit clear then EPP available */
  1504. if (!clear_epp_timeout(pb))
  1505. return 0; /* No way to clear timeout */
  1506. /* Check for Intel bug. */
  1507. if (intel_bug_present(pb))
  1508. return 0;
  1509. pb->modes |= PARPORT_MODE_EPP;
  1510. /* Set up access functions to use EPP hardware. */
  1511. pb->ops->epp_read_data = parport_pc_epp_read_data;
  1512. pb->ops->epp_write_data = parport_pc_epp_write_data;
  1513. pb->ops->epp_read_addr = parport_pc_epp_read_addr;
  1514. pb->ops->epp_write_addr = parport_pc_epp_write_addr;
  1515. return 1;
  1516. }
  1517. static int parport_ECPEPP_supported(struct parport *pb)
  1518. {
  1519. struct parport_pc_private *priv = pb->private_data;
  1520. int result;
  1521. unsigned char oecr;
  1522. if (!priv->ecr)
  1523. return 0;
  1524. oecr = inb(ECONTROL(pb));
  1525. /* Search for SMC style EPP+ECP mode */
  1526. ECR_WRITE(pb, 0x80);
  1527. outb(0x04, CONTROL(pb));
  1528. result = parport_EPP_supported(pb);
  1529. ECR_WRITE(pb, oecr);
  1530. if (result) {
  1531. /* Set up access functions to use ECP+EPP hardware. */
  1532. pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
  1533. pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
  1534. pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
  1535. pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
  1536. }
  1537. return result;
  1538. }
  1539. #else /* No IEEE 1284 support */
  1540. /* Don't bother probing for modes we know we won't use. */
  1541. static int parport_PS2_supported(struct parport *pb) { return 0; }
  1542. #ifdef CONFIG_PARPORT_PC_FIFO
  1543. static int parport_ECP_supported(struct parport *pb)
  1544. {
  1545. return 0;
  1546. }
  1547. #endif
  1548. static int parport_EPP_supported(struct parport *pb)
  1549. {
  1550. return 0;
  1551. }
  1552. static int parport_ECPEPP_supported(struct parport *pb)
  1553. {
  1554. return 0;
  1555. }
  1556. static int parport_ECPPS2_supported(struct parport *pb)
  1557. {
  1558. return 0;
  1559. }
  1560. #endif /* No IEEE 1284 support */
  1561. /* --- IRQ detection -------------------------------------- */
  1562. /* Only if supports ECP mode */
  1563. static int programmable_irq_support(struct parport *pb)
  1564. {
  1565. int irq, intrLine;
  1566. unsigned char oecr = inb(ECONTROL(pb));
  1567. static const int lookup[8] = {
  1568. PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
  1569. };
  1570. ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
  1571. intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
  1572. irq = lookup[intrLine];
  1573. ECR_WRITE(pb, oecr);
  1574. return irq;
  1575. }
  1576. static int irq_probe_ECP(struct parport *pb)
  1577. {
  1578. int i;
  1579. unsigned long irqs;
  1580. irqs = probe_irq_on();
  1581. ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
  1582. ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
  1583. ECR_WRITE(pb, ECR_TST << 5);
  1584. /* If Full FIFO sure that writeIntrThreshold is generated */
  1585. for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
  1586. outb(0xaa, FIFO(pb));
  1587. pb->irq = probe_irq_off(irqs);
  1588. ECR_WRITE(pb, ECR_SPP << 5);
  1589. if (pb->irq <= 0)
  1590. pb->irq = PARPORT_IRQ_NONE;
  1591. return pb->irq;
  1592. }
  1593. /*
  1594. * This detection seems that only works in National Semiconductors
  1595. * This doesn't work in SMC, LGS, and Winbond
  1596. */
  1597. static int irq_probe_EPP(struct parport *pb)
  1598. {
  1599. #ifndef ADVANCED_DETECT
  1600. return PARPORT_IRQ_NONE;
  1601. #else
  1602. int irqs;
  1603. unsigned char oecr;
  1604. if (pb->modes & PARPORT_MODE_PCECR)
  1605. oecr = inb(ECONTROL(pb));
  1606. irqs = probe_irq_on();
  1607. if (pb->modes & PARPORT_MODE_PCECR)
  1608. frob_econtrol(pb, 0x10, 0x10);
  1609. clear_epp_timeout(pb);
  1610. parport_pc_frob_control(pb, 0x20, 0x20);
  1611. parport_pc_frob_control(pb, 0x10, 0x10);
  1612. clear_epp_timeout(pb);
  1613. /* Device isn't expecting an EPP read
  1614. * and generates an IRQ.
  1615. */
  1616. parport_pc_read_epp(pb);
  1617. udelay(20);
  1618. pb->irq = probe_irq_off(irqs);
  1619. if (pb->modes & PARPORT_MODE_PCECR)
  1620. ECR_WRITE(pb, oecr);
  1621. parport_pc_write_control(pb, 0xc);
  1622. if (pb->irq <= 0)
  1623. pb->irq = PARPORT_IRQ_NONE;
  1624. return pb->irq;
  1625. #endif /* Advanced detection */
  1626. }
  1627. static int irq_probe_SPP(struct parport *pb)
  1628. {
  1629. /* Don't even try to do this. */
  1630. return PARPORT_IRQ_NONE;
  1631. }
  1632. /* We will attempt to share interrupt requests since other devices
  1633. * such as sound cards and network cards seem to like using the
  1634. * printer IRQs.
  1635. *
  1636. * When ECP is available we can autoprobe for IRQs.
  1637. * NOTE: If we can autoprobe it, we can register the IRQ.
  1638. */
  1639. static int parport_irq_probe(struct parport *pb)
  1640. {
  1641. struct parport_pc_private *priv = pb->private_data;
  1642. if (priv->ecr) {
  1643. pb->irq = programmable_irq_support(pb);
  1644. if (pb->irq == PARPORT_IRQ_NONE)
  1645. pb->irq = irq_probe_ECP(pb);
  1646. }
  1647. if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
  1648. (pb->modes & PARPORT_MODE_EPP))
  1649. pb->irq = irq_probe_EPP(pb);
  1650. clear_epp_timeout(pb);
  1651. if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
  1652. pb->irq = irq_probe_EPP(pb);
  1653. clear_epp_timeout(pb);
  1654. if (pb->irq == PARPORT_IRQ_NONE)
  1655. pb->irq = irq_probe_SPP(pb);
  1656. if (pb->irq == PARPORT_IRQ_NONE)
  1657. pb->irq = get_superio_irq(pb);
  1658. return pb->irq;
  1659. }
  1660. /* --- DMA detection -------------------------------------- */
  1661. /* Only if chipset conforms to ECP ISA Interface Standard */
  1662. static int programmable_dma_support(struct parport *p)
  1663. {
  1664. unsigned char oecr = inb(ECONTROL(p));
  1665. int dma;
  1666. frob_set_mode(p, ECR_CNF);
  1667. dma = inb(CONFIGB(p)) & 0x07;
  1668. /* 000: Indicates jumpered 8-bit DMA if read-only.
  1669. 100: Indicates jumpered 16-bit DMA if read-only. */
  1670. if ((dma & 0x03) == 0)
  1671. dma = PARPORT_DMA_NONE;
  1672. ECR_WRITE(p, oecr);
  1673. return dma;
  1674. }
  1675. static int parport_dma_probe(struct parport *p)
  1676. {
  1677. const struct parport_pc_private *priv = p->private_data;
  1678. if (priv->ecr) /* ask ECP chipset first */
  1679. p->dma = programmable_dma_support(p);
  1680. if (p->dma == PARPORT_DMA_NONE) {
  1681. /* ask known Super-IO chips proper, although these
  1682. claim ECP compatible, some don't report their DMA
  1683. conforming to ECP standards */
  1684. p->dma = get_superio_dma(p);
  1685. }
  1686. return p->dma;
  1687. }
  1688. /* --- Initialisation code -------------------------------- */
  1689. static LIST_HEAD(ports_list);
  1690. static DEFINE_SPINLOCK(ports_lock);
  1691. struct parport *parport_pc_probe_port(unsigned long int base,
  1692. unsigned long int base_hi,
  1693. int irq, int dma,
  1694. struct device *dev,
  1695. int irqflags)
  1696. {
  1697. struct parport_pc_private *priv;
  1698. struct parport_operations *ops;
  1699. struct parport *p;
  1700. int probedirq = PARPORT_IRQ_NONE;
  1701. struct resource *base_res;
  1702. struct resource *ECR_res = NULL;
  1703. struct resource *EPP_res = NULL;
  1704. struct platform_device *pdev = NULL;
  1705. int ret;
  1706. if (!dev) {
  1707. /* We need a physical device to attach to, but none was
  1708. * provided. Create our own. */
  1709. pdev = platform_device_register_simple("parport_pc",
  1710. base, NULL, 0);
  1711. if (IS_ERR(pdev))
  1712. return NULL;
  1713. dev = &pdev->dev;
  1714. ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(24));
  1715. if (ret) {
  1716. dev_err(dev, "Unable to set coherent dma mask: disabling DMA\n");
  1717. dma = PARPORT_DMA_NONE;
  1718. }
  1719. }
  1720. ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
  1721. if (!ops)
  1722. goto out1;
  1723. priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
  1724. if (!priv)
  1725. goto out2;
  1726. /* a misnomer, actually - it's allocate and reserve parport number */
  1727. p = parport_register_port(base, irq, dma, ops);
  1728. if (!p)
  1729. goto out3;
  1730. base_res = request_region(base, 3, p->name);
  1731. if (!base_res)
  1732. goto out4;
  1733. memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
  1734. priv->ctr = 0xc;
  1735. priv->ctr_writable = ~0x10;
  1736. priv->ecr = 0;
  1737. priv->fifo_depth = 0;
  1738. priv->dma_buf = NULL;
  1739. priv->dma_handle = 0;
  1740. INIT_LIST_HEAD(&priv->list);
  1741. priv->port = p;
  1742. p->dev = dev;
  1743. p->base_hi = base_hi;
  1744. p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
  1745. p->private_data = priv;
  1746. if (base_hi) {
  1747. ECR_res = request_region(base_hi, 3, p->name);
  1748. if (ECR_res)
  1749. parport_ECR_present(p);
  1750. }
  1751. if (base != 0x3bc) {
  1752. EPP_res = request_region(base+0x3, 5, p->name);
  1753. if (EPP_res)
  1754. if (!parport_EPP_supported(p))
  1755. parport_ECPEPP_supported(p);
  1756. }
  1757. if (!parport_SPP_supported(p))
  1758. /* No port. */
  1759. goto out5;
  1760. if (priv->ecr)
  1761. parport_ECPPS2_supported(p);
  1762. else
  1763. parport_PS2_supported(p);
  1764. p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
  1765. pr_info("%s: PC-style at 0x%lx", p->name, p->base);
  1766. if (p->base_hi && priv->ecr)
  1767. pr_cont(" (0x%lx)", p->base_hi);
  1768. if (p->irq == PARPORT_IRQ_AUTO) {
  1769. p->irq = PARPORT_IRQ_NONE;
  1770. parport_irq_probe(p);
  1771. } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
  1772. p->irq = PARPORT_IRQ_NONE;
  1773. parport_irq_probe(p);
  1774. probedirq = p->irq;
  1775. p->irq = PARPORT_IRQ_NONE;
  1776. }
  1777. if (p->irq != PARPORT_IRQ_NONE) {
  1778. pr_cont(", irq %d", p->irq);
  1779. priv->ctr_writable |= 0x10;
  1780. if (p->dma == PARPORT_DMA_AUTO) {
  1781. p->dma = PARPORT_DMA_NONE;
  1782. parport_dma_probe(p);
  1783. }
  1784. }
  1785. if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
  1786. is mandatory (see above) */
  1787. p->dma = PARPORT_DMA_NONE;
  1788. #ifdef CONFIG_PARPORT_PC_FIFO
  1789. if (parport_ECP_supported(p) &&
  1790. p->dma != PARPORT_DMA_NOFIFO &&
  1791. priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
  1792. p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
  1793. p->ops->compat_write_data = parport_pc_compat_write_block_pio;
  1794. #ifdef CONFIG_PARPORT_1284
  1795. p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
  1796. /* currently broken, but working on it.. (FB) */
  1797. /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
  1798. #endif /* IEEE 1284 support */
  1799. if (p->dma != PARPORT_DMA_NONE) {
  1800. pr_cont(", dma %d", p->dma);
  1801. p->modes |= PARPORT_MODE_DMA;
  1802. } else
  1803. pr_cont(", using FIFO");
  1804. } else
  1805. /* We can't use the DMA channel after all. */
  1806. p->dma = PARPORT_DMA_NONE;
  1807. #endif /* Allowed to use FIFO/DMA */
  1808. pr_cont(" [");
  1809. #define printmode(x) \
  1810. do { \
  1811. if (p->modes & PARPORT_MODE_##x) \
  1812. pr_cont("%s%s", f++ ? "," : "", #x); \
  1813. } while (0)
  1814. {
  1815. int f = 0;
  1816. printmode(PCSPP);
  1817. printmode(TRISTATE);
  1818. printmode(COMPAT);
  1819. printmode(EPP);
  1820. printmode(ECP);
  1821. printmode(DMA);
  1822. }
  1823. #undef printmode
  1824. #ifndef CONFIG_PARPORT_1284
  1825. pr_cont("(,...)");
  1826. #endif /* CONFIG_PARPORT_1284 */
  1827. pr_cont("]\n");
  1828. if (probedirq != PARPORT_IRQ_NONE)
  1829. pr_info("%s: irq %d detected\n", p->name, probedirq);
  1830. /* If No ECP release the ports grabbed above. */
  1831. if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
  1832. release_region(base_hi, 3);
  1833. ECR_res = NULL;
  1834. }
  1835. /* Likewise for EEP ports */
  1836. if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
  1837. release_region(base+3, 5);
  1838. EPP_res = NULL;
  1839. }
  1840. if (p->irq != PARPORT_IRQ_NONE) {
  1841. if (request_irq(p->irq, parport_irq_handler,
  1842. irqflags, p->name, p)) {
  1843. pr_warn("%s: irq %d in use, resorting to polled operation\n",
  1844. p->name, p->irq);
  1845. p->irq = PARPORT_IRQ_NONE;
  1846. p->dma = PARPORT_DMA_NONE;
  1847. }
  1848. #ifdef CONFIG_PARPORT_PC_FIFO
  1849. #ifdef HAS_DMA
  1850. if (p->dma != PARPORT_DMA_NONE) {
  1851. if (request_dma(p->dma, p->name)) {
  1852. pr_warn("%s: dma %d in use, resorting to PIO operation\n",
  1853. p->name, p->dma);
  1854. p->dma = PARPORT_DMA_NONE;
  1855. } else {
  1856. priv->dma_buf =
  1857. dma_alloc_coherent(dev,
  1858. PAGE_SIZE,
  1859. &priv->dma_handle,
  1860. GFP_KERNEL);
  1861. if (!priv->dma_buf) {
  1862. pr_warn("%s: cannot get buffer for DMA, resorting to PIO operation\n",
  1863. p->name);
  1864. free_dma(p->dma);
  1865. p->dma = PARPORT_DMA_NONE;
  1866. }
  1867. }
  1868. }
  1869. #endif
  1870. #endif
  1871. }
  1872. /* Done probing. Now put the port into a sensible start-up state. */
  1873. if (priv->ecr)
  1874. /*
  1875. * Put the ECP detected port in PS2 mode.
  1876. * Do this also for ports that have ECR but don't do ECP.
  1877. */
  1878. ECR_WRITE(p, 0x34);
  1879. parport_pc_write_data(p, 0);
  1880. parport_pc_data_forward(p);
  1881. /* Now that we've told the sharing engine about the port, and
  1882. found out its characteristics, let the high-level drivers
  1883. know about it. */
  1884. spin_lock(&ports_lock);
  1885. list_add(&priv->list, &ports_list);
  1886. spin_unlock(&ports_lock);
  1887. parport_announce_port(p);
  1888. return p;
  1889. out5:
  1890. if (ECR_res)
  1891. release_region(base_hi, 3);
  1892. if (EPP_res)
  1893. release_region(base+0x3, 5);
  1894. release_region(base, 3);
  1895. out4:
  1896. parport_del_port(p);
  1897. out3:
  1898. kfree(priv);
  1899. out2:
  1900. kfree(ops);
  1901. out1:
  1902. if (pdev)
  1903. platform_device_unregister(pdev);
  1904. return NULL;
  1905. }
  1906. EXPORT_SYMBOL(parport_pc_probe_port);
  1907. void parport_pc_unregister_port(struct parport *p)
  1908. {
  1909. struct parport_pc_private *priv = p->private_data;
  1910. struct parport_operations *ops = p->ops;
  1911. parport_remove_port(p);
  1912. spin_lock(&ports_lock);
  1913. list_del_init(&priv->list);
  1914. spin_unlock(&ports_lock);
  1915. #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
  1916. if (p->dma != PARPORT_DMA_NONE)
  1917. free_dma(p->dma);
  1918. #endif
  1919. if (p->irq != PARPORT_IRQ_NONE)
  1920. free_irq(p->irq, p);
  1921. release_region(p->base, 3);
  1922. if (p->size > 3)
  1923. release_region(p->base + 3, p->size - 3);
  1924. if (p->modes & PARPORT_MODE_ECP)
  1925. release_region(p->base_hi, 3);
  1926. #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
  1927. if (priv->dma_buf)
  1928. dma_free_coherent(p->physport->dev, PAGE_SIZE,
  1929. priv->dma_buf,
  1930. priv->dma_handle);
  1931. #endif
  1932. kfree(p->private_data);
  1933. parport_del_port(p);
  1934. kfree(ops); /* hope no-one cached it */
  1935. }
  1936. EXPORT_SYMBOL(parport_pc_unregister_port);
  1937. #ifdef CONFIG_PCI
  1938. /* ITE support maintained by Rich Liu <[email protected]> */
  1939. static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma,
  1940. const struct parport_pc_via_data *via)
  1941. {
  1942. short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
  1943. u32 ite8872set;
  1944. u32 ite8872_lpt, ite8872_lpthi;
  1945. u8 ite8872_irq, type;
  1946. int irq;
  1947. int i;
  1948. pr_debug("sio_ite_8872_probe()\n");
  1949. /* make sure which one chip */
  1950. for (i = 0; i < 5; i++) {
  1951. if (request_region(inta_addr[i], 32, "it887x")) {
  1952. int test;
  1953. pci_write_config_dword(pdev, 0x60,
  1954. 0xe5000000 | inta_addr[i]);
  1955. pci_write_config_dword(pdev, 0x78,
  1956. 0x00000000 | inta_addr[i]);
  1957. test = inb(inta_addr[i]);
  1958. if (test != 0xff)
  1959. break;
  1960. release_region(inta_addr[i], 32);
  1961. }
  1962. }
  1963. if (i >= 5) {
  1964. pr_info("parport_pc: cannot find ITE8872 INTA\n");
  1965. return 0;
  1966. }
  1967. type = inb(inta_addr[i] + 0x18);
  1968. type &= 0x0f;
  1969. switch (type) {
  1970. case 0x2:
  1971. pr_info("parport_pc: ITE8871 found (1P)\n");
  1972. ite8872set = 0x64200000;
  1973. break;
  1974. case 0xa:
  1975. pr_info("parport_pc: ITE8875 found (1P)\n");
  1976. ite8872set = 0x64200000;
  1977. break;
  1978. case 0xe:
  1979. pr_info("parport_pc: ITE8872 found (2S1P)\n");
  1980. ite8872set = 0x64e00000;
  1981. break;
  1982. case 0x6:
  1983. pr_info("parport_pc: ITE8873 found (1S)\n");
  1984. release_region(inta_addr[i], 32);
  1985. return 0;
  1986. case 0x8:
  1987. pr_info("parport_pc: ITE8874 found (2S)\n");
  1988. release_region(inta_addr[i], 32);
  1989. return 0;
  1990. default:
  1991. pr_info("parport_pc: unknown ITE887x\n");
  1992. pr_info("parport_pc: please mail 'lspci -nvv' output to [email protected]\n");
  1993. release_region(inta_addr[i], 32);
  1994. return 0;
  1995. }
  1996. pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
  1997. pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
  1998. ite8872_lpt &= 0x0000ff00;
  1999. pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
  2000. ite8872_lpthi &= 0x0000ff00;
  2001. pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
  2002. pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
  2003. pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
  2004. /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
  2005. /* SET Parallel IRQ */
  2006. pci_write_config_dword(pdev, 0x9c,
  2007. ite8872set | (ite8872_irq * 0x11111));
  2008. pr_debug("ITE887x: The IRQ is %d\n", ite8872_irq);
  2009. pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt);
  2010. pr_debug("ITE887x: The PARALLEL I/O porthi is 0x%x\n", ite8872_lpthi);
  2011. /* Let the user (or defaults) steer us away from interrupts */
  2012. irq = ite8872_irq;
  2013. if (autoirq != PARPORT_IRQ_AUTO)
  2014. irq = PARPORT_IRQ_NONE;
  2015. /*
  2016. * Release the resource so that parport_pc_probe_port can get it.
  2017. */
  2018. release_region(inta_addr[i], 32);
  2019. if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
  2020. irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
  2021. pr_info("parport_pc: ITE 8872 parallel port: io=0x%X",
  2022. ite8872_lpt);
  2023. if (irq != PARPORT_IRQ_NONE)
  2024. pr_cont(", irq=%d", irq);
  2025. pr_cont("\n");
  2026. return 1;
  2027. }
  2028. return 0;
  2029. }
  2030. /* VIA 8231 support by Pavel Fedin <[email protected]>
  2031. based on VIA 686a support code by Jeff Garzik <[email protected]> */
  2032. static int parport_init_mode;
  2033. /* Data for two known VIA chips */
  2034. static struct parport_pc_via_data via_686a_data = {
  2035. 0x51,
  2036. 0x50,
  2037. 0x85,
  2038. 0x02,
  2039. 0xE2,
  2040. 0xF0,
  2041. 0xE6
  2042. };
  2043. static struct parport_pc_via_data via_8231_data = {
  2044. 0x45,
  2045. 0x44,
  2046. 0x50,
  2047. 0x04,
  2048. 0xF2,
  2049. 0xFA,
  2050. 0xF6
  2051. };
  2052. static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma,
  2053. const struct parport_pc_via_data *via)
  2054. {
  2055. u8 tmp, tmp2, siofunc;
  2056. u8 ppcontrol = 0;
  2057. int dma, irq;
  2058. unsigned port1, port2;
  2059. unsigned have_epp = 0;
  2060. printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
  2061. switch (parport_init_mode) {
  2062. case 1:
  2063. printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
  2064. siofunc = VIA_FUNCTION_PARPORT_SPP;
  2065. break;
  2066. case 2:
  2067. printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
  2068. siofunc = VIA_FUNCTION_PARPORT_SPP;
  2069. ppcontrol = VIA_PARPORT_BIDIR;
  2070. break;
  2071. case 3:
  2072. printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
  2073. siofunc = VIA_FUNCTION_PARPORT_EPP;
  2074. ppcontrol = VIA_PARPORT_BIDIR;
  2075. have_epp = 1;
  2076. break;
  2077. case 4:
  2078. printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
  2079. siofunc = VIA_FUNCTION_PARPORT_ECP;
  2080. ppcontrol = VIA_PARPORT_BIDIR;
  2081. break;
  2082. case 5:
  2083. printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
  2084. siofunc = VIA_FUNCTION_PARPORT_ECP;
  2085. ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
  2086. have_epp = 1;
  2087. break;
  2088. default:
  2089. printk(KERN_DEBUG "parport_pc: probing current configuration\n");
  2090. siofunc = VIA_FUNCTION_PROBE;
  2091. break;
  2092. }
  2093. /*
  2094. * unlock super i/o configuration
  2095. */
  2096. pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
  2097. tmp |= via->via_pci_superio_config_data;
  2098. pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
  2099. /* Bits 1-0: Parallel Port Mode / Enable */
  2100. outb(via->viacfg_function, VIA_CONFIG_INDEX);
  2101. tmp = inb(VIA_CONFIG_DATA);
  2102. /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
  2103. outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
  2104. tmp2 = inb(VIA_CONFIG_DATA);
  2105. if (siofunc == VIA_FUNCTION_PROBE) {
  2106. siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
  2107. ppcontrol = tmp2;
  2108. } else {
  2109. tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
  2110. tmp |= siofunc;
  2111. outb(via->viacfg_function, VIA_CONFIG_INDEX);
  2112. outb(tmp, VIA_CONFIG_DATA);
  2113. tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
  2114. tmp2 |= ppcontrol;
  2115. outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
  2116. outb(tmp2, VIA_CONFIG_DATA);
  2117. }
  2118. /* Parallel Port I/O Base Address, bits 9-2 */
  2119. outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
  2120. port1 = inb(VIA_CONFIG_DATA) << 2;
  2121. printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
  2122. port1);
  2123. if (port1 == 0x3BC && have_epp) {
  2124. outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
  2125. outb((0x378 >> 2), VIA_CONFIG_DATA);
  2126. printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
  2127. port1 = 0x378;
  2128. }
  2129. /*
  2130. * lock super i/o configuration
  2131. */
  2132. pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
  2133. tmp &= ~via->via_pci_superio_config_data;
  2134. pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
  2135. if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
  2136. pr_info("parport_pc: VIA parallel port disabled in BIOS\n");
  2137. return 0;
  2138. }
  2139. /* Bits 7-4: PnP Routing for Parallel Port IRQ */
  2140. pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
  2141. irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
  2142. if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
  2143. /* Bits 3-2: PnP Routing for Parallel Port DMA */
  2144. pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
  2145. dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
  2146. } else
  2147. /* if ECP not enabled, DMA is not enabled, assumed
  2148. bogus 'dma' value */
  2149. dma = PARPORT_DMA_NONE;
  2150. /* Let the user (or defaults) steer us away from interrupts and DMA */
  2151. if (autoirq == PARPORT_IRQ_NONE) {
  2152. irq = PARPORT_IRQ_NONE;
  2153. dma = PARPORT_DMA_NONE;
  2154. }
  2155. if (autodma == PARPORT_DMA_NONE)
  2156. dma = PARPORT_DMA_NONE;
  2157. switch (port1) {
  2158. case 0x3bc:
  2159. port2 = 0x7bc; break;
  2160. case 0x378:
  2161. port2 = 0x778; break;
  2162. case 0x278:
  2163. port2 = 0x678; break;
  2164. default:
  2165. pr_info("parport_pc: Weird VIA parport base 0x%X, ignoring\n",
  2166. port1);
  2167. return 0;
  2168. }
  2169. /* filter bogus IRQs */
  2170. switch (irq) {
  2171. case 0:
  2172. case 2:
  2173. case 8:
  2174. case 13:
  2175. irq = PARPORT_IRQ_NONE;
  2176. break;
  2177. default: /* do nothing */
  2178. break;
  2179. }
  2180. /* finally, do the probe with values obtained */
  2181. if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
  2182. pr_info("parport_pc: VIA parallel port: io=0x%X", port1);
  2183. if (irq != PARPORT_IRQ_NONE)
  2184. pr_cont(", irq=%d", irq);
  2185. if (dma != PARPORT_DMA_NONE)
  2186. pr_cont(", dma=%d", dma);
  2187. pr_cont("\n");
  2188. return 1;
  2189. }
  2190. pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
  2191. port1, irq, dma);
  2192. return 0;
  2193. }
  2194. enum parport_pc_sio_types {
  2195. sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
  2196. sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
  2197. sio_ite_8872,
  2198. last_sio
  2199. };
  2200. /* each element directly indexed from enum list, above */
  2201. static struct parport_pc_superio {
  2202. int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
  2203. const struct parport_pc_via_data *via);
  2204. const struct parport_pc_via_data *via;
  2205. } parport_pc_superio_info[] = {
  2206. { sio_via_probe, &via_686a_data, },
  2207. { sio_via_probe, &via_8231_data, },
  2208. { sio_ite_8872_probe, NULL, },
  2209. };
  2210. enum parport_pc_pci_cards {
  2211. siig_1p_10x = last_sio,
  2212. siig_2p_10x,
  2213. siig_1p_20x,
  2214. siig_2p_20x,
  2215. lava_parallel,
  2216. lava_parallel_dual_a,
  2217. lava_parallel_dual_b,
  2218. boca_ioppar,
  2219. plx_9050,
  2220. timedia_4006a,
  2221. timedia_4014,
  2222. timedia_4008a,
  2223. timedia_4018,
  2224. timedia_9018a,
  2225. syba_2p_epp,
  2226. syba_1p_ecp,
  2227. titan_010l,
  2228. avlab_1p,
  2229. avlab_2p,
  2230. oxsemi_952,
  2231. oxsemi_954,
  2232. oxsemi_840,
  2233. oxsemi_pcie_pport,
  2234. aks_0100,
  2235. mobility_pp,
  2236. netmos_9900,
  2237. netmos_9705,
  2238. netmos_9715,
  2239. netmos_9755,
  2240. netmos_9805,
  2241. netmos_9815,
  2242. netmos_9901,
  2243. netmos_9865,
  2244. quatech_sppxp100,
  2245. wch_ch382l,
  2246. brainboxes_uc146,
  2247. brainboxes_px203,
  2248. };
  2249. /* each element directly indexed from enum list, above
  2250. * (but offset by last_sio) */
  2251. static struct parport_pc_pci {
  2252. int numports;
  2253. struct { /* BAR (base address registers) numbers in the config
  2254. space header */
  2255. int lo;
  2256. int hi;
  2257. /* -1 if not there, >6 for offset-method (max BAR is 6) */
  2258. } addr[4];
  2259. /* If set, this is called immediately after pci_enable_device.
  2260. * If it returns non-zero, no probing will take place and the
  2261. * ports will not be used. */
  2262. int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
  2263. /* If set, this is called after probing for ports. If 'failed'
  2264. * is non-zero we couldn't use any of the ports. */
  2265. void (*postinit_hook) (struct pci_dev *pdev, int failed);
  2266. } cards[] = {
  2267. /* siig_1p_10x */ { 1, { { 2, 3 }, } },
  2268. /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
  2269. /* siig_1p_20x */ { 1, { { 0, 1 }, } },
  2270. /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
  2271. /* lava_parallel */ { 1, { { 0, -1 }, } },
  2272. /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
  2273. /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
  2274. /* boca_ioppar */ { 1, { { 0, -1 }, } },
  2275. /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
  2276. /* timedia_4006a */ { 1, { { 0, -1 }, } },
  2277. /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
  2278. /* timedia_4008a */ { 1, { { 0, 1 }, } },
  2279. /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
  2280. /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
  2281. /* SYBA uses fixed offsets in
  2282. a 1K io window */
  2283. /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
  2284. /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
  2285. /* titan_010l */ { 1, { { 3, -1 }, } },
  2286. /* avlab_1p */ { 1, { { 0, 1}, } },
  2287. /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
  2288. /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
  2289. * and 840 locks up if you write 1 to bit 2! */
  2290. /* oxsemi_952 */ { 1, { { 0, 1 }, } },
  2291. /* oxsemi_954 */ { 1, { { 0, -1 }, } },
  2292. /* oxsemi_840 */ { 1, { { 0, 1 }, } },
  2293. /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
  2294. /* aks_0100 */ { 1, { { 0, -1 }, } },
  2295. /* mobility_pp */ { 1, { { 0, 1 }, } },
  2296. /* netmos_9900 */ { 1, { { 0, -1 }, } },
  2297. /* The netmos entries below are untested */
  2298. /* netmos_9705 */ { 1, { { 0, -1 }, } },
  2299. /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
  2300. /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
  2301. /* netmos_9805 */ { 1, { { 0, 1 }, } },
  2302. /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } },
  2303. /* netmos_9901 */ { 1, { { 0, -1 }, } },
  2304. /* netmos_9865 */ { 1, { { 0, -1 }, } },
  2305. /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
  2306. /* wch_ch382l */ { 1, { { 2, -1 }, } },
  2307. /* brainboxes_uc146 */ { 1, { { 3, -1 }, } },
  2308. /* brainboxes_px203 */ { 1, { { 0, -1 }, } },
  2309. };
  2310. static const struct pci_device_id parport_pc_pci_tbl[] = {
  2311. /* Super-IO onboard chips */
  2312. { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
  2313. { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
  2314. { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
  2315. PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
  2316. /* PCI cards */
  2317. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
  2318. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
  2319. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
  2320. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
  2321. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
  2322. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
  2323. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
  2324. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
  2325. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
  2326. PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
  2327. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
  2328. PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
  2329. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
  2330. PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
  2331. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
  2332. PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
  2333. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  2334. PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
  2335. /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
  2336. { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
  2337. { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
  2338. { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
  2339. { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
  2340. { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
  2341. { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
  2342. PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
  2343. { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
  2344. PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
  2345. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
  2346. PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
  2347. /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
  2348. /* AFAVLAB_TK9902 */
  2349. { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
  2350. { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
  2351. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
  2352. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
  2353. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
  2354. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
  2355. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
  2356. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
  2357. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
  2358. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2359. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
  2360. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2361. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
  2362. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2363. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
  2364. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2365. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
  2366. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2367. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
  2368. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2369. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
  2370. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2371. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
  2372. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2373. { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
  2374. PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
  2375. { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
  2376. /* NetMos communication controllers */
  2377. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  2378. 0xA000, 0x2000, 0, 0, netmos_9900 },
  2379. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
  2380. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
  2381. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
  2382. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
  2383. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
  2384. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
  2385. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
  2386. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
  2387. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
  2388. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
  2389. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
  2390. 0xA000, 0x2000, 0, 0, netmos_9901 },
  2391. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
  2392. 0xA000, 0x1000, 0, 0, netmos_9865 },
  2393. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
  2394. 0xA000, 0x2000, 0, 0, netmos_9865 },
  2395. /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
  2396. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
  2397. PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
  2398. /* WCH CH382L PCI-E single parallel port card */
  2399. { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382l },
  2400. /* Brainboxes IX-500/550 */
  2401. { PCI_VENDOR_ID_INTASHIELD, 0x402a,
  2402. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2403. /* Brainboxes UC-146/UC-157 */
  2404. { PCI_VENDOR_ID_INTASHIELD, 0x0be1,
  2405. PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc146 },
  2406. { PCI_VENDOR_ID_INTASHIELD, 0x0be2,
  2407. PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc146 },
  2408. /* Brainboxes PX-146/PX-257 */
  2409. { PCI_VENDOR_ID_INTASHIELD, 0x401c,
  2410. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2411. /* Brainboxes PX-203 */
  2412. { PCI_VENDOR_ID_INTASHIELD, 0x4007,
  2413. PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_px203 },
  2414. /* Brainboxes PX-475 */
  2415. { PCI_VENDOR_ID_INTASHIELD, 0x401f,
  2416. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
  2417. { 0, } /* terminate list */
  2418. };
  2419. MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
  2420. struct pci_parport_data {
  2421. int num;
  2422. struct parport *ports[2];
  2423. };
  2424. static int parport_pc_pci_probe(struct pci_dev *dev,
  2425. const struct pci_device_id *id)
  2426. {
  2427. int err, count, n, i = id->driver_data;
  2428. struct pci_parport_data *data;
  2429. if (i < last_sio)
  2430. /* This is an onboard Super-IO and has already been probed */
  2431. return 0;
  2432. /* This is a PCI card */
  2433. i -= last_sio;
  2434. count = 0;
  2435. err = pci_enable_device(dev);
  2436. if (err)
  2437. return err;
  2438. data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
  2439. if (!data)
  2440. return -ENOMEM;
  2441. if (cards[i].preinit_hook &&
  2442. cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
  2443. kfree(data);
  2444. return -ENODEV;
  2445. }
  2446. for (n = 0; n < cards[i].numports; n++) {
  2447. int lo = cards[i].addr[n].lo;
  2448. int hi = cards[i].addr[n].hi;
  2449. int irq;
  2450. unsigned long io_lo, io_hi;
  2451. io_lo = pci_resource_start(dev, lo);
  2452. io_hi = 0;
  2453. if ((hi >= 0) && (hi <= 6))
  2454. io_hi = pci_resource_start(dev, hi);
  2455. else if (hi > 6)
  2456. io_lo += hi; /* Reinterpret the meaning of
  2457. "hi" as an offset (see SYBA
  2458. def.) */
  2459. /* TODO: test if sharing interrupts works */
  2460. irq = dev->irq;
  2461. if (irq == IRQ_NONE) {
  2462. printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
  2463. id->vendor, id->device, io_lo, io_hi);
  2464. irq = PARPORT_IRQ_NONE;
  2465. } else {
  2466. printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
  2467. id->vendor, id->device, io_lo, io_hi, irq);
  2468. }
  2469. data->ports[count] =
  2470. parport_pc_probe_port(io_lo, io_hi, irq,
  2471. PARPORT_DMA_NONE, &dev->dev,
  2472. IRQF_SHARED);
  2473. if (data->ports[count])
  2474. count++;
  2475. }
  2476. data->num = count;
  2477. if (cards[i].postinit_hook)
  2478. cards[i].postinit_hook(dev, count == 0);
  2479. if (count) {
  2480. pci_set_drvdata(dev, data);
  2481. return 0;
  2482. }
  2483. kfree(data);
  2484. return -ENODEV;
  2485. }
  2486. static void parport_pc_pci_remove(struct pci_dev *dev)
  2487. {
  2488. struct pci_parport_data *data = pci_get_drvdata(dev);
  2489. int i;
  2490. if (data) {
  2491. for (i = data->num - 1; i >= 0; i--)
  2492. parport_pc_unregister_port(data->ports[i]);
  2493. kfree(data);
  2494. }
  2495. }
  2496. static struct pci_driver parport_pc_pci_driver = {
  2497. .name = "parport_pc",
  2498. .id_table = parport_pc_pci_tbl,
  2499. .probe = parport_pc_pci_probe,
  2500. .remove = parport_pc_pci_remove,
  2501. };
  2502. static int __init parport_pc_init_superio(int autoirq, int autodma)
  2503. {
  2504. const struct pci_device_id *id;
  2505. struct pci_dev *pdev = NULL;
  2506. int ret = 0;
  2507. for_each_pci_dev(pdev) {
  2508. id = pci_match_id(parport_pc_pci_tbl, pdev);
  2509. if (id == NULL || id->driver_data >= last_sio)
  2510. continue;
  2511. if (parport_pc_superio_info[id->driver_data].probe(
  2512. pdev, autoirq, autodma,
  2513. parport_pc_superio_info[id->driver_data].via)) {
  2514. ret++;
  2515. }
  2516. }
  2517. return ret; /* number of devices found */
  2518. }
  2519. #else
  2520. static struct pci_driver parport_pc_pci_driver;
  2521. static int __init parport_pc_init_superio(int autoirq, int autodma)
  2522. {
  2523. return 0;
  2524. }
  2525. #endif /* CONFIG_PCI */
  2526. #ifdef CONFIG_PNP
  2527. static const struct pnp_device_id parport_pc_pnp_tbl[] = {
  2528. /* Standard LPT Printer Port */
  2529. {.id = "PNP0400", .driver_data = 0},
  2530. /* ECP Printer Port */
  2531. {.id = "PNP0401", .driver_data = 0},
  2532. { }
  2533. };
  2534. MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
  2535. static int parport_pc_pnp_probe(struct pnp_dev *dev,
  2536. const struct pnp_device_id *id)
  2537. {
  2538. struct parport *pdata;
  2539. unsigned long io_lo, io_hi;
  2540. int dma, irq;
  2541. if (pnp_port_valid(dev, 0) &&
  2542. !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
  2543. io_lo = pnp_port_start(dev, 0);
  2544. } else
  2545. return -EINVAL;
  2546. if (pnp_port_valid(dev, 1) &&
  2547. !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
  2548. io_hi = pnp_port_start(dev, 1);
  2549. } else
  2550. io_hi = 0;
  2551. if (pnp_irq_valid(dev, 0) &&
  2552. !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
  2553. irq = pnp_irq(dev, 0);
  2554. } else
  2555. irq = PARPORT_IRQ_NONE;
  2556. if (pnp_dma_valid(dev, 0) &&
  2557. !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
  2558. dma = pnp_dma(dev, 0);
  2559. } else
  2560. dma = PARPORT_DMA_NONE;
  2561. dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
  2562. pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
  2563. if (pdata == NULL)
  2564. return -ENODEV;
  2565. pnp_set_drvdata(dev, pdata);
  2566. return 0;
  2567. }
  2568. static void parport_pc_pnp_remove(struct pnp_dev *dev)
  2569. {
  2570. struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
  2571. if (!pdata)
  2572. return;
  2573. parport_pc_unregister_port(pdata);
  2574. }
  2575. /* we only need the pnp layer to activate the device, at least for now */
  2576. static struct pnp_driver parport_pc_pnp_driver = {
  2577. .name = "parport_pc",
  2578. .id_table = parport_pc_pnp_tbl,
  2579. .probe = parport_pc_pnp_probe,
  2580. .remove = parport_pc_pnp_remove,
  2581. };
  2582. #else
  2583. static struct pnp_driver parport_pc_pnp_driver;
  2584. #endif /* CONFIG_PNP */
  2585. static int parport_pc_platform_probe(struct platform_device *pdev)
  2586. {
  2587. /* Always succeed, the actual probing is done in
  2588. * parport_pc_probe_port(). */
  2589. return 0;
  2590. }
  2591. static struct platform_driver parport_pc_platform_driver = {
  2592. .driver = {
  2593. .name = "parport_pc",
  2594. },
  2595. .probe = parport_pc_platform_probe,
  2596. };
  2597. /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
  2598. static int __attribute__((unused))
  2599. parport_pc_find_isa_ports(int autoirq, int autodma)
  2600. {
  2601. int count = 0;
  2602. if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
  2603. count++;
  2604. if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
  2605. count++;
  2606. if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
  2607. count++;
  2608. return count;
  2609. }
  2610. /* This function is called by parport_pc_init if the user didn't
  2611. * specify any ports to probe. Its job is to find some ports. Order
  2612. * is important here -- we want ISA ports to be registered first,
  2613. * followed by PCI cards (for least surprise), but before that we want
  2614. * to do chipset-specific tests for some onboard ports that we know
  2615. * about.
  2616. *
  2617. * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
  2618. * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
  2619. */
  2620. static void __init parport_pc_find_ports(int autoirq, int autodma)
  2621. {
  2622. int count = 0, err;
  2623. #ifdef CONFIG_PARPORT_PC_SUPERIO
  2624. detect_and_report_it87();
  2625. detect_and_report_winbond();
  2626. detect_and_report_smsc();
  2627. #endif
  2628. /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
  2629. count += parport_pc_init_superio(autoirq, autodma);
  2630. /* PnP ports, skip detection if SuperIO already found them */
  2631. if (!count) {
  2632. err = pnp_register_driver(&parport_pc_pnp_driver);
  2633. if (!err)
  2634. pnp_registered_parport = 1;
  2635. }
  2636. /* ISA ports and whatever (see asm/parport.h). */
  2637. parport_pc_find_nonpci_ports(autoirq, autodma);
  2638. err = pci_register_driver(&parport_pc_pci_driver);
  2639. if (!err)
  2640. pci_registered_parport = 1;
  2641. }
  2642. /*
  2643. * Piles of crap below pretend to be a parser for module and kernel
  2644. * parameters. Say "thank you" to whoever had come up with that
  2645. * syntax and keep in mind that code below is a cleaned up version.
  2646. */
  2647. static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
  2648. [0 ... PARPORT_PC_MAX_PORTS] = 0
  2649. };
  2650. static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
  2651. [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
  2652. };
  2653. static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
  2654. [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
  2655. };
  2656. static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
  2657. [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
  2658. };
  2659. static int __init parport_parse_param(const char *s, int *val,
  2660. int automatic, int none, int nofifo)
  2661. {
  2662. if (!s)
  2663. return 0;
  2664. if (!strncmp(s, "auto", 4))
  2665. *val = automatic;
  2666. else if (!strncmp(s, "none", 4))
  2667. *val = none;
  2668. else if (nofifo && !strncmp(s, "nofifo", 6))
  2669. *val = nofifo;
  2670. else {
  2671. char *ep;
  2672. unsigned long r = simple_strtoul(s, &ep, 0);
  2673. if (ep != s)
  2674. *val = r;
  2675. else {
  2676. pr_err("parport: bad specifier `%s'\n", s);
  2677. return -1;
  2678. }
  2679. }
  2680. return 0;
  2681. }
  2682. static int __init parport_parse_irq(const char *irqstr, int *val)
  2683. {
  2684. return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
  2685. PARPORT_IRQ_NONE, 0);
  2686. }
  2687. static int __init parport_parse_dma(const char *dmastr, int *val)
  2688. {
  2689. return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
  2690. PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
  2691. }
  2692. #ifdef CONFIG_PCI
  2693. static int __init parport_init_mode_setup(char *str)
  2694. {
  2695. printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n",
  2696. str);
  2697. if (!strcmp(str, "spp"))
  2698. parport_init_mode = 1;
  2699. if (!strcmp(str, "ps2"))
  2700. parport_init_mode = 2;
  2701. if (!strcmp(str, "epp"))
  2702. parport_init_mode = 3;
  2703. if (!strcmp(str, "ecp"))
  2704. parport_init_mode = 4;
  2705. if (!strcmp(str, "ecpepp"))
  2706. parport_init_mode = 5;
  2707. return 1;
  2708. }
  2709. #endif
  2710. #ifdef MODULE
  2711. static char *irq[PARPORT_PC_MAX_PORTS];
  2712. static char *dma[PARPORT_PC_MAX_PORTS];
  2713. MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
  2714. module_param_hw_array(io, int, ioport, NULL, 0);
  2715. MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
  2716. module_param_hw_array(io_hi, int, ioport, NULL, 0);
  2717. MODULE_PARM_DESC(irq, "IRQ line");
  2718. module_param_hw_array(irq, charp, irq, NULL, 0);
  2719. MODULE_PARM_DESC(dma, "DMA channel");
  2720. module_param_hw_array(dma, charp, dma, NULL, 0);
  2721. #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
  2722. (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
  2723. MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
  2724. module_param(verbose_probing, int, 0644);
  2725. #endif
  2726. #ifdef CONFIG_PCI
  2727. static char *init_mode;
  2728. MODULE_PARM_DESC(init_mode,
  2729. "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
  2730. module_param(init_mode, charp, 0);
  2731. #endif
  2732. static int __init parse_parport_params(void)
  2733. {
  2734. unsigned int i;
  2735. int val;
  2736. #ifdef CONFIG_PCI
  2737. if (init_mode)
  2738. parport_init_mode_setup(init_mode);
  2739. #endif
  2740. for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
  2741. if (parport_parse_irq(irq[i], &val))
  2742. return 1;
  2743. irqval[i] = val;
  2744. if (parport_parse_dma(dma[i], &val))
  2745. return 1;
  2746. dmaval[i] = val;
  2747. }
  2748. if (!io[0]) {
  2749. /* The user can make us use any IRQs or DMAs we find. */
  2750. if (irq[0] && !parport_parse_irq(irq[0], &val))
  2751. switch (val) {
  2752. case PARPORT_IRQ_NONE:
  2753. case PARPORT_IRQ_AUTO:
  2754. irqval[0] = val;
  2755. break;
  2756. default:
  2757. pr_warn("parport_pc: irq specified without base address. Use 'io=' to specify one\n");
  2758. }
  2759. if (dma[0] && !parport_parse_dma(dma[0], &val))
  2760. switch (val) {
  2761. case PARPORT_DMA_NONE:
  2762. case PARPORT_DMA_AUTO:
  2763. dmaval[0] = val;
  2764. break;
  2765. default:
  2766. pr_warn("parport_pc: dma specified without base address. Use 'io=' to specify one\n");
  2767. }
  2768. }
  2769. return 0;
  2770. }
  2771. #else
  2772. static int parport_setup_ptr __initdata;
  2773. /*
  2774. * Acceptable parameters:
  2775. *
  2776. * parport=0
  2777. * parport=auto
  2778. * parport=0xBASE[,IRQ[,DMA]]
  2779. *
  2780. * IRQ/DMA may be numeric or 'auto' or 'none'
  2781. */
  2782. static int __init parport_setup(char *str)
  2783. {
  2784. char *endptr;
  2785. char *sep;
  2786. int val;
  2787. if (!str || !*str || (*str == '0' && !*(str+1))) {
  2788. /* Disable parport if "parport=0" in cmdline */
  2789. io[0] = PARPORT_DISABLE;
  2790. return 1;
  2791. }
  2792. if (!strncmp(str, "auto", 4)) {
  2793. irqval[0] = PARPORT_IRQ_AUTO;
  2794. dmaval[0] = PARPORT_DMA_AUTO;
  2795. return 1;
  2796. }
  2797. val = simple_strtoul(str, &endptr, 0);
  2798. if (endptr == str) {
  2799. pr_warn("parport=%s not understood\n", str);
  2800. return 1;
  2801. }
  2802. if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
  2803. pr_err("parport=%s ignored, too many ports\n", str);
  2804. return 1;
  2805. }
  2806. io[parport_setup_ptr] = val;
  2807. irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
  2808. dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
  2809. sep = strchr(str, ',');
  2810. if (sep++) {
  2811. if (parport_parse_irq(sep, &val))
  2812. return 1;
  2813. irqval[parport_setup_ptr] = val;
  2814. sep = strchr(sep, ',');
  2815. if (sep++) {
  2816. if (parport_parse_dma(sep, &val))
  2817. return 1;
  2818. dmaval[parport_setup_ptr] = val;
  2819. }
  2820. }
  2821. parport_setup_ptr++;
  2822. return 1;
  2823. }
  2824. static int __init parse_parport_params(void)
  2825. {
  2826. return io[0] == PARPORT_DISABLE;
  2827. }
  2828. __setup("parport=", parport_setup);
  2829. /*
  2830. * Acceptable parameters:
  2831. *
  2832. * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
  2833. */
  2834. #ifdef CONFIG_PCI
  2835. __setup("parport_init_mode=", parport_init_mode_setup);
  2836. #endif
  2837. #endif
  2838. /* "Parser" ends here */
  2839. static int __init parport_pc_init(void)
  2840. {
  2841. int err;
  2842. if (parse_parport_params())
  2843. return -EINVAL;
  2844. err = platform_driver_register(&parport_pc_platform_driver);
  2845. if (err)
  2846. return err;
  2847. if (io[0]) {
  2848. int i;
  2849. /* Only probe the ports we were given. */
  2850. user_specified = 1;
  2851. for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
  2852. if (!io[i])
  2853. break;
  2854. if (io_hi[i] == PARPORT_IOHI_AUTO)
  2855. io_hi[i] = 0x400 + io[i];
  2856. parport_pc_probe_port(io[i], io_hi[i],
  2857. irqval[i], dmaval[i], NULL, 0);
  2858. }
  2859. } else
  2860. parport_pc_find_ports(irqval[0], dmaval[0]);
  2861. return 0;
  2862. }
  2863. static void __exit parport_pc_exit(void)
  2864. {
  2865. if (pci_registered_parport)
  2866. pci_unregister_driver(&parport_pc_pci_driver);
  2867. if (pnp_registered_parport)
  2868. pnp_unregister_driver(&parport_pc_pnp_driver);
  2869. platform_driver_unregister(&parport_pc_platform_driver);
  2870. while (!list_empty(&ports_list)) {
  2871. struct parport_pc_private *priv;
  2872. struct parport *port;
  2873. struct device *dev;
  2874. priv = list_entry(ports_list.next,
  2875. struct parport_pc_private, list);
  2876. port = priv->port;
  2877. dev = port->dev;
  2878. parport_pc_unregister_port(port);
  2879. if (dev && dev->bus == &platform_bus_type)
  2880. platform_device_unregister(to_platform_device(dev));
  2881. }
  2882. }
  2883. MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
  2884. MODULE_DESCRIPTION("PC-style parallel port driver");
  2885. MODULE_LICENSE("GPL");
  2886. module_init(parport_pc_init)
  2887. module_exit(parport_pc_exit)