sba_iommu.c 57 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. ** System Bus Adapter (SBA) I/O MMU manager
  4. **
  5. ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
  6. ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
  7. ** (c) Copyright 2000-2004 Hewlett-Packard Company
  8. **
  9. ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
  10. **
  11. **
  12. **
  13. ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
  14. ** J5000/J7000/N-class/L-class machines and their successors.
  15. **
  16. ** FIXME: add DMA hint support programming in both sba and lba modules.
  17. */
  18. #include <linux/types.h>
  19. #include <linux/kernel.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/slab.h>
  22. #include <linux/init.h>
  23. #include <linux/mm.h>
  24. #include <linux/string.h>
  25. #include <linux/pci.h>
  26. #include <linux/dma-map-ops.h>
  27. #include <linux/scatterlist.h>
  28. #include <linux/iommu-helper.h>
  29. /*
  30. * The semantics of 64 register access on 32bit systems can't be guaranteed
  31. * by the C standard, we hope the _lo_hi() macros defining readq and writeq
  32. * here will behave as expected.
  33. */
  34. #include <linux/io-64-nonatomic-lo-hi.h>
  35. #include <asm/byteorder.h>
  36. #include <asm/io.h>
  37. #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
  38. #include <asm/hardware.h> /* for register_parisc_driver() stuff */
  39. #include <linux/proc_fs.h>
  40. #include <linux/seq_file.h>
  41. #include <linux/module.h>
  42. #include <asm/ropes.h>
  43. #include <asm/mckinley.h> /* for proc_mckinley_root */
  44. #include <asm/runway.h> /* for proc_runway_root */
  45. #include <asm/page.h> /* for PAGE0 */
  46. #include <asm/pdc.h> /* for PDC_MODEL_* */
  47. #include <asm/pdcpat.h> /* for is_pdc_pat() */
  48. #include <asm/parisc-device.h>
  49. #include "iommu.h"
  50. #define MODULE_NAME "SBA"
  51. /*
  52. ** The number of debug flags is a clue - this code is fragile.
  53. ** Don't even think about messing with it unless you have
  54. ** plenty of 710's to sacrifice to the computer gods. :^)
  55. */
  56. #undef DEBUG_SBA_INIT
  57. #undef DEBUG_SBA_RUN
  58. #undef DEBUG_SBA_RUN_SG
  59. #undef DEBUG_SBA_RESOURCE
  60. #undef ASSERT_PDIR_SANITY
  61. #undef DEBUG_LARGE_SG_ENTRIES
  62. #undef DEBUG_DMB_TRAP
  63. #ifdef DEBUG_SBA_INIT
  64. #define DBG_INIT(x...) printk(x)
  65. #else
  66. #define DBG_INIT(x...)
  67. #endif
  68. #ifdef DEBUG_SBA_RUN
  69. #define DBG_RUN(x...) printk(x)
  70. #else
  71. #define DBG_RUN(x...)
  72. #endif
  73. #ifdef DEBUG_SBA_RUN_SG
  74. #define DBG_RUN_SG(x...) printk(x)
  75. #else
  76. #define DBG_RUN_SG(x...)
  77. #endif
  78. #ifdef DEBUG_SBA_RESOURCE
  79. #define DBG_RES(x...) printk(x)
  80. #else
  81. #define DBG_RES(x...)
  82. #endif
  83. #define SBA_INLINE __inline__
  84. #define DEFAULT_DMA_HINT_REG 0
  85. struct sba_device *sba_list;
  86. EXPORT_SYMBOL_GPL(sba_list);
  87. static unsigned long ioc_needs_fdc = 0;
  88. /* global count of IOMMUs in the system */
  89. static unsigned int global_ioc_cnt = 0;
  90. /* PA8700 (Piranha 2.2) bug workaround */
  91. static unsigned long piranha_bad_128k = 0;
  92. /* Looks nice and keeps the compiler happy */
  93. #define SBA_DEV(d) ((struct sba_device *) (d))
  94. #ifdef CONFIG_AGP_PARISC
  95. #define SBA_AGP_SUPPORT
  96. #endif /*CONFIG_AGP_PARISC*/
  97. #ifdef SBA_AGP_SUPPORT
  98. static int sba_reserve_agpgart = 1;
  99. module_param(sba_reserve_agpgart, int, 0444);
  100. MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
  101. #endif
  102. /************************************
  103. ** SBA register read and write support
  104. **
  105. ** BE WARNED: register writes are posted.
  106. ** (ie follow writes which must reach HW with a read)
  107. **
  108. ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
  109. */
  110. #define READ_REG32(addr) readl(addr)
  111. #define READ_REG64(addr) readq(addr)
  112. #define WRITE_REG32(val, addr) writel((val), (addr))
  113. #define WRITE_REG64(val, addr) writeq((val), (addr))
  114. #ifdef CONFIG_64BIT
  115. #define READ_REG(addr) READ_REG64(addr)
  116. #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
  117. #else
  118. #define READ_REG(addr) READ_REG32(addr)
  119. #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
  120. #endif
  121. #ifdef DEBUG_SBA_INIT
  122. /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
  123. /**
  124. * sba_dump_ranges - debugging only - print ranges assigned to this IOA
  125. * @hpa: base address of the sba
  126. *
  127. * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
  128. * IO Adapter (aka Bus Converter).
  129. */
  130. static void
  131. sba_dump_ranges(void __iomem *hpa)
  132. {
  133. DBG_INIT("SBA at 0x%p\n", hpa);
  134. DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
  135. DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
  136. DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
  137. DBG_INIT("\n");
  138. DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
  139. DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
  140. DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
  141. }
  142. /**
  143. * sba_dump_tlb - debugging only - print IOMMU operating parameters
  144. * @hpa: base address of the IOMMU
  145. *
  146. * Print the size/location of the IO MMU PDIR.
  147. */
  148. static void sba_dump_tlb(void __iomem *hpa)
  149. {
  150. DBG_INIT("IO TLB at 0x%p\n", hpa);
  151. DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
  152. DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
  153. DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
  154. DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
  155. DBG_INIT("\n");
  156. }
  157. #else
  158. #define sba_dump_ranges(x)
  159. #define sba_dump_tlb(x)
  160. #endif /* DEBUG_SBA_INIT */
  161. #ifdef ASSERT_PDIR_SANITY
  162. /**
  163. * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
  164. * @ioc: IO MMU structure which owns the pdir we are interested in.
  165. * @msg: text to print ont the output line.
  166. * @pide: pdir index.
  167. *
  168. * Print one entry of the IO MMU PDIR in human readable form.
  169. */
  170. static void
  171. sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
  172. {
  173. /* start printing from lowest pde in rval */
  174. u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
  175. unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
  176. uint rcnt;
  177. printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
  178. msg,
  179. rptr, pide & (BITS_PER_LONG - 1), *rptr);
  180. rcnt = 0;
  181. while (rcnt < BITS_PER_LONG) {
  182. printk(KERN_DEBUG "%s %2d %p %016Lx\n",
  183. (rcnt == (pide & (BITS_PER_LONG - 1)))
  184. ? " -->" : " ",
  185. rcnt, ptr, *ptr );
  186. rcnt++;
  187. ptr++;
  188. }
  189. printk(KERN_DEBUG "%s", msg);
  190. }
  191. /**
  192. * sba_check_pdir - debugging only - consistency checker
  193. * @ioc: IO MMU structure which owns the pdir we are interested in.
  194. * @msg: text to print ont the output line.
  195. *
  196. * Verify the resource map and pdir state is consistent
  197. */
  198. static int
  199. sba_check_pdir(struct ioc *ioc, char *msg)
  200. {
  201. u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
  202. u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
  203. u64 *pptr = ioc->pdir_base; /* pdir ptr */
  204. uint pide = 0;
  205. while (rptr < rptr_end) {
  206. u32 rval = *rptr;
  207. int rcnt = 32; /* number of bits we might check */
  208. while (rcnt) {
  209. /* Get last byte and highest bit from that */
  210. u32 pde = ((u32) (((char *)pptr)[7])) << 24;
  211. if ((rval ^ pde) & 0x80000000)
  212. {
  213. /*
  214. ** BUMMER! -- res_map != pdir --
  215. ** Dump rval and matching pdir entries
  216. */
  217. sba_dump_pdir_entry(ioc, msg, pide);
  218. return(1);
  219. }
  220. rcnt--;
  221. rval <<= 1; /* try the next bit */
  222. pptr++;
  223. pide++;
  224. }
  225. rptr++; /* look at next word of res_map */
  226. }
  227. /* It'd be nice if we always got here :^) */
  228. return 0;
  229. }
  230. /**
  231. * sba_dump_sg - debugging only - print Scatter-Gather list
  232. * @ioc: IO MMU structure which owns the pdir we are interested in.
  233. * @startsg: head of the SG list
  234. * @nents: number of entries in SG list
  235. *
  236. * print the SG list so we can verify it's correct by hand.
  237. */
  238. static void
  239. sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
  240. {
  241. while (nents-- > 0) {
  242. printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
  243. nents,
  244. (unsigned long) sg_dma_address(startsg),
  245. sg_dma_len(startsg),
  246. sg_virt(startsg), startsg->length);
  247. startsg++;
  248. }
  249. }
  250. #endif /* ASSERT_PDIR_SANITY */
  251. /**************************************************************
  252. *
  253. * I/O Pdir Resource Management
  254. *
  255. * Bits set in the resource map are in use.
  256. * Each bit can represent a number of pages.
  257. * LSbs represent lower addresses (IOVA's).
  258. *
  259. ***************************************************************/
  260. #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
  261. /* Convert from IOVP to IOVA and vice versa. */
  262. #ifdef ZX1_SUPPORT
  263. /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
  264. #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
  265. #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
  266. #else
  267. /* only support Astro and ancestors. Saves a few cycles in key places */
  268. #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
  269. #define SBA_IOVP(ioc,iova) (iova)
  270. #endif
  271. #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
  272. #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
  273. #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
  274. static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
  275. unsigned int bitshiftcnt)
  276. {
  277. return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
  278. + bitshiftcnt;
  279. }
  280. /**
  281. * sba_search_bitmap - find free space in IO PDIR resource bitmap
  282. * @ioc: IO MMU structure which owns the pdir we are interested in.
  283. * @bits_wanted: number of entries we need.
  284. *
  285. * Find consecutive free bits in resource bitmap.
  286. * Each bit represents one entry in the IO Pdir.
  287. * Cool perf optimization: search for log2(size) bits at a time.
  288. */
  289. static SBA_INLINE unsigned long
  290. sba_search_bitmap(struct ioc *ioc, struct device *dev,
  291. unsigned long bits_wanted)
  292. {
  293. unsigned long *res_ptr = ioc->res_hint;
  294. unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
  295. unsigned long pide = ~0UL, tpide;
  296. unsigned long boundary_size;
  297. unsigned long shift;
  298. int ret;
  299. boundary_size = dma_get_seg_boundary_nr_pages(dev, IOVP_SHIFT);
  300. #if defined(ZX1_SUPPORT)
  301. BUG_ON(ioc->ibase & ~IOVP_MASK);
  302. shift = ioc->ibase >> IOVP_SHIFT;
  303. #else
  304. shift = 0;
  305. #endif
  306. if (bits_wanted > (BITS_PER_LONG/2)) {
  307. /* Search word at a time - no mask needed */
  308. for(; res_ptr < res_end; ++res_ptr) {
  309. tpide = ptr_to_pide(ioc, res_ptr, 0);
  310. ret = iommu_is_span_boundary(tpide, bits_wanted,
  311. shift,
  312. boundary_size);
  313. if ((*res_ptr == 0) && !ret) {
  314. *res_ptr = RESMAP_MASK(bits_wanted);
  315. pide = tpide;
  316. break;
  317. }
  318. }
  319. /* point to the next word on next pass */
  320. res_ptr++;
  321. ioc->res_bitshift = 0;
  322. } else {
  323. /*
  324. ** Search the resource bit map on well-aligned values.
  325. ** "o" is the alignment.
  326. ** We need the alignment to invalidate I/O TLB using
  327. ** SBA HW features in the unmap path.
  328. */
  329. unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
  330. uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
  331. unsigned long mask;
  332. if (bitshiftcnt >= BITS_PER_LONG) {
  333. bitshiftcnt = 0;
  334. res_ptr++;
  335. }
  336. mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
  337. DBG_RES("%s() o %ld %p", __func__, o, res_ptr);
  338. while(res_ptr < res_end)
  339. {
  340. DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
  341. WARN_ON(mask == 0);
  342. tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
  343. ret = iommu_is_span_boundary(tpide, bits_wanted,
  344. shift,
  345. boundary_size);
  346. if ((((*res_ptr) & mask) == 0) && !ret) {
  347. *res_ptr |= mask; /* mark resources busy! */
  348. pide = tpide;
  349. break;
  350. }
  351. mask >>= o;
  352. bitshiftcnt += o;
  353. if (mask == 0) {
  354. mask = RESMAP_MASK(bits_wanted);
  355. bitshiftcnt=0;
  356. res_ptr++;
  357. }
  358. }
  359. /* look in the same word on the next pass */
  360. ioc->res_bitshift = bitshiftcnt + bits_wanted;
  361. }
  362. /* wrapped ? */
  363. if (res_end <= res_ptr) {
  364. ioc->res_hint = (unsigned long *) ioc->res_map;
  365. ioc->res_bitshift = 0;
  366. } else {
  367. ioc->res_hint = res_ptr;
  368. }
  369. return (pide);
  370. }
  371. /**
  372. * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
  373. * @ioc: IO MMU structure which owns the pdir we are interested in.
  374. * @size: number of bytes to create a mapping for
  375. *
  376. * Given a size, find consecutive unmarked and then mark those bits in the
  377. * resource bit map.
  378. */
  379. static int
  380. sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
  381. {
  382. unsigned int pages_needed = size >> IOVP_SHIFT;
  383. #ifdef SBA_COLLECT_STATS
  384. unsigned long cr_start = mfctl(16);
  385. #endif
  386. unsigned long pide;
  387. pide = sba_search_bitmap(ioc, dev, pages_needed);
  388. if (pide >= (ioc->res_size << 3)) {
  389. pide = sba_search_bitmap(ioc, dev, pages_needed);
  390. if (pide >= (ioc->res_size << 3))
  391. panic("%s: I/O MMU @ %p is out of mapping resources\n",
  392. __FILE__, ioc->ioc_hpa);
  393. }
  394. #ifdef ASSERT_PDIR_SANITY
  395. /* verify the first enable bit is clear */
  396. if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
  397. sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
  398. }
  399. #endif
  400. DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
  401. __func__, size, pages_needed, pide,
  402. (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
  403. ioc->res_bitshift );
  404. #ifdef SBA_COLLECT_STATS
  405. {
  406. unsigned long cr_end = mfctl(16);
  407. unsigned long tmp = cr_end - cr_start;
  408. /* check for roll over */
  409. cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
  410. }
  411. ioc->avg_search[ioc->avg_idx++] = cr_start;
  412. ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
  413. ioc->used_pages += pages_needed;
  414. #endif
  415. return (pide);
  416. }
  417. /**
  418. * sba_free_range - unmark bits in IO PDIR resource bitmap
  419. * @ioc: IO MMU structure which owns the pdir we are interested in.
  420. * @iova: IO virtual address which was previously allocated.
  421. * @size: number of bytes to create a mapping for
  422. *
  423. * clear bits in the ioc's resource map
  424. */
  425. static SBA_INLINE void
  426. sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
  427. {
  428. unsigned long iovp = SBA_IOVP(ioc, iova);
  429. unsigned int pide = PDIR_INDEX(iovp);
  430. unsigned int ridx = pide >> 3; /* convert bit to byte address */
  431. unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
  432. int bits_not_wanted = size >> IOVP_SHIFT;
  433. /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
  434. unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
  435. DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
  436. __func__, (uint) iova, size,
  437. bits_not_wanted, m, pide, res_ptr, *res_ptr);
  438. #ifdef SBA_COLLECT_STATS
  439. ioc->used_pages -= bits_not_wanted;
  440. #endif
  441. *res_ptr &= ~m;
  442. }
  443. /**************************************************************
  444. *
  445. * "Dynamic DMA Mapping" support (aka "Coherent I/O")
  446. *
  447. ***************************************************************/
  448. #ifdef SBA_HINT_SUPPORT
  449. #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
  450. #endif
  451. typedef unsigned long space_t;
  452. #define KERNEL_SPACE 0
  453. /**
  454. * sba_io_pdir_entry - fill in one IO PDIR entry
  455. * @pdir_ptr: pointer to IO PDIR entry
  456. * @sid: process Space ID - currently only support KERNEL_SPACE
  457. * @vba: Virtual CPU address of buffer to map
  458. * @hint: DMA hint set to use for this mapping
  459. *
  460. * SBA Mapping Routine
  461. *
  462. * Given a virtual address (vba, arg2) and space id, (sid, arg1)
  463. * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
  464. * pdir_ptr (arg0).
  465. * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
  466. * for Astro/Ike looks like:
  467. *
  468. *
  469. * 0 19 51 55 63
  470. * +-+---------------------+----------------------------------+----+--------+
  471. * |V| U | PPN[43:12] | U | VI |
  472. * +-+---------------------+----------------------------------+----+--------+
  473. *
  474. * Pluto is basically identical, supports fewer physical address bits:
  475. *
  476. * 0 23 51 55 63
  477. * +-+------------------------+-------------------------------+----+--------+
  478. * |V| U | PPN[39:12] | U | VI |
  479. * +-+------------------------+-------------------------------+----+--------+
  480. *
  481. * V == Valid Bit (Most Significant Bit is bit 0)
  482. * U == Unused
  483. * PPN == Physical Page Number
  484. * VI == Virtual Index (aka Coherent Index)
  485. *
  486. * LPA instruction output is put into PPN field.
  487. * LCI (Load Coherence Index) instruction provides the "VI" bits.
  488. *
  489. * We pre-swap the bytes since PCX-W is Big Endian and the
  490. * IOMMU uses little endian for the pdir.
  491. */
  492. static void SBA_INLINE
  493. sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
  494. unsigned long hint)
  495. {
  496. u64 pa; /* physical address */
  497. register unsigned ci; /* coherent index */
  498. pa = lpa(vba);
  499. pa &= IOVP_MASK;
  500. asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba));
  501. pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */
  502. pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
  503. *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
  504. /*
  505. * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
  506. * (bit #61, big endian), we have to flush and sync every time
  507. * IO-PDIR is changed in Ike/Astro.
  508. */
  509. asm_io_fdc(pdir_ptr);
  510. }
  511. /**
  512. * sba_mark_invalid - invalidate one or more IO PDIR entries
  513. * @ioc: IO MMU structure which owns the pdir we are interested in.
  514. * @iova: IO Virtual Address mapped earlier
  515. * @byte_cnt: number of bytes this mapping covers.
  516. *
  517. * Marking the IO PDIR entry(ies) as Invalid and invalidate
  518. * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
  519. * is to purge stale entries in the IO TLB when unmapping entries.
  520. *
  521. * The PCOM register supports purging of multiple pages, with a minium
  522. * of 1 page and a maximum of 2GB. Hardware requires the address be
  523. * aligned to the size of the range being purged. The size of the range
  524. * must be a power of 2. The "Cool perf optimization" in the
  525. * allocation routine helps keep that true.
  526. */
  527. static SBA_INLINE void
  528. sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
  529. {
  530. u32 iovp = (u32) SBA_IOVP(ioc,iova);
  531. u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
  532. #ifdef ASSERT_PDIR_SANITY
  533. /* Assert first pdir entry is set.
  534. **
  535. ** Even though this is a big-endian machine, the entries
  536. ** in the iopdir are little endian. That's why we look at
  537. ** the byte at +7 instead of at +0.
  538. */
  539. if (0x80 != (((u8 *) pdir_ptr)[7])) {
  540. sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
  541. }
  542. #endif
  543. if (byte_cnt > IOVP_SIZE)
  544. {
  545. #if 0
  546. unsigned long entries_per_cacheline = ioc_needs_fdc ?
  547. L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
  548. - (unsigned long) pdir_ptr;
  549. : 262144;
  550. #endif
  551. /* set "size" field for PCOM */
  552. iovp |= get_order(byte_cnt) + PAGE_SHIFT;
  553. do {
  554. /* clear I/O Pdir entry "valid" bit first */
  555. ((u8 *) pdir_ptr)[7] = 0;
  556. asm_io_fdc(pdir_ptr);
  557. if (ioc_needs_fdc) {
  558. #if 0
  559. entries_per_cacheline = L1_CACHE_SHIFT - 3;
  560. #endif
  561. }
  562. pdir_ptr++;
  563. byte_cnt -= IOVP_SIZE;
  564. } while (byte_cnt > IOVP_SIZE);
  565. } else
  566. iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
  567. /*
  568. ** clear I/O PDIR entry "valid" bit.
  569. ** We have to R/M/W the cacheline regardless how much of the
  570. ** pdir entry that we clobber.
  571. ** The rest of the entry would be useful for debugging if we
  572. ** could dump core on HPMC.
  573. */
  574. ((u8 *) pdir_ptr)[7] = 0;
  575. asm_io_fdc(pdir_ptr);
  576. WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
  577. }
  578. /**
  579. * sba_dma_supported - PCI driver can query DMA support
  580. * @dev: instance of PCI owned by the driver that's asking
  581. * @mask: number of address bits this PCI device can handle
  582. *
  583. * See Documentation/core-api/dma-api-howto.rst
  584. */
  585. static int sba_dma_supported( struct device *dev, u64 mask)
  586. {
  587. struct ioc *ioc;
  588. if (dev == NULL) {
  589. printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
  590. BUG();
  591. return(0);
  592. }
  593. ioc = GET_IOC(dev);
  594. if (!ioc)
  595. return 0;
  596. /*
  597. * check if mask is >= than the current max IO Virt Address
  598. * The max IO Virt address will *always* < 30 bits.
  599. */
  600. return((int)(mask >= (ioc->ibase - 1 +
  601. (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
  602. }
  603. /**
  604. * sba_map_single - map one buffer and return IOVA for DMA
  605. * @dev: instance of PCI owned by the driver that's asking.
  606. * @addr: driver buffer to map.
  607. * @size: number of bytes to map in driver buffer.
  608. * @direction: R/W or both.
  609. *
  610. * See Documentation/core-api/dma-api-howto.rst
  611. */
  612. static dma_addr_t
  613. sba_map_single(struct device *dev, void *addr, size_t size,
  614. enum dma_data_direction direction)
  615. {
  616. struct ioc *ioc;
  617. unsigned long flags;
  618. dma_addr_t iovp;
  619. dma_addr_t offset;
  620. u64 *pdir_start;
  621. int pide;
  622. ioc = GET_IOC(dev);
  623. if (!ioc)
  624. return DMA_MAPPING_ERROR;
  625. /* save offset bits */
  626. offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
  627. /* round up to nearest IOVP_SIZE */
  628. size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
  629. spin_lock_irqsave(&ioc->res_lock, flags);
  630. #ifdef ASSERT_PDIR_SANITY
  631. sba_check_pdir(ioc,"Check before sba_map_single()");
  632. #endif
  633. #ifdef SBA_COLLECT_STATS
  634. ioc->msingle_calls++;
  635. ioc->msingle_pages += size >> IOVP_SHIFT;
  636. #endif
  637. pide = sba_alloc_range(ioc, dev, size);
  638. iovp = (dma_addr_t) pide << IOVP_SHIFT;
  639. DBG_RUN("%s() 0x%p -> 0x%lx\n",
  640. __func__, addr, (long) iovp | offset);
  641. pdir_start = &(ioc->pdir_base[pide]);
  642. while (size > 0) {
  643. sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
  644. DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
  645. pdir_start,
  646. (u8) (((u8 *) pdir_start)[7]),
  647. (u8) (((u8 *) pdir_start)[6]),
  648. (u8) (((u8 *) pdir_start)[5]),
  649. (u8) (((u8 *) pdir_start)[4]),
  650. (u8) (((u8 *) pdir_start)[3]),
  651. (u8) (((u8 *) pdir_start)[2]),
  652. (u8) (((u8 *) pdir_start)[1]),
  653. (u8) (((u8 *) pdir_start)[0])
  654. );
  655. addr += IOVP_SIZE;
  656. size -= IOVP_SIZE;
  657. pdir_start++;
  658. }
  659. /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
  660. asm_io_sync();
  661. #ifdef ASSERT_PDIR_SANITY
  662. sba_check_pdir(ioc,"Check after sba_map_single()");
  663. #endif
  664. spin_unlock_irqrestore(&ioc->res_lock, flags);
  665. /* form complete address */
  666. return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
  667. }
  668. static dma_addr_t
  669. sba_map_page(struct device *dev, struct page *page, unsigned long offset,
  670. size_t size, enum dma_data_direction direction,
  671. unsigned long attrs)
  672. {
  673. return sba_map_single(dev, page_address(page) + offset, size,
  674. direction);
  675. }
  676. /**
  677. * sba_unmap_page - unmap one IOVA and free resources
  678. * @dev: instance of PCI owned by the driver that's asking.
  679. * @iova: IOVA of driver buffer previously mapped.
  680. * @size: number of bytes mapped in driver buffer.
  681. * @direction: R/W or both.
  682. *
  683. * See Documentation/core-api/dma-api-howto.rst
  684. */
  685. static void
  686. sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size,
  687. enum dma_data_direction direction, unsigned long attrs)
  688. {
  689. struct ioc *ioc;
  690. #if DELAYED_RESOURCE_CNT > 0
  691. struct sba_dma_pair *d;
  692. #endif
  693. unsigned long flags;
  694. dma_addr_t offset;
  695. DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size);
  696. ioc = GET_IOC(dev);
  697. if (!ioc) {
  698. WARN_ON(!ioc);
  699. return;
  700. }
  701. offset = iova & ~IOVP_MASK;
  702. iova ^= offset; /* clear offset bits */
  703. size += offset;
  704. size = ALIGN(size, IOVP_SIZE);
  705. spin_lock_irqsave(&ioc->res_lock, flags);
  706. #ifdef SBA_COLLECT_STATS
  707. ioc->usingle_calls++;
  708. ioc->usingle_pages += size >> IOVP_SHIFT;
  709. #endif
  710. sba_mark_invalid(ioc, iova, size);
  711. #if DELAYED_RESOURCE_CNT > 0
  712. /* Delaying when we re-use a IO Pdir entry reduces the number
  713. * of MMIO reads needed to flush writes to the PCOM register.
  714. */
  715. d = &(ioc->saved[ioc->saved_cnt]);
  716. d->iova = iova;
  717. d->size = size;
  718. if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
  719. int cnt = ioc->saved_cnt;
  720. while (cnt--) {
  721. sba_free_range(ioc, d->iova, d->size);
  722. d--;
  723. }
  724. ioc->saved_cnt = 0;
  725. READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
  726. }
  727. #else /* DELAYED_RESOURCE_CNT == 0 */
  728. sba_free_range(ioc, iova, size);
  729. /* If fdc's were issued, force fdc's to be visible now */
  730. asm_io_sync();
  731. READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
  732. #endif /* DELAYED_RESOURCE_CNT == 0 */
  733. spin_unlock_irqrestore(&ioc->res_lock, flags);
  734. /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
  735. ** For Astro based systems this isn't a big deal WRT performance.
  736. ** As long as 2.4 kernels copyin/copyout data from/to userspace,
  737. ** we don't need the syncdma. The issue here is I/O MMU cachelines
  738. ** are *not* coherent in all cases. May be hwrev dependent.
  739. ** Need to investigate more.
  740. asm volatile("syncdma");
  741. */
  742. }
  743. /**
  744. * sba_alloc - allocate/map shared mem for DMA
  745. * @hwdev: instance of PCI owned by the driver that's asking.
  746. * @size: number of bytes mapped in driver buffer.
  747. * @dma_handle: IOVA of new buffer.
  748. *
  749. * See Documentation/core-api/dma-api-howto.rst
  750. */
  751. static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle,
  752. gfp_t gfp, unsigned long attrs)
  753. {
  754. void *ret;
  755. if (!hwdev) {
  756. /* only support PCI */
  757. *dma_handle = 0;
  758. return NULL;
  759. }
  760. ret = (void *) __get_free_pages(gfp, get_order(size));
  761. if (ret) {
  762. memset(ret, 0, size);
  763. *dma_handle = sba_map_single(hwdev, ret, size, 0);
  764. }
  765. return ret;
  766. }
  767. /**
  768. * sba_free - free/unmap shared mem for DMA
  769. * @hwdev: instance of PCI owned by the driver that's asking.
  770. * @size: number of bytes mapped in driver buffer.
  771. * @vaddr: virtual address IOVA of "consistent" buffer.
  772. * @dma_handler: IO virtual address of "consistent" buffer.
  773. *
  774. * See Documentation/core-api/dma-api-howto.rst
  775. */
  776. static void
  777. sba_free(struct device *hwdev, size_t size, void *vaddr,
  778. dma_addr_t dma_handle, unsigned long attrs)
  779. {
  780. sba_unmap_page(hwdev, dma_handle, size, 0, 0);
  781. free_pages((unsigned long) vaddr, get_order(size));
  782. }
  783. /*
  784. ** Since 0 is a valid pdir_base index value, can't use that
  785. ** to determine if a value is valid or not. Use a flag to indicate
  786. ** the SG list entry contains a valid pdir index.
  787. */
  788. #define PIDE_FLAG 0x80000000UL
  789. #ifdef SBA_COLLECT_STATS
  790. #define IOMMU_MAP_STATS
  791. #endif
  792. #include "iommu-helpers.h"
  793. #ifdef DEBUG_LARGE_SG_ENTRIES
  794. int dump_run_sg = 0;
  795. #endif
  796. /**
  797. * sba_map_sg - map Scatter/Gather list
  798. * @dev: instance of PCI owned by the driver that's asking.
  799. * @sglist: array of buffer/length pairs
  800. * @nents: number of entries in list
  801. * @direction: R/W or both.
  802. *
  803. * See Documentation/core-api/dma-api-howto.rst
  804. */
  805. static int
  806. sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
  807. enum dma_data_direction direction, unsigned long attrs)
  808. {
  809. struct ioc *ioc;
  810. int coalesced, filled = 0;
  811. unsigned long flags;
  812. DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
  813. ioc = GET_IOC(dev);
  814. if (!ioc)
  815. return -EINVAL;
  816. /* Fast path single entry scatterlists. */
  817. if (nents == 1) {
  818. sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist),
  819. sglist->length, direction);
  820. sg_dma_len(sglist) = sglist->length;
  821. return 1;
  822. }
  823. spin_lock_irqsave(&ioc->res_lock, flags);
  824. #ifdef ASSERT_PDIR_SANITY
  825. if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
  826. {
  827. sba_dump_sg(ioc, sglist, nents);
  828. panic("Check before sba_map_sg()");
  829. }
  830. #endif
  831. #ifdef SBA_COLLECT_STATS
  832. ioc->msg_calls++;
  833. #endif
  834. /*
  835. ** First coalesce the chunks and allocate I/O pdir space
  836. **
  837. ** If this is one DMA stream, we can properly map using the
  838. ** correct virtual address associated with each DMA page.
  839. ** w/o this association, we wouldn't have coherent DMA!
  840. ** Access to the virtual address is what forces a two pass algorithm.
  841. */
  842. coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
  843. /*
  844. ** Program the I/O Pdir
  845. **
  846. ** map the virtual addresses to the I/O Pdir
  847. ** o dma_address will contain the pdir index
  848. ** o dma_len will contain the number of bytes to map
  849. ** o address contains the virtual address.
  850. */
  851. filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
  852. /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
  853. asm_io_sync();
  854. #ifdef ASSERT_PDIR_SANITY
  855. if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
  856. {
  857. sba_dump_sg(ioc, sglist, nents);
  858. panic("Check after sba_map_sg()\n");
  859. }
  860. #endif
  861. spin_unlock_irqrestore(&ioc->res_lock, flags);
  862. DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
  863. return filled;
  864. }
  865. /**
  866. * sba_unmap_sg - unmap Scatter/Gather list
  867. * @dev: instance of PCI owned by the driver that's asking.
  868. * @sglist: array of buffer/length pairs
  869. * @nents: number of entries in list
  870. * @direction: R/W or both.
  871. *
  872. * See Documentation/core-api/dma-api-howto.rst
  873. */
  874. static void
  875. sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
  876. enum dma_data_direction direction, unsigned long attrs)
  877. {
  878. struct ioc *ioc;
  879. #ifdef ASSERT_PDIR_SANITY
  880. unsigned long flags;
  881. #endif
  882. DBG_RUN_SG("%s() START %d entries, %p,%x\n",
  883. __func__, nents, sg_virt(sglist), sglist->length);
  884. ioc = GET_IOC(dev);
  885. if (!ioc) {
  886. WARN_ON(!ioc);
  887. return;
  888. }
  889. #ifdef SBA_COLLECT_STATS
  890. ioc->usg_calls++;
  891. #endif
  892. #ifdef ASSERT_PDIR_SANITY
  893. spin_lock_irqsave(&ioc->res_lock, flags);
  894. sba_check_pdir(ioc,"Check before sba_unmap_sg()");
  895. spin_unlock_irqrestore(&ioc->res_lock, flags);
  896. #endif
  897. while (nents && sg_dma_len(sglist)) {
  898. sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist),
  899. direction, 0);
  900. #ifdef SBA_COLLECT_STATS
  901. ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
  902. ioc->usingle_calls--; /* kluge since call is unmap_sg() */
  903. #endif
  904. ++sglist;
  905. nents--;
  906. }
  907. DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
  908. #ifdef ASSERT_PDIR_SANITY
  909. spin_lock_irqsave(&ioc->res_lock, flags);
  910. sba_check_pdir(ioc,"Check after sba_unmap_sg()");
  911. spin_unlock_irqrestore(&ioc->res_lock, flags);
  912. #endif
  913. }
  914. static const struct dma_map_ops sba_ops = {
  915. .dma_supported = sba_dma_supported,
  916. .alloc = sba_alloc,
  917. .free = sba_free,
  918. .map_page = sba_map_page,
  919. .unmap_page = sba_unmap_page,
  920. .map_sg = sba_map_sg,
  921. .unmap_sg = sba_unmap_sg,
  922. .get_sgtable = dma_common_get_sgtable,
  923. .alloc_pages = dma_common_alloc_pages,
  924. .free_pages = dma_common_free_pages,
  925. };
  926. /**************************************************************************
  927. **
  928. ** SBA PAT PDC support
  929. **
  930. ** o call pdc_pat_cell_module()
  931. ** o store ranges in PCI "resource" structures
  932. **
  933. **************************************************************************/
  934. static void
  935. sba_get_pat_resources(struct sba_device *sba_dev)
  936. {
  937. #if 0
  938. /*
  939. ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
  940. ** PAT PDC to program the SBA/LBA directed range registers...this
  941. ** burden may fall on the LBA code since it directly supports the
  942. ** PCI subsystem. It's not clear yet. - ggg
  943. */
  944. PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
  945. FIXME : ???
  946. PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
  947. Tells where the dvi bits are located in the address.
  948. PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
  949. FIXME : ???
  950. #endif
  951. }
  952. /**************************************************************
  953. *
  954. * Initialization and claim
  955. *
  956. ***************************************************************/
  957. #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
  958. #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
  959. static void *
  960. sba_alloc_pdir(unsigned int pdir_size)
  961. {
  962. unsigned long pdir_base;
  963. unsigned long pdir_order = get_order(pdir_size);
  964. pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
  965. if (NULL == (void *) pdir_base) {
  966. panic("%s() could not allocate I/O Page Table\n",
  967. __func__);
  968. }
  969. /* If this is not PA8700 (PCX-W2)
  970. ** OR newer than ver 2.2
  971. ** OR in a system that doesn't need VINDEX bits from SBA,
  972. **
  973. ** then we aren't exposed to the HW bug.
  974. */
  975. if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
  976. || (boot_cpu_data.pdc.versions > 0x202)
  977. || (boot_cpu_data.pdc.capabilities & 0x08L) )
  978. return (void *) pdir_base;
  979. /*
  980. * PA8700 (PCX-W2, aka piranha) silent data corruption fix
  981. *
  982. * An interaction between PA8700 CPU (Ver 2.2 or older) and
  983. * Ike/Astro can cause silent data corruption. This is only
  984. * a problem if the I/O PDIR is located in memory such that
  985. * (little-endian) bits 17 and 18 are on and bit 20 is off.
  986. *
  987. * Since the max IO Pdir size is 2MB, by cleverly allocating the
  988. * right physical address, we can either avoid (IOPDIR <= 1MB)
  989. * or minimize (2MB IO Pdir) the problem if we restrict the
  990. * IO Pdir to a maximum size of 2MB-128K (1902K).
  991. *
  992. * Because we always allocate 2^N sized IO pdirs, either of the
  993. * "bad" regions will be the last 128K if at all. That's easy
  994. * to test for.
  995. *
  996. */
  997. if (pdir_order <= (19-12)) {
  998. if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
  999. /* allocate a new one on 512k alignment */
  1000. unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
  1001. /* release original */
  1002. free_pages(pdir_base, pdir_order);
  1003. pdir_base = new_pdir;
  1004. /* release excess */
  1005. while (pdir_order < (19-12)) {
  1006. new_pdir += pdir_size;
  1007. free_pages(new_pdir, pdir_order);
  1008. pdir_order +=1;
  1009. pdir_size <<=1;
  1010. }
  1011. }
  1012. } else {
  1013. /*
  1014. ** 1MB or 2MB Pdir
  1015. ** Needs to be aligned on an "odd" 1MB boundary.
  1016. */
  1017. unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
  1018. /* release original */
  1019. free_pages( pdir_base, pdir_order);
  1020. /* release first 1MB */
  1021. free_pages(new_pdir, 20-12);
  1022. pdir_base = new_pdir + 1024*1024;
  1023. if (pdir_order > (20-12)) {
  1024. /*
  1025. ** 2MB Pdir.
  1026. **
  1027. ** Flag tells init_bitmap() to mark bad 128k as used
  1028. ** and to reduce the size by 128k.
  1029. */
  1030. piranha_bad_128k = 1;
  1031. new_pdir += 3*1024*1024;
  1032. /* release last 1MB */
  1033. free_pages(new_pdir, 20-12);
  1034. /* release unusable 128KB */
  1035. free_pages(new_pdir - 128*1024 , 17-12);
  1036. pdir_size -= 128*1024;
  1037. }
  1038. }
  1039. memset((void *) pdir_base, 0, pdir_size);
  1040. return (void *) pdir_base;
  1041. }
  1042. struct ibase_data_struct {
  1043. struct ioc *ioc;
  1044. int ioc_num;
  1045. };
  1046. static int setup_ibase_imask_callback(struct device *dev, void *data)
  1047. {
  1048. /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
  1049. extern void lba_set_iregs(struct parisc_device *, u32, u32);
  1050. struct parisc_device *lba = to_parisc_device(dev);
  1051. struct ibase_data_struct *ibd = data;
  1052. int rope_num = (lba->hpa.start >> 13) & 0xf;
  1053. if (rope_num >> 3 == ibd->ioc_num)
  1054. lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
  1055. return 0;
  1056. }
  1057. /* setup Mercury or Elroy IBASE/IMASK registers. */
  1058. static void
  1059. setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
  1060. {
  1061. struct ibase_data_struct ibase_data = {
  1062. .ioc = ioc,
  1063. .ioc_num = ioc_num,
  1064. };
  1065. device_for_each_child(&sba->dev, &ibase_data,
  1066. setup_ibase_imask_callback);
  1067. }
  1068. #ifdef SBA_AGP_SUPPORT
  1069. static int
  1070. sba_ioc_find_quicksilver(struct device *dev, void *data)
  1071. {
  1072. int *agp_found = data;
  1073. struct parisc_device *lba = to_parisc_device(dev);
  1074. if (IS_QUICKSILVER(lba))
  1075. *agp_found = 1;
  1076. return 0;
  1077. }
  1078. #endif
  1079. static void
  1080. sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
  1081. {
  1082. u32 iova_space_mask;
  1083. u32 iova_space_size;
  1084. int iov_order, tcnfg;
  1085. #ifdef SBA_AGP_SUPPORT
  1086. int agp_found = 0;
  1087. #endif
  1088. /*
  1089. ** Firmware programs the base and size of a "safe IOVA space"
  1090. ** (one that doesn't overlap memory or LMMIO space) in the
  1091. ** IBASE and IMASK registers.
  1092. */
  1093. ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1fffffULL;
  1094. iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
  1095. if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
  1096. printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
  1097. iova_space_size /= 2;
  1098. }
  1099. /*
  1100. ** iov_order is always based on a 1GB IOVA space since we want to
  1101. ** turn on the other half for AGP GART.
  1102. */
  1103. iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
  1104. ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
  1105. DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
  1106. __func__, ioc->ioc_hpa, iova_space_size >> 20,
  1107. iov_order + PAGE_SHIFT);
  1108. ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
  1109. get_order(ioc->pdir_size));
  1110. if (!ioc->pdir_base)
  1111. panic("Couldn't allocate I/O Page Table\n");
  1112. memset(ioc->pdir_base, 0, ioc->pdir_size);
  1113. DBG_INIT("%s() pdir %p size %x\n",
  1114. __func__, ioc->pdir_base, ioc->pdir_size);
  1115. #ifdef SBA_HINT_SUPPORT
  1116. ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
  1117. ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
  1118. DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
  1119. ioc->hint_shift_pdir, ioc->hint_mask_pdir);
  1120. #endif
  1121. WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
  1122. WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
  1123. /* build IMASK for IOC and Elroy */
  1124. iova_space_mask = 0xffffffff;
  1125. iova_space_mask <<= (iov_order + PAGE_SHIFT);
  1126. ioc->imask = iova_space_mask;
  1127. #ifdef ZX1_SUPPORT
  1128. ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
  1129. #endif
  1130. sba_dump_tlb(ioc->ioc_hpa);
  1131. setup_ibase_imask(sba, ioc, ioc_num);
  1132. WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
  1133. #ifdef CONFIG_64BIT
  1134. /*
  1135. ** Setting the upper bits makes checking for bypass addresses
  1136. ** a little faster later on.
  1137. */
  1138. ioc->imask |= 0xFFFFFFFF00000000UL;
  1139. #endif
  1140. /* Set I/O PDIR Page size to system page size */
  1141. switch (PAGE_SHIFT) {
  1142. case 12: tcnfg = 0; break; /* 4K */
  1143. case 13: tcnfg = 1; break; /* 8K */
  1144. case 14: tcnfg = 2; break; /* 16K */
  1145. case 16: tcnfg = 3; break; /* 64K */
  1146. default:
  1147. panic(__FILE__ "Unsupported system page size %d",
  1148. 1 << PAGE_SHIFT);
  1149. break;
  1150. }
  1151. WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
  1152. /*
  1153. ** Program the IOC's ibase and enable IOVA translation
  1154. ** Bit zero == enable bit.
  1155. */
  1156. WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
  1157. /*
  1158. ** Clear I/O TLB of any possible entries.
  1159. ** (Yes. This is a bit paranoid...but so what)
  1160. */
  1161. WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
  1162. #ifdef SBA_AGP_SUPPORT
  1163. /*
  1164. ** If an AGP device is present, only use half of the IOV space
  1165. ** for PCI DMA. Unfortunately we can't know ahead of time
  1166. ** whether GART support will actually be used, for now we
  1167. ** can just key on any AGP device found in the system.
  1168. ** We program the next pdir index after we stop w/ a key for
  1169. ** the GART code to handshake on.
  1170. */
  1171. device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
  1172. if (agp_found && sba_reserve_agpgart) {
  1173. printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
  1174. __func__, (iova_space_size/2) >> 20);
  1175. ioc->pdir_size /= 2;
  1176. ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
  1177. }
  1178. #endif /*SBA_AGP_SUPPORT*/
  1179. }
  1180. static void
  1181. sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
  1182. {
  1183. u32 iova_space_size, iova_space_mask;
  1184. unsigned int pdir_size, iov_order, tcnfg;
  1185. /*
  1186. ** Determine IOVA Space size from memory size.
  1187. **
  1188. ** Ideally, PCI drivers would register the maximum number
  1189. ** of DMA they can have outstanding for each device they
  1190. ** own. Next best thing would be to guess how much DMA
  1191. ** can be outstanding based on PCI Class/sub-class. Both
  1192. ** methods still require some "extra" to support PCI
  1193. ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
  1194. **
  1195. ** While we have 32-bits "IOVA" space, top two 2 bits are used
  1196. ** for DMA hints - ergo only 30 bits max.
  1197. */
  1198. iova_space_size = (u32) (totalram_pages()/global_ioc_cnt);
  1199. /* limit IOVA space size to 1MB-1GB */
  1200. if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
  1201. iova_space_size = 1 << (20 - PAGE_SHIFT);
  1202. }
  1203. else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
  1204. iova_space_size = 1 << (30 - PAGE_SHIFT);
  1205. }
  1206. /*
  1207. ** iova space must be log2() in size.
  1208. ** thus, pdir/res_map will also be log2().
  1209. ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
  1210. */
  1211. iov_order = get_order(iova_space_size << PAGE_SHIFT);
  1212. /* iova_space_size is now bytes, not pages */
  1213. iova_space_size = 1 << (iov_order + PAGE_SHIFT);
  1214. ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
  1215. DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
  1216. __func__,
  1217. ioc->ioc_hpa,
  1218. (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT),
  1219. iova_space_size>>20,
  1220. iov_order + PAGE_SHIFT);
  1221. ioc->pdir_base = sba_alloc_pdir(pdir_size);
  1222. DBG_INIT("%s() pdir %p size %x\n",
  1223. __func__, ioc->pdir_base, pdir_size);
  1224. #ifdef SBA_HINT_SUPPORT
  1225. /* FIXME : DMA HINTs not used */
  1226. ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
  1227. ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
  1228. DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
  1229. ioc->hint_shift_pdir, ioc->hint_mask_pdir);
  1230. #endif
  1231. WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
  1232. /* build IMASK for IOC and Elroy */
  1233. iova_space_mask = 0xffffffff;
  1234. iova_space_mask <<= (iov_order + PAGE_SHIFT);
  1235. /*
  1236. ** On C3000 w/512MB mem, HP-UX 10.20 reports:
  1237. ** ibase=0, imask=0xFE000000, size=0x2000000.
  1238. */
  1239. ioc->ibase = 0;
  1240. ioc->imask = iova_space_mask; /* save it */
  1241. #ifdef ZX1_SUPPORT
  1242. ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
  1243. #endif
  1244. DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
  1245. __func__, ioc->ibase, ioc->imask);
  1246. /*
  1247. ** FIXME: Hint registers are programmed with default hint
  1248. ** values during boot, so hints should be sane even if we
  1249. ** can't reprogram them the way drivers want.
  1250. */
  1251. setup_ibase_imask(sba, ioc, ioc_num);
  1252. /*
  1253. ** Program the IOC's ibase and enable IOVA translation
  1254. */
  1255. WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
  1256. WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
  1257. /* Set I/O PDIR Page size to system page size */
  1258. switch (PAGE_SHIFT) {
  1259. case 12: tcnfg = 0; break; /* 4K */
  1260. case 13: tcnfg = 1; break; /* 8K */
  1261. case 14: tcnfg = 2; break; /* 16K */
  1262. case 16: tcnfg = 3; break; /* 64K */
  1263. default:
  1264. panic(__FILE__ "Unsupported system page size %d",
  1265. 1 << PAGE_SHIFT);
  1266. break;
  1267. }
  1268. /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */
  1269. WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
  1270. /*
  1271. ** Clear I/O TLB of any possible entries.
  1272. ** (Yes. This is a bit paranoid...but so what)
  1273. */
  1274. WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
  1275. ioc->ibase = 0; /* used by SBA_IOVA and related macros */
  1276. DBG_INIT("%s() DONE\n", __func__);
  1277. }
  1278. /**************************************************************************
  1279. **
  1280. ** SBA initialization code (HW and SW)
  1281. **
  1282. ** o identify SBA chip itself
  1283. ** o initialize SBA chip modes (HardFail)
  1284. ** o initialize SBA chip modes (HardFail)
  1285. ** o FIXME: initialize DMA hints for reasonable defaults
  1286. **
  1287. **************************************************************************/
  1288. static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
  1289. {
  1290. return ioremap(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
  1291. }
  1292. static void sba_hw_init(struct sba_device *sba_dev)
  1293. {
  1294. int i;
  1295. int num_ioc;
  1296. u64 ioc_ctl;
  1297. if (!is_pdc_pat()) {
  1298. /* Shutdown the USB controller on Astro-based workstations.
  1299. ** Once we reprogram the IOMMU, the next DMA performed by
  1300. ** USB will HPMC the box. USB is only enabled if a
  1301. ** keyboard is present and found.
  1302. **
  1303. ** With serial console, j6k v5.0 firmware says:
  1304. ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
  1305. **
  1306. ** FIXME: Using GFX+USB console at power up but direct
  1307. ** linux to serial console is still broken.
  1308. ** USB could generate DMA so we must reset USB.
  1309. ** The proper sequence would be:
  1310. ** o block console output
  1311. ** o reset USB device
  1312. ** o reprogram serial port
  1313. ** o unblock console output
  1314. */
  1315. if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
  1316. pdc_io_reset_devices();
  1317. }
  1318. }
  1319. #if 0
  1320. printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
  1321. PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
  1322. /*
  1323. ** Need to deal with DMA from LAN.
  1324. ** Maybe use page zero boot device as a handle to talk
  1325. ** to PDC about which device to shutdown.
  1326. **
  1327. ** Netbooting, j6k v5.0 firmware says:
  1328. ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
  1329. ** ARGH! invalid class.
  1330. */
  1331. if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
  1332. && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
  1333. pdc_io_reset();
  1334. }
  1335. #endif
  1336. if (!IS_PLUTO(sba_dev->dev)) {
  1337. ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
  1338. DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
  1339. __func__, sba_dev->sba_hpa, ioc_ctl);
  1340. ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
  1341. ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
  1342. /* j6700 v1.6 firmware sets 0x294f */
  1343. /* A500 firmware sets 0x4d */
  1344. WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
  1345. #ifdef DEBUG_SBA_INIT
  1346. ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
  1347. DBG_INIT(" 0x%Lx\n", ioc_ctl);
  1348. #endif
  1349. } /* if !PLUTO */
  1350. if (IS_ASTRO(sba_dev->dev)) {
  1351. int err;
  1352. sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
  1353. num_ioc = 1;
  1354. sba_dev->chip_resv.name = "Astro Intr Ack";
  1355. sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
  1356. sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
  1357. err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
  1358. BUG_ON(err < 0);
  1359. } else if (IS_PLUTO(sba_dev->dev)) {
  1360. int err;
  1361. sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
  1362. num_ioc = 1;
  1363. sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
  1364. sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
  1365. sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
  1366. err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
  1367. WARN_ON(err < 0);
  1368. sba_dev->iommu_resv.name = "IOVA Space";
  1369. sba_dev->iommu_resv.start = 0x40000000UL;
  1370. sba_dev->iommu_resv.end = 0x50000000UL - 1;
  1371. err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
  1372. WARN_ON(err < 0);
  1373. } else {
  1374. /* IKE, REO */
  1375. sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
  1376. sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
  1377. num_ioc = 2;
  1378. /* TODO - LOOKUP Ike/Stretch chipset mem map */
  1379. }
  1380. /* XXX: What about Reo Grande? */
  1381. sba_dev->num_ioc = num_ioc;
  1382. for (i = 0; i < num_ioc; i++) {
  1383. void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
  1384. unsigned int j;
  1385. for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
  1386. /*
  1387. * Clear ROPE(N)_CONFIG AO bit.
  1388. * Disables "NT Ordering" (~= !"Relaxed Ordering")
  1389. * Overrides bit 1 in DMA Hint Sets.
  1390. * Improves netperf UDP_STREAM by ~10% for bcm5701.
  1391. */
  1392. if (IS_PLUTO(sba_dev->dev)) {
  1393. void __iomem *rope_cfg;
  1394. unsigned long cfg_val;
  1395. rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
  1396. cfg_val = READ_REG(rope_cfg);
  1397. cfg_val &= ~IOC_ROPE_AO;
  1398. WRITE_REG(cfg_val, rope_cfg);
  1399. }
  1400. /*
  1401. ** Make sure the box crashes on rope errors.
  1402. */
  1403. WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
  1404. }
  1405. /* flush out the last writes */
  1406. READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
  1407. DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
  1408. i,
  1409. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
  1410. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
  1411. );
  1412. DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
  1413. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
  1414. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
  1415. );
  1416. if (IS_PLUTO(sba_dev->dev)) {
  1417. sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
  1418. } else {
  1419. sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
  1420. }
  1421. }
  1422. }
  1423. static void
  1424. sba_common_init(struct sba_device *sba_dev)
  1425. {
  1426. int i;
  1427. /* add this one to the head of the list (order doesn't matter)
  1428. ** This will be useful for debugging - especially if we get coredumps
  1429. */
  1430. sba_dev->next = sba_list;
  1431. sba_list = sba_dev;
  1432. for(i=0; i< sba_dev->num_ioc; i++) {
  1433. int res_size;
  1434. #ifdef DEBUG_DMB_TRAP
  1435. extern void iterate_pages(unsigned long , unsigned long ,
  1436. void (*)(pte_t * , unsigned long),
  1437. unsigned long );
  1438. void set_data_memory_break(pte_t * , unsigned long);
  1439. #endif
  1440. /* resource map size dictated by pdir_size */
  1441. res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
  1442. /* Second part of PIRANHA BUG */
  1443. if (piranha_bad_128k) {
  1444. res_size -= (128*1024)/sizeof(u64);
  1445. }
  1446. res_size >>= 3; /* convert bit count to byte count */
  1447. DBG_INIT("%s() res_size 0x%x\n",
  1448. __func__, res_size);
  1449. sba_dev->ioc[i].res_size = res_size;
  1450. sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
  1451. #ifdef DEBUG_DMB_TRAP
  1452. iterate_pages( sba_dev->ioc[i].res_map, res_size,
  1453. set_data_memory_break, 0);
  1454. #endif
  1455. if (NULL == sba_dev->ioc[i].res_map)
  1456. {
  1457. panic("%s:%s() could not allocate resource map\n",
  1458. __FILE__, __func__ );
  1459. }
  1460. memset(sba_dev->ioc[i].res_map, 0, res_size);
  1461. /* next available IOVP - circular search */
  1462. sba_dev->ioc[i].res_hint = (unsigned long *)
  1463. &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
  1464. #ifdef ASSERT_PDIR_SANITY
  1465. /* Mark first bit busy - ie no IOVA 0 */
  1466. sba_dev->ioc[i].res_map[0] = 0x80;
  1467. sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
  1468. #endif
  1469. /* Third (and last) part of PIRANHA BUG */
  1470. if (piranha_bad_128k) {
  1471. /* region from +1408K to +1536 is un-usable. */
  1472. int idx_start = (1408*1024/sizeof(u64)) >> 3;
  1473. int idx_end = (1536*1024/sizeof(u64)) >> 3;
  1474. long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
  1475. long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
  1476. /* mark that part of the io pdir busy */
  1477. while (p_start < p_end)
  1478. *p_start++ = -1;
  1479. }
  1480. #ifdef DEBUG_DMB_TRAP
  1481. iterate_pages( sba_dev->ioc[i].res_map, res_size,
  1482. set_data_memory_break, 0);
  1483. iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
  1484. set_data_memory_break, 0);
  1485. #endif
  1486. DBG_INIT("%s() %d res_map %x %p\n",
  1487. __func__, i, res_size, sba_dev->ioc[i].res_map);
  1488. }
  1489. spin_lock_init(&sba_dev->sba_lock);
  1490. ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
  1491. #ifdef DEBUG_SBA_INIT
  1492. /*
  1493. * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
  1494. * (bit #61, big endian), we have to flush and sync every time
  1495. * IO-PDIR is changed in Ike/Astro.
  1496. */
  1497. if (ioc_needs_fdc) {
  1498. printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
  1499. } else {
  1500. printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
  1501. }
  1502. #endif
  1503. }
  1504. #ifdef CONFIG_PROC_FS
  1505. static int sba_proc_info(struct seq_file *m, void *p)
  1506. {
  1507. struct sba_device *sba_dev = sba_list;
  1508. struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
  1509. int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
  1510. #ifdef SBA_COLLECT_STATS
  1511. unsigned long avg = 0, min, max;
  1512. #endif
  1513. int i;
  1514. seq_printf(m, "%s rev %d.%d\n",
  1515. sba_dev->name,
  1516. (sba_dev->hw_rev & 0x7) + 1,
  1517. (sba_dev->hw_rev & 0x18) >> 3);
  1518. seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
  1519. (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
  1520. total_pages);
  1521. seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
  1522. ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
  1523. seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
  1524. READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
  1525. READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
  1526. READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE));
  1527. for (i=0; i<4; i++)
  1528. seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n",
  1529. i,
  1530. READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
  1531. READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
  1532. READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18));
  1533. #ifdef SBA_COLLECT_STATS
  1534. seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
  1535. total_pages - ioc->used_pages, ioc->used_pages,
  1536. (int)(ioc->used_pages * 100 / total_pages));
  1537. min = max = ioc->avg_search[0];
  1538. for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
  1539. avg += ioc->avg_search[i];
  1540. if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
  1541. if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
  1542. }
  1543. avg /= SBA_SEARCH_SAMPLE;
  1544. seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
  1545. min, avg, max);
  1546. seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
  1547. ioc->msingle_calls, ioc->msingle_pages,
  1548. (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
  1549. /* KLUGE - unmap_sg calls unmap_single for each mapped page */
  1550. min = ioc->usingle_calls;
  1551. max = ioc->usingle_pages - ioc->usg_pages;
  1552. seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
  1553. min, max, (int)((max * 1000)/min));
  1554. seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
  1555. ioc->msg_calls, ioc->msg_pages,
  1556. (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
  1557. seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
  1558. ioc->usg_calls, ioc->usg_pages,
  1559. (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
  1560. #endif
  1561. return 0;
  1562. }
  1563. static int
  1564. sba_proc_bitmap_info(struct seq_file *m, void *p)
  1565. {
  1566. struct sba_device *sba_dev = sba_list;
  1567. struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
  1568. seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
  1569. ioc->res_size, false);
  1570. seq_putc(m, '\n');
  1571. return 0;
  1572. }
  1573. #endif /* CONFIG_PROC_FS */
  1574. static const struct parisc_device_id sba_tbl[] __initconst = {
  1575. { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
  1576. { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
  1577. { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
  1578. { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
  1579. { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
  1580. { 0, }
  1581. };
  1582. static int sba_driver_callback(struct parisc_device *);
  1583. static struct parisc_driver sba_driver __refdata = {
  1584. .name = MODULE_NAME,
  1585. .id_table = sba_tbl,
  1586. .probe = sba_driver_callback,
  1587. };
  1588. /*
  1589. ** Determine if sba should claim this chip (return 0) or not (return 1).
  1590. ** If so, initialize the chip and tell other partners in crime they
  1591. ** have work to do.
  1592. */
  1593. static int __init sba_driver_callback(struct parisc_device *dev)
  1594. {
  1595. struct sba_device *sba_dev;
  1596. u32 func_class;
  1597. int i;
  1598. char *version;
  1599. void __iomem *sba_addr = ioremap(dev->hpa.start, SBA_FUNC_SIZE);
  1600. #ifdef CONFIG_PROC_FS
  1601. struct proc_dir_entry *root;
  1602. #endif
  1603. sba_dump_ranges(sba_addr);
  1604. /* Read HW Rev First */
  1605. func_class = READ_REG(sba_addr + SBA_FCLASS);
  1606. if (IS_ASTRO(dev)) {
  1607. unsigned long fclass;
  1608. static char astro_rev[]="Astro ?.?";
  1609. /* Astro is broken...Read HW Rev First */
  1610. fclass = READ_REG(sba_addr);
  1611. astro_rev[6] = '1' + (char) (fclass & 0x7);
  1612. astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
  1613. version = astro_rev;
  1614. } else if (IS_IKE(dev)) {
  1615. static char ike_rev[] = "Ike rev ?";
  1616. ike_rev[8] = '0' + (char) (func_class & 0xff);
  1617. version = ike_rev;
  1618. } else if (IS_PLUTO(dev)) {
  1619. static char pluto_rev[]="Pluto ?.?";
  1620. pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
  1621. pluto_rev[8] = '0' + (char) (func_class & 0x0f);
  1622. version = pluto_rev;
  1623. } else {
  1624. static char reo_rev[] = "REO rev ?";
  1625. reo_rev[8] = '0' + (char) (func_class & 0xff);
  1626. version = reo_rev;
  1627. }
  1628. if (!global_ioc_cnt) {
  1629. global_ioc_cnt = count_parisc_driver(&sba_driver);
  1630. /* Astro and Pluto have one IOC per SBA */
  1631. if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
  1632. global_ioc_cnt *= 2;
  1633. }
  1634. printk(KERN_INFO "%s found %s at 0x%llx\n",
  1635. MODULE_NAME, version, (unsigned long long)dev->hpa.start);
  1636. sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
  1637. if (!sba_dev) {
  1638. printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
  1639. return -ENOMEM;
  1640. }
  1641. parisc_set_drvdata(dev, sba_dev);
  1642. for(i=0; i<MAX_IOC; i++)
  1643. spin_lock_init(&(sba_dev->ioc[i].res_lock));
  1644. sba_dev->dev = dev;
  1645. sba_dev->hw_rev = func_class;
  1646. sba_dev->name = dev->name;
  1647. sba_dev->sba_hpa = sba_addr;
  1648. sba_get_pat_resources(sba_dev);
  1649. sba_hw_init(sba_dev);
  1650. sba_common_init(sba_dev);
  1651. hppa_dma_ops = &sba_ops;
  1652. #ifdef CONFIG_PROC_FS
  1653. switch (dev->id.hversion) {
  1654. case PLUTO_MCKINLEY_PORT:
  1655. root = proc_mckinley_root;
  1656. break;
  1657. case ASTRO_RUNWAY_PORT:
  1658. case IKE_MERCED_PORT:
  1659. default:
  1660. root = proc_runway_root;
  1661. break;
  1662. }
  1663. proc_create_single("sba_iommu", 0, root, sba_proc_info);
  1664. proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info);
  1665. #endif
  1666. return 0;
  1667. }
  1668. /*
  1669. ** One time initialization to let the world know the SBA was found.
  1670. ** This is the only routine which is NOT static.
  1671. ** Must be called exactly once before pci_init().
  1672. */
  1673. void __init sba_init(void)
  1674. {
  1675. register_parisc_driver(&sba_driver);
  1676. }
  1677. /**
  1678. * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
  1679. * @dev: The parisc device.
  1680. *
  1681. * Returns the appropriate IOMMU data for the given parisc PCI controller.
  1682. * This is cached and used later for PCI DMA Mapping.
  1683. */
  1684. void * sba_get_iommu(struct parisc_device *pci_hba)
  1685. {
  1686. struct parisc_device *sba_dev = parisc_parent(pci_hba);
  1687. struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
  1688. char t = sba_dev->id.hw_type;
  1689. int iocnum = (pci_hba->hw_path >> 3); /* rope # */
  1690. WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
  1691. return &(sba->ioc[iocnum]);
  1692. }
  1693. /**
  1694. * sba_directed_lmmio - return first directed LMMIO range routed to rope
  1695. * @pa_dev: The parisc device.
  1696. * @r: resource PCI host controller wants start/end fields assigned.
  1697. *
  1698. * For the given parisc PCI controller, determine if any direct ranges
  1699. * are routed down the corresponding rope.
  1700. */
  1701. void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
  1702. {
  1703. struct parisc_device *sba_dev = parisc_parent(pci_hba);
  1704. struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
  1705. char t = sba_dev->id.hw_type;
  1706. int i;
  1707. int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
  1708. BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
  1709. r->start = r->end = 0;
  1710. /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
  1711. for (i=0; i<4; i++) {
  1712. int base, size;
  1713. void __iomem *reg = sba->sba_hpa + i*0x18;
  1714. base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
  1715. if ((base & 1) == 0)
  1716. continue; /* not enabled */
  1717. size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
  1718. if ((size & (ROPES_PER_IOC-1)) != rope)
  1719. continue; /* directed down different rope */
  1720. r->start = (base & ~1UL) | PCI_F_EXTEND;
  1721. size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
  1722. r->end = r->start + size;
  1723. r->flags = IORESOURCE_MEM;
  1724. }
  1725. }
  1726. /**
  1727. * sba_distributed_lmmio - return portion of distributed LMMIO range
  1728. * @pa_dev: The parisc device.
  1729. * @r: resource PCI host controller wants start/end fields assigned.
  1730. *
  1731. * For the given parisc PCI controller, return portion of distributed LMMIO
  1732. * range. The distributed LMMIO is always present and it's just a question
  1733. * of the base address and size of the range.
  1734. */
  1735. void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
  1736. {
  1737. struct parisc_device *sba_dev = parisc_parent(pci_hba);
  1738. struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
  1739. char t = sba_dev->id.hw_type;
  1740. int base, size;
  1741. int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
  1742. BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
  1743. r->start = r->end = 0;
  1744. base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
  1745. if ((base & 1) == 0) {
  1746. BUG(); /* Gah! Distr Range wasn't enabled! */
  1747. return;
  1748. }
  1749. r->start = (base & ~1UL) | PCI_F_EXTEND;
  1750. size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
  1751. r->start += rope * (size + 1); /* adjust base for this rope */
  1752. r->end = r->start + size;
  1753. r->flags = IORESOURCE_MEM;
  1754. }