gsc.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Interrupt management for most GSC and related devices.
  4. *
  5. * (c) Copyright 1999 Alex deVries for The Puffin Group
  6. * (c) Copyright 1999 Grant Grundler for Hewlett-Packard
  7. * (c) Copyright 1999 Matthew Wilcox
  8. * (c) Copyright 2000 Helge Deller
  9. * (c) Copyright 2001 Matthew Wilcox for Hewlett-Packard
  10. */
  11. #include <linux/bitops.h>
  12. #include <linux/errno.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/ioport.h>
  16. #include <linux/module.h>
  17. #include <linux/types.h>
  18. #include <asm/hardware.h>
  19. #include <asm/io.h>
  20. #include "gsc.h"
  21. #undef DEBUG
  22. #ifdef DEBUG
  23. #define DEBPRINTK printk
  24. #else
  25. #define DEBPRINTK(x,...)
  26. #endif
  27. int gsc_alloc_irq(struct gsc_irq *i)
  28. {
  29. int irq = txn_alloc_irq(GSC_EIM_WIDTH);
  30. if (irq < 0) {
  31. printk("cannot get irq\n");
  32. return irq;
  33. }
  34. i->txn_addr = txn_alloc_addr(irq);
  35. i->txn_data = txn_alloc_data(irq);
  36. i->irq = irq;
  37. return irq;
  38. }
  39. int gsc_claim_irq(struct gsc_irq *i, int irq)
  40. {
  41. int c = irq;
  42. irq += CPU_IRQ_BASE; /* virtualize the IRQ first */
  43. irq = txn_claim_irq(irq);
  44. if (irq < 0) {
  45. printk("cannot claim irq %d\n", c);
  46. return irq;
  47. }
  48. i->txn_addr = txn_alloc_addr(irq);
  49. i->txn_data = txn_alloc_data(irq);
  50. i->irq = irq;
  51. return irq;
  52. }
  53. EXPORT_SYMBOL(gsc_alloc_irq);
  54. EXPORT_SYMBOL(gsc_claim_irq);
  55. /* Common interrupt demultiplexer used by Asp, Lasi & Wax. */
  56. irqreturn_t gsc_asic_intr(int gsc_asic_irq, void *dev)
  57. {
  58. unsigned long irr;
  59. struct gsc_asic *gsc_asic = dev;
  60. irr = gsc_readl(gsc_asic->hpa + OFFSET_IRR);
  61. if (irr == 0)
  62. return IRQ_NONE;
  63. DEBPRINTK("%s intr, mask=0x%x\n", gsc_asic->name, irr);
  64. do {
  65. int local_irq = __ffs(irr);
  66. unsigned int irq = gsc_asic->global_irq[local_irq];
  67. generic_handle_irq(irq);
  68. irr &= ~(1 << local_irq);
  69. } while (irr);
  70. return IRQ_HANDLED;
  71. }
  72. int gsc_find_local_irq(unsigned int irq, int *global_irqs, int limit)
  73. {
  74. int local_irq;
  75. for (local_irq = 0; local_irq < limit; local_irq++) {
  76. if (global_irqs[local_irq] == irq)
  77. return local_irq;
  78. }
  79. return NO_IRQ;
  80. }
  81. static void gsc_asic_mask_irq(struct irq_data *d)
  82. {
  83. struct gsc_asic *irq_dev = irq_data_get_irq_chip_data(d);
  84. int local_irq = gsc_find_local_irq(d->irq, irq_dev->global_irq, 32);
  85. u32 imr;
  86. DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, d->irq,
  87. irq_dev->name, imr);
  88. /* Disable the IRQ line by clearing the bit in the IMR */
  89. imr = gsc_readl(irq_dev->hpa + OFFSET_IMR);
  90. imr &= ~(1 << local_irq);
  91. gsc_writel(imr, irq_dev->hpa + OFFSET_IMR);
  92. }
  93. static void gsc_asic_unmask_irq(struct irq_data *d)
  94. {
  95. struct gsc_asic *irq_dev = irq_data_get_irq_chip_data(d);
  96. int local_irq = gsc_find_local_irq(d->irq, irq_dev->global_irq, 32);
  97. u32 imr;
  98. DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, d->irq,
  99. irq_dev->name, imr);
  100. /* Enable the IRQ line by setting the bit in the IMR */
  101. imr = gsc_readl(irq_dev->hpa + OFFSET_IMR);
  102. imr |= 1 << local_irq;
  103. gsc_writel(imr, irq_dev->hpa + OFFSET_IMR);
  104. /*
  105. * FIXME: read IPR to make sure the IRQ isn't already pending.
  106. * If so, we need to read IRR and manually call do_irq().
  107. */
  108. }
  109. #ifdef CONFIG_SMP
  110. static int gsc_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
  111. bool force)
  112. {
  113. struct gsc_asic *gsc_dev = irq_data_get_irq_chip_data(d);
  114. struct cpumask tmask;
  115. int cpu_irq;
  116. if (!cpumask_and(&tmask, dest, cpu_online_mask))
  117. return -EINVAL;
  118. cpu_irq = cpu_check_affinity(d, &tmask);
  119. if (cpu_irq < 0)
  120. return cpu_irq;
  121. gsc_dev->gsc_irq.txn_addr = txn_affinity_addr(d->irq, cpu_irq);
  122. gsc_dev->eim = ((u32) gsc_dev->gsc_irq.txn_addr) | gsc_dev->gsc_irq.txn_data;
  123. /* switch IRQ's for devices below LASI/WAX to other CPU */
  124. gsc_writel(gsc_dev->eim, gsc_dev->hpa + OFFSET_IAR);
  125. irq_data_update_effective_affinity(d, &tmask);
  126. return IRQ_SET_MASK_OK;
  127. }
  128. #endif
  129. static struct irq_chip gsc_asic_interrupt_type = {
  130. .name = "GSC-ASIC",
  131. .irq_unmask = gsc_asic_unmask_irq,
  132. .irq_mask = gsc_asic_mask_irq,
  133. #ifdef CONFIG_SMP
  134. .irq_set_affinity = gsc_set_affinity_irq,
  135. #endif
  136. };
  137. int gsc_assign_irq(struct irq_chip *type, void *data)
  138. {
  139. static int irq = GSC_IRQ_BASE;
  140. if (irq > GSC_IRQ_MAX)
  141. return NO_IRQ;
  142. irq_set_chip_and_handler(irq, type, handle_simple_irq);
  143. irq_set_chip_data(irq, data);
  144. return irq++;
  145. }
  146. void gsc_asic_assign_irq(struct gsc_asic *asic, int local_irq, int *irqp)
  147. {
  148. int irq = asic->global_irq[local_irq];
  149. if (irq <= 0) {
  150. irq = gsc_assign_irq(&gsc_asic_interrupt_type, asic);
  151. if (irq == NO_IRQ)
  152. return;
  153. asic->global_irq[local_irq] = irq;
  154. }
  155. *irqp = irq;
  156. }
  157. struct gsc_fixup_struct {
  158. void (*choose_irq)(struct parisc_device *, void *);
  159. void *ctrl;
  160. };
  161. static int gsc_fixup_irqs_callback(struct device *dev, void *data)
  162. {
  163. struct parisc_device *padev = to_parisc_device(dev);
  164. struct gsc_fixup_struct *gf = data;
  165. /* work-around for 715/64 and others which have parent
  166. at path [5] and children at path [5/0/x] */
  167. if (padev->id.hw_type == HPHW_FAULTY)
  168. gsc_fixup_irqs(padev, gf->ctrl, gf->choose_irq);
  169. gf->choose_irq(padev, gf->ctrl);
  170. return 0;
  171. }
  172. void gsc_fixup_irqs(struct parisc_device *parent, void *ctrl,
  173. void (*choose_irq)(struct parisc_device *, void *))
  174. {
  175. struct gsc_fixup_struct data = {
  176. .choose_irq = choose_irq,
  177. .ctrl = ctrl,
  178. };
  179. device_for_each_child(&parent->dev, &data, gsc_fixup_irqs_callback);
  180. }
  181. int gsc_common_setup(struct parisc_device *parent, struct gsc_asic *gsc_asic)
  182. {
  183. struct resource *res;
  184. int i;
  185. gsc_asic->gsc = parent;
  186. /* Initialise local irq -> global irq mapping */
  187. for (i = 0; i < 32; i++) {
  188. gsc_asic->global_irq[i] = NO_IRQ;
  189. }
  190. /* allocate resource region */
  191. res = request_mem_region(gsc_asic->hpa, 0x100000, gsc_asic->name);
  192. if (res) {
  193. res->flags = IORESOURCE_MEM; /* do not mark it busy ! */
  194. }
  195. #if 0
  196. printk(KERN_WARNING "%s IRQ %d EIM 0x%x", gsc_asic->name,
  197. parent->irq, gsc_asic->eim);
  198. if (gsc_readl(gsc_asic->hpa + OFFSET_IMR))
  199. printk(" IMR is non-zero! (0x%x)",
  200. gsc_readl(gsc_asic->hpa + OFFSET_IMR));
  201. printk("\n");
  202. #endif
  203. return 0;
  204. }
  205. extern struct parisc_driver lasi_driver;
  206. extern struct parisc_driver asp_driver;
  207. extern struct parisc_driver wax_driver;
  208. void __init gsc_init(void)
  209. {
  210. #ifdef CONFIG_GSC_LASI
  211. register_parisc_driver(&lasi_driver);
  212. register_parisc_driver(&asp_driver);
  213. #endif
  214. #ifdef CONFIG_GSC_WAX
  215. register_parisc_driver(&wax_driver);
  216. #endif
  217. }