vf610-ocotp.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Toradex AG.
  4. *
  5. * Author: Sanchayan Maity <[email protected]>
  6. *
  7. * Based on the barebox ocotp driver,
  8. * Copyright (c) 2010 Baruch Siach <[email protected]>
  9. * Orex Computed Radiography
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/nvmem-provider.h>
  17. #include <linux/of.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. /* OCOTP Register Offsets */
  21. #define OCOTP_CTRL_REG 0x00
  22. #define OCOTP_CTRL_SET 0x04
  23. #define OCOTP_CTRL_CLR 0x08
  24. #define OCOTP_TIMING 0x10
  25. #define OCOTP_DATA 0x20
  26. #define OCOTP_READ_CTRL_REG 0x30
  27. #define OCOTP_READ_FUSE_DATA 0x40
  28. /* OCOTP Register bits and masks */
  29. #define OCOTP_CTRL_WR_UNLOCK 16
  30. #define OCOTP_CTRL_WR_UNLOCK_KEY 0x3E77
  31. #define OCOTP_CTRL_WR_UNLOCK_MASK GENMASK(31, 16)
  32. #define OCOTP_CTRL_ADDR 0
  33. #define OCOTP_CTRL_ADDR_MASK GENMASK(6, 0)
  34. #define OCOTP_CTRL_RELOAD_SHADOWS BIT(10)
  35. #define OCOTP_CTRL_ERR BIT(9)
  36. #define OCOTP_CTRL_BUSY BIT(8)
  37. #define OCOTP_TIMING_STROBE_READ 16
  38. #define OCOTP_TIMING_STROBE_READ_MASK GENMASK(21, 16)
  39. #define OCOTP_TIMING_RELAX 12
  40. #define OCOTP_TIMING_RELAX_MASK GENMASK(15, 12)
  41. #define OCOTP_TIMING_STROBE_PROG 0
  42. #define OCOTP_TIMING_STROBE_PROG_MASK GENMASK(11, 0)
  43. #define OCOTP_READ_CTRL_READ_FUSE 0x1
  44. #define VF610_OCOTP_TIMEOUT 100000
  45. #define BF(value, field) (((value) << field) & field##_MASK)
  46. #define DEF_RELAX 20
  47. static const int base_to_fuse_addr_mappings[][2] = {
  48. {0x400, 0x00},
  49. {0x410, 0x01},
  50. {0x420, 0x02},
  51. {0x450, 0x05},
  52. {0x4F0, 0x0F},
  53. {0x600, 0x20},
  54. {0x610, 0x21},
  55. {0x620, 0x22},
  56. {0x630, 0x23},
  57. {0x640, 0x24},
  58. {0x650, 0x25},
  59. {0x660, 0x26},
  60. {0x670, 0x27},
  61. {0x6F0, 0x2F},
  62. {0x880, 0x38},
  63. {0x890, 0x39},
  64. {0x8A0, 0x3A},
  65. {0x8B0, 0x3B},
  66. {0x8C0, 0x3C},
  67. {0x8D0, 0x3D},
  68. {0x8E0, 0x3E},
  69. {0x8F0, 0x3F},
  70. {0xC80, 0x78},
  71. {0xC90, 0x79},
  72. {0xCA0, 0x7A},
  73. {0xCB0, 0x7B},
  74. {0xCC0, 0x7C},
  75. {0xCD0, 0x7D},
  76. {0xCE0, 0x7E},
  77. {0xCF0, 0x7F},
  78. };
  79. struct vf610_ocotp {
  80. void __iomem *base;
  81. struct clk *clk;
  82. struct device *dev;
  83. struct nvmem_device *nvmem;
  84. int timing;
  85. };
  86. static int vf610_ocotp_wait_busy(void __iomem *base)
  87. {
  88. int timeout = VF610_OCOTP_TIMEOUT;
  89. while ((readl(base) & OCOTP_CTRL_BUSY) && --timeout)
  90. udelay(10);
  91. if (!timeout) {
  92. writel(OCOTP_CTRL_ERR, base + OCOTP_CTRL_CLR);
  93. return -ETIMEDOUT;
  94. }
  95. udelay(10);
  96. return 0;
  97. }
  98. static int vf610_ocotp_calculate_timing(struct vf610_ocotp *ocotp_dev)
  99. {
  100. u32 clk_rate;
  101. u32 relax, strobe_read, strobe_prog;
  102. u32 timing;
  103. clk_rate = clk_get_rate(ocotp_dev->clk);
  104. /* Refer section OTP read/write timing parameters in TRM */
  105. relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
  106. strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
  107. strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
  108. timing = BF(relax, OCOTP_TIMING_RELAX);
  109. timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ);
  110. timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG);
  111. return timing;
  112. }
  113. static int vf610_get_fuse_address(int base_addr_offset)
  114. {
  115. int i;
  116. for (i = 0; i < ARRAY_SIZE(base_to_fuse_addr_mappings); i++) {
  117. if (base_to_fuse_addr_mappings[i][0] == base_addr_offset)
  118. return base_to_fuse_addr_mappings[i][1];
  119. }
  120. return -EINVAL;
  121. }
  122. static int vf610_ocotp_read(void *context, unsigned int offset,
  123. void *val, size_t bytes)
  124. {
  125. struct vf610_ocotp *ocotp = context;
  126. void __iomem *base = ocotp->base;
  127. u32 reg, *buf = val;
  128. int fuse_addr;
  129. int ret;
  130. while (bytes > 0) {
  131. fuse_addr = vf610_get_fuse_address(offset);
  132. if (fuse_addr > 0) {
  133. writel(ocotp->timing, base + OCOTP_TIMING);
  134. ret = vf610_ocotp_wait_busy(base + OCOTP_CTRL_REG);
  135. if (ret)
  136. return ret;
  137. reg = readl(base + OCOTP_CTRL_REG);
  138. reg &= ~OCOTP_CTRL_ADDR_MASK;
  139. reg &= ~OCOTP_CTRL_WR_UNLOCK_MASK;
  140. reg |= BF(fuse_addr, OCOTP_CTRL_ADDR);
  141. writel(reg, base + OCOTP_CTRL_REG);
  142. writel(OCOTP_READ_CTRL_READ_FUSE,
  143. base + OCOTP_READ_CTRL_REG);
  144. ret = vf610_ocotp_wait_busy(base + OCOTP_CTRL_REG);
  145. if (ret)
  146. return ret;
  147. if (readl(base) & OCOTP_CTRL_ERR) {
  148. dev_dbg(ocotp->dev, "Error reading from fuse address %x\n",
  149. fuse_addr);
  150. writel(OCOTP_CTRL_ERR, base + OCOTP_CTRL_CLR);
  151. }
  152. /*
  153. * In case of error, we do not abort and expect to read
  154. * 0xBADABADA as mentioned by the TRM. We just read this
  155. * value and return.
  156. */
  157. *buf = readl(base + OCOTP_READ_FUSE_DATA);
  158. } else {
  159. *buf = 0;
  160. }
  161. buf++;
  162. bytes -= 4;
  163. offset += 4;
  164. }
  165. return 0;
  166. }
  167. static struct nvmem_config ocotp_config = {
  168. .name = "ocotp",
  169. .stride = 4,
  170. .word_size = 4,
  171. .reg_read = vf610_ocotp_read,
  172. };
  173. static const struct of_device_id ocotp_of_match[] = {
  174. { .compatible = "fsl,vf610-ocotp", },
  175. {/* sentinel */},
  176. };
  177. MODULE_DEVICE_TABLE(of, ocotp_of_match);
  178. static int vf610_ocotp_probe(struct platform_device *pdev)
  179. {
  180. struct device *dev = &pdev->dev;
  181. struct resource *res;
  182. struct vf610_ocotp *ocotp_dev;
  183. ocotp_dev = devm_kzalloc(dev, sizeof(struct vf610_ocotp), GFP_KERNEL);
  184. if (!ocotp_dev)
  185. return -ENOMEM;
  186. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  187. ocotp_dev->base = devm_ioremap_resource(dev, res);
  188. if (IS_ERR(ocotp_dev->base))
  189. return PTR_ERR(ocotp_dev->base);
  190. ocotp_dev->clk = devm_clk_get(dev, NULL);
  191. if (IS_ERR(ocotp_dev->clk)) {
  192. dev_err(dev, "failed getting clock, err = %ld\n",
  193. PTR_ERR(ocotp_dev->clk));
  194. return PTR_ERR(ocotp_dev->clk);
  195. }
  196. ocotp_dev->dev = dev;
  197. ocotp_dev->timing = vf610_ocotp_calculate_timing(ocotp_dev);
  198. ocotp_config.size = resource_size(res);
  199. ocotp_config.priv = ocotp_dev;
  200. ocotp_config.dev = dev;
  201. ocotp_dev->nvmem = devm_nvmem_register(dev, &ocotp_config);
  202. return PTR_ERR_OR_ZERO(ocotp_dev->nvmem);
  203. }
  204. static struct platform_driver vf610_ocotp_driver = {
  205. .probe = vf610_ocotp_probe,
  206. .driver = {
  207. .name = "vf610-ocotp",
  208. .of_match_table = ocotp_of_match,
  209. },
  210. };
  211. module_platform_driver(vf610_ocotp_driver);
  212. MODULE_AUTHOR("Sanchayan Maity <[email protected]>");
  213. MODULE_DESCRIPTION("Vybrid OCOTP driver");
  214. MODULE_LICENSE("GPL v2");