hwio.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Low-level I/O functions.
  4. *
  5. * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
  6. * Copyright (c) 2010, ST-Ericsson
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/align.h>
  12. #include "hwio.h"
  13. #include "wfx.h"
  14. #include "bus.h"
  15. #include "traces.h"
  16. #define WFX_HIF_BUFFER_SIZE 0x2000
  17. static int wfx_read32(struct wfx_dev *wdev, int reg, u32 *val)
  18. {
  19. int ret;
  20. __le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
  21. *val = ~0; /* Never return undefined value */
  22. if (!tmp)
  23. return -ENOMEM;
  24. ret = wdev->hwbus_ops->copy_from_io(wdev->hwbus_priv, reg, tmp, sizeof(u32));
  25. if (ret >= 0)
  26. *val = le32_to_cpu(*tmp);
  27. kfree(tmp);
  28. if (ret)
  29. dev_err(wdev->dev, "%s: bus communication error: %d\n", __func__, ret);
  30. return ret;
  31. }
  32. static int wfx_write32(struct wfx_dev *wdev, int reg, u32 val)
  33. {
  34. int ret;
  35. __le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
  36. if (!tmp)
  37. return -ENOMEM;
  38. *tmp = cpu_to_le32(val);
  39. ret = wdev->hwbus_ops->copy_to_io(wdev->hwbus_priv, reg, tmp, sizeof(u32));
  40. kfree(tmp);
  41. if (ret)
  42. dev_err(wdev->dev, "%s: bus communication error: %d\n", __func__, ret);
  43. return ret;
  44. }
  45. static int wfx_read32_locked(struct wfx_dev *wdev, int reg, u32 *val)
  46. {
  47. int ret;
  48. wdev->hwbus_ops->lock(wdev->hwbus_priv);
  49. ret = wfx_read32(wdev, reg, val);
  50. _trace_io_read32(reg, *val);
  51. wdev->hwbus_ops->unlock(wdev->hwbus_priv);
  52. return ret;
  53. }
  54. static int wfx_write32_locked(struct wfx_dev *wdev, int reg, u32 val)
  55. {
  56. int ret;
  57. wdev->hwbus_ops->lock(wdev->hwbus_priv);
  58. ret = wfx_write32(wdev, reg, val);
  59. _trace_io_write32(reg, val);
  60. wdev->hwbus_ops->unlock(wdev->hwbus_priv);
  61. return ret;
  62. }
  63. static int wfx_write32_bits_locked(struct wfx_dev *wdev, int reg, u32 mask, u32 val)
  64. {
  65. int ret;
  66. u32 val_r, val_w;
  67. WARN_ON(~mask & val);
  68. val &= mask;
  69. wdev->hwbus_ops->lock(wdev->hwbus_priv);
  70. ret = wfx_read32(wdev, reg, &val_r);
  71. _trace_io_read32(reg, val_r);
  72. if (ret < 0)
  73. goto err;
  74. val_w = (val_r & ~mask) | val;
  75. if (val_w != val_r) {
  76. ret = wfx_write32(wdev, reg, val_w);
  77. _trace_io_write32(reg, val_w);
  78. }
  79. err:
  80. wdev->hwbus_ops->unlock(wdev->hwbus_priv);
  81. return ret;
  82. }
  83. static int wfx_indirect_read(struct wfx_dev *wdev, int reg, u32 addr, void *buf, size_t len)
  84. {
  85. int ret;
  86. int i;
  87. u32 cfg;
  88. u32 prefetch;
  89. WARN_ON(len >= WFX_HIF_BUFFER_SIZE);
  90. WARN_ON(reg != WFX_REG_AHB_DPORT && reg != WFX_REG_SRAM_DPORT);
  91. if (reg == WFX_REG_AHB_DPORT)
  92. prefetch = CFG_PREFETCH_AHB;
  93. else if (reg == WFX_REG_SRAM_DPORT)
  94. prefetch = CFG_PREFETCH_SRAM;
  95. else
  96. return -ENODEV;
  97. ret = wfx_write32(wdev, WFX_REG_BASE_ADDR, addr);
  98. if (ret < 0)
  99. goto err;
  100. ret = wfx_read32(wdev, WFX_REG_CONFIG, &cfg);
  101. if (ret < 0)
  102. goto err;
  103. ret = wfx_write32(wdev, WFX_REG_CONFIG, cfg | prefetch);
  104. if (ret < 0)
  105. goto err;
  106. for (i = 0; i < 20; i++) {
  107. ret = wfx_read32(wdev, WFX_REG_CONFIG, &cfg);
  108. if (ret < 0)
  109. goto err;
  110. if (!(cfg & prefetch))
  111. break;
  112. usleep_range(200, 250);
  113. }
  114. if (i == 20) {
  115. ret = -ETIMEDOUT;
  116. goto err;
  117. }
  118. ret = wdev->hwbus_ops->copy_from_io(wdev->hwbus_priv, reg, buf, len);
  119. err:
  120. if (ret < 0)
  121. memset(buf, 0xFF, len); /* Never return undefined value */
  122. return ret;
  123. }
  124. static int wfx_indirect_write(struct wfx_dev *wdev, int reg, u32 addr,
  125. const void *buf, size_t len)
  126. {
  127. int ret;
  128. WARN_ON(len >= WFX_HIF_BUFFER_SIZE);
  129. WARN_ON(reg != WFX_REG_AHB_DPORT && reg != WFX_REG_SRAM_DPORT);
  130. ret = wfx_write32(wdev, WFX_REG_BASE_ADDR, addr);
  131. if (ret < 0)
  132. return ret;
  133. return wdev->hwbus_ops->copy_to_io(wdev->hwbus_priv, reg, buf, len);
  134. }
  135. static int wfx_indirect_read_locked(struct wfx_dev *wdev, int reg, u32 addr,
  136. void *buf, size_t len)
  137. {
  138. int ret;
  139. wdev->hwbus_ops->lock(wdev->hwbus_priv);
  140. ret = wfx_indirect_read(wdev, reg, addr, buf, len);
  141. _trace_io_ind_read(reg, addr, buf, len);
  142. wdev->hwbus_ops->unlock(wdev->hwbus_priv);
  143. return ret;
  144. }
  145. static int wfx_indirect_write_locked(struct wfx_dev *wdev, int reg, u32 addr,
  146. const void *buf, size_t len)
  147. {
  148. int ret;
  149. wdev->hwbus_ops->lock(wdev->hwbus_priv);
  150. ret = wfx_indirect_write(wdev, reg, addr, buf, len);
  151. _trace_io_ind_write(reg, addr, buf, len);
  152. wdev->hwbus_ops->unlock(wdev->hwbus_priv);
  153. return ret;
  154. }
  155. static int wfx_indirect_read32_locked(struct wfx_dev *wdev, int reg, u32 addr, u32 *val)
  156. {
  157. int ret;
  158. __le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
  159. if (!tmp)
  160. return -ENOMEM;
  161. wdev->hwbus_ops->lock(wdev->hwbus_priv);
  162. ret = wfx_indirect_read(wdev, reg, addr, tmp, sizeof(u32));
  163. *val = le32_to_cpu(*tmp);
  164. _trace_io_ind_read32(reg, addr, *val);
  165. wdev->hwbus_ops->unlock(wdev->hwbus_priv);
  166. kfree(tmp);
  167. return ret;
  168. }
  169. static int wfx_indirect_write32_locked(struct wfx_dev *wdev, int reg, u32 addr, u32 val)
  170. {
  171. int ret;
  172. __le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
  173. if (!tmp)
  174. return -ENOMEM;
  175. *tmp = cpu_to_le32(val);
  176. wdev->hwbus_ops->lock(wdev->hwbus_priv);
  177. ret = wfx_indirect_write(wdev, reg, addr, tmp, sizeof(u32));
  178. _trace_io_ind_write32(reg, addr, val);
  179. wdev->hwbus_ops->unlock(wdev->hwbus_priv);
  180. kfree(tmp);
  181. return ret;
  182. }
  183. int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t len)
  184. {
  185. int ret;
  186. WARN(!IS_ALIGNED((uintptr_t)buf, 4), "unaligned buffer");
  187. wdev->hwbus_ops->lock(wdev->hwbus_priv);
  188. ret = wdev->hwbus_ops->copy_from_io(wdev->hwbus_priv, WFX_REG_IN_OUT_QUEUE, buf, len);
  189. _trace_io_read(WFX_REG_IN_OUT_QUEUE, buf, len);
  190. wdev->hwbus_ops->unlock(wdev->hwbus_priv);
  191. if (ret)
  192. dev_err(wdev->dev, "%s: bus communication error: %d\n", __func__, ret);
  193. return ret;
  194. }
  195. int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t len)
  196. {
  197. int ret;
  198. WARN(!IS_ALIGNED((uintptr_t)buf, 4), "unaligned buffer");
  199. wdev->hwbus_ops->lock(wdev->hwbus_priv);
  200. ret = wdev->hwbus_ops->copy_to_io(wdev->hwbus_priv, WFX_REG_IN_OUT_QUEUE, buf, len);
  201. _trace_io_write(WFX_REG_IN_OUT_QUEUE, buf, len);
  202. wdev->hwbus_ops->unlock(wdev->hwbus_priv);
  203. if (ret)
  204. dev_err(wdev->dev, "%s: bus communication error: %d\n", __func__, ret);
  205. return ret;
  206. }
  207. int wfx_sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
  208. {
  209. return wfx_indirect_read_locked(wdev, WFX_REG_SRAM_DPORT, addr, buf, len);
  210. }
  211. int wfx_ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
  212. {
  213. return wfx_indirect_read_locked(wdev, WFX_REG_AHB_DPORT, addr, buf, len);
  214. }
  215. int wfx_sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len)
  216. {
  217. return wfx_indirect_write_locked(wdev, WFX_REG_SRAM_DPORT, addr, buf, len);
  218. }
  219. int wfx_ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len)
  220. {
  221. return wfx_indirect_write_locked(wdev, WFX_REG_AHB_DPORT, addr, buf, len);
  222. }
  223. int wfx_sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
  224. {
  225. return wfx_indirect_read32_locked(wdev, WFX_REG_SRAM_DPORT, addr, val);
  226. }
  227. int wfx_ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
  228. {
  229. return wfx_indirect_read32_locked(wdev, WFX_REG_AHB_DPORT, addr, val);
  230. }
  231. int wfx_sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
  232. {
  233. return wfx_indirect_write32_locked(wdev, WFX_REG_SRAM_DPORT, addr, val);
  234. }
  235. int wfx_ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
  236. {
  237. return wfx_indirect_write32_locked(wdev, WFX_REG_AHB_DPORT, addr, val);
  238. }
  239. int wfx_config_reg_read(struct wfx_dev *wdev, u32 *val)
  240. {
  241. return wfx_read32_locked(wdev, WFX_REG_CONFIG, val);
  242. }
  243. int wfx_config_reg_write(struct wfx_dev *wdev, u32 val)
  244. {
  245. return wfx_write32_locked(wdev, WFX_REG_CONFIG, val);
  246. }
  247. int wfx_config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
  248. {
  249. return wfx_write32_bits_locked(wdev, WFX_REG_CONFIG, mask, val);
  250. }
  251. int wfx_control_reg_read(struct wfx_dev *wdev, u32 *val)
  252. {
  253. return wfx_read32_locked(wdev, WFX_REG_CONTROL, val);
  254. }
  255. int wfx_control_reg_write(struct wfx_dev *wdev, u32 val)
  256. {
  257. return wfx_write32_locked(wdev, WFX_REG_CONTROL, val);
  258. }
  259. int wfx_control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
  260. {
  261. return wfx_write32_bits_locked(wdev, WFX_REG_CONTROL, mask, val);
  262. }
  263. int wfx_igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val)
  264. {
  265. int ret;
  266. *val = ~0; /* Never return undefined value */
  267. ret = wfx_write32_locked(wdev, WFX_REG_SET_GEN_R_W, IGPR_RW | index << 24);
  268. if (ret)
  269. return ret;
  270. ret = wfx_read32_locked(wdev, WFX_REG_SET_GEN_R_W, val);
  271. if (ret)
  272. return ret;
  273. *val &= IGPR_VALUE;
  274. return ret;
  275. }
  276. int wfx_igpr_reg_write(struct wfx_dev *wdev, int index, u32 val)
  277. {
  278. return wfx_write32_locked(wdev, WFX_REG_SET_GEN_R_W, index << 24 | val);
  279. }