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android_kernel_...
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drivers
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wireless
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realtek
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rtw89
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rtw8852a.h

rtw8852a.h 2.4 KB
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  1. /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
    2. 

  2. /* Copyright(c) 2019-2020  Realtek Corporation
    3. 

  3.  */
    4. 

  4. 

  5. #ifndef __RTW89_8852A_H__
    6. 

  6. #define __RTW89_8852A_H__
    7. 

  7. 

  8. #include "core.h"
    9. 

  9. 

  10. #define RF_PATH_NUM_8852A 2
    11. 

  11. #define NTX_NUM_8852A 2
    12. 

  12. 

  13. enum rtw8852a_pmac_mode {
    14. 

  14. 	NONE_TEST,
    15. 

  15. 	PKTS_TX,
    16. 

  16. 	PKTS_RX,
    17. 

  17. 	CONT_TX
    18. 

  18. };
    19. 

  19. 

  20. struct rtw8852au_efuse {
    21. 

  21. 	u8 rsvd[0x38];
    22. 

  22. 	u8 mac_addr[ETH_ALEN];
    23. 

  23. };
    24. 

  24. 

  25. struct rtw8852ae_efuse {
    26. 

  26. 	u8 mac_addr[ETH_ALEN];
    27. 

  27. };
    28. 

  28. 

  29. struct rtw8852a_tssi_offset {
    30. 

  30. 	u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
    31. 

  31. 	u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
    32. 

  32. 	u8 rsvd[7];
    33. 

  33. 	u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
    34. 

  34. } __packed;
    35. 

  35. 

  36. struct rtw8852a_efuse {
    37. 

  37. 	u8 rsvd[0x210];
    38. 

  38. 	struct rtw8852a_tssi_offset path_a_tssi;
    39. 

  39. 	u8 rsvd1[10];
    40. 

  40. 	struct rtw8852a_tssi_offset path_b_tssi;
    41. 

  41. 	u8 rsvd2[94];
    42. 

  42. 	u8 channel_plan;
    43. 

  43. 	u8 xtal_k;
    44. 

  44. 	u8 rsvd3;
    45. 

  45. 	u8 iqk_lck;
    46. 

  46. 	u8 rsvd4[5];
    47. 

  47. 	u8 reg_setting:2;
    48. 

  48. 	u8 tx_diversity:1;
    49. 

  49. 	u8 rx_diversity:2;
    50. 

  50. 	u8 ac_mode:1;
    51. 

  51. 	u8 module_type:2;
    52. 

  52. 	u8 rsvd5;
    53. 

  53. 	u8 shared_ant:1;
    54. 

  54. 	u8 coex_type:3;
    55. 

  55. 	u8 ant_iso:1;
    56. 

  56. 	u8 radio_on_off:1;
    57. 

  57. 	u8 rsvd6:2;
    58. 

  58. 	u8 eeprom_version;
    59. 

  59. 	u8 customer_id;
    60. 

  60. 	u8 tx_bb_swing_2g;
    61. 

  61. 	u8 tx_bb_swing_5g;
    62. 

  62. 	u8 tx_cali_pwr_trk_mode;
    63. 

  63. 	u8 trx_path_selection;
    64. 

  64. 	u8 rfe_type;
    65. 

  65. 	u8 country_code[2];
    66. 

  66. 	u8 rsvd7[3];
    67. 

  67. 	u8 path_a_therm;
    68. 

  68. 	u8 path_b_therm;
    69. 

  69. 	u8 rsvd8[46];
    70. 

  70. 	u8 path_a_cck_pwr_idx[6];
    71. 

  71. 	u8 path_a_bw40_1tx_pwr_idx[5];
    72. 

  72. 	u8 path_a_ofdm_1tx_pwr_idx_diff:4;
    73. 

  73. 	u8 path_a_bw20_1tx_pwr_idx_diff:4;
    74. 

  74. 	u8 path_a_bw20_2tx_pwr_idx_diff:4;
    75. 

  75. 	u8 path_a_bw40_2tx_pwr_idx_diff:4;
    76. 

  76. 	u8 path_a_cck_2tx_pwr_idx_diff:4;
    77. 

  77. 	u8 path_a_ofdm_2tx_pwr_idx_diff:4;
    78. 

  78. 	u8 rsvd9[0xf2];
    79. 

  79. 	union {
    80. 

  80. 		struct rtw8852au_efuse u;
    81. 

  81. 		struct rtw8852ae_efuse e;
    82. 

  82. 	};
    83. 

  83. } __packed;
    84. 

  84. 

  85. struct rtw8852a_bb_pmac_info {
    86. 

  86. 	u8 en_pmac_tx:1;
    87. 

  87. 	u8 is_cck:1;
    88. 

  88. 	u8 mode:3;
    89. 

  89. 	u8 rsvd:3;
    90. 

  90. 	u16 tx_cnt;
    91. 

  91. 	u16 period;
    92. 

  92. 	u16 tx_time;
    93. 

  93. 	u8 duty_cycle;
    94. 

  94. };
    95. 

  95. 

  96. extern const struct rtw89_chip_info rtw8852a_chip_info;
    97. 

  97. 

  98. void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev);
    99. 

  99. void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
    100. 

  100. 			     struct rtw8852a_bb_pmac_info *tx_info,
    101. 

  101. 			     enum rtw89_phy_idx idx);
    102. 

  102. void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
    103. 

  103. 				 u16 tx_cnt, u16 period, u16 tx_time,
    104. 

  104. 				 enum rtw89_phy_idx idx);
    105. 

  105. void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
    106. 

  106. 			   enum rtw89_phy_idx idx);
    107. 

  107. void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path);
    108. 

  108. void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
    109. 

  109. 				enum rtw89_phy_idx idx, u8 mode);
    110. 

  110. 

  111. #endif
    112.