main.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2. /* Copyright(c) 2018-2019 Realtek Corporation
  3. */
  4. #include <linux/devcoredump.h>
  5. #include "main.h"
  6. #include "regd.h"
  7. #include "fw.h"
  8. #include "ps.h"
  9. #include "sec.h"
  10. #include "mac.h"
  11. #include "coex.h"
  12. #include "phy.h"
  13. #include "reg.h"
  14. #include "efuse.h"
  15. #include "tx.h"
  16. #include "debug.h"
  17. #include "bf.h"
  18. #include "sar.h"
  19. bool rtw_disable_lps_deep_mode;
  20. EXPORT_SYMBOL(rtw_disable_lps_deep_mode);
  21. bool rtw_bf_support = true;
  22. unsigned int rtw_debug_mask;
  23. EXPORT_SYMBOL(rtw_debug_mask);
  24. /* EDCCA is enabled during normal behavior. For debugging purpose in
  25. * a noisy environment, it can be disabled via edcca debugfs. Because
  26. * all rtw88 devices will probably be affected if environment is noisy,
  27. * rtw_edcca_enabled is just declared by driver instead of by device.
  28. * So, turning it off will take effect for all rtw88 devices before
  29. * there is a tough reason to maintain rtw_edcca_enabled by device.
  30. */
  31. bool rtw_edcca_enabled = true;
  32. module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644);
  33. module_param_named(support_bf, rtw_bf_support, bool, 0644);
  34. module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
  35. MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS");
  36. MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
  37. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  38. static struct ieee80211_channel rtw_channeltable_2g[] = {
  39. {.center_freq = 2412, .hw_value = 1,},
  40. {.center_freq = 2417, .hw_value = 2,},
  41. {.center_freq = 2422, .hw_value = 3,},
  42. {.center_freq = 2427, .hw_value = 4,},
  43. {.center_freq = 2432, .hw_value = 5,},
  44. {.center_freq = 2437, .hw_value = 6,},
  45. {.center_freq = 2442, .hw_value = 7,},
  46. {.center_freq = 2447, .hw_value = 8,},
  47. {.center_freq = 2452, .hw_value = 9,},
  48. {.center_freq = 2457, .hw_value = 10,},
  49. {.center_freq = 2462, .hw_value = 11,},
  50. {.center_freq = 2467, .hw_value = 12,},
  51. {.center_freq = 2472, .hw_value = 13,},
  52. {.center_freq = 2484, .hw_value = 14,},
  53. };
  54. static struct ieee80211_channel rtw_channeltable_5g[] = {
  55. {.center_freq = 5180, .hw_value = 36,},
  56. {.center_freq = 5200, .hw_value = 40,},
  57. {.center_freq = 5220, .hw_value = 44,},
  58. {.center_freq = 5240, .hw_value = 48,},
  59. {.center_freq = 5260, .hw_value = 52,},
  60. {.center_freq = 5280, .hw_value = 56,},
  61. {.center_freq = 5300, .hw_value = 60,},
  62. {.center_freq = 5320, .hw_value = 64,},
  63. {.center_freq = 5500, .hw_value = 100,},
  64. {.center_freq = 5520, .hw_value = 104,},
  65. {.center_freq = 5540, .hw_value = 108,},
  66. {.center_freq = 5560, .hw_value = 112,},
  67. {.center_freq = 5580, .hw_value = 116,},
  68. {.center_freq = 5600, .hw_value = 120,},
  69. {.center_freq = 5620, .hw_value = 124,},
  70. {.center_freq = 5640, .hw_value = 128,},
  71. {.center_freq = 5660, .hw_value = 132,},
  72. {.center_freq = 5680, .hw_value = 136,},
  73. {.center_freq = 5700, .hw_value = 140,},
  74. {.center_freq = 5720, .hw_value = 144,},
  75. {.center_freq = 5745, .hw_value = 149,},
  76. {.center_freq = 5765, .hw_value = 153,},
  77. {.center_freq = 5785, .hw_value = 157,},
  78. {.center_freq = 5805, .hw_value = 161,},
  79. {.center_freq = 5825, .hw_value = 165,
  80. .flags = IEEE80211_CHAN_NO_HT40MINUS},
  81. };
  82. static struct ieee80211_rate rtw_ratetable[] = {
  83. {.bitrate = 10, .hw_value = 0x00,},
  84. {.bitrate = 20, .hw_value = 0x01,},
  85. {.bitrate = 55, .hw_value = 0x02,},
  86. {.bitrate = 110, .hw_value = 0x03,},
  87. {.bitrate = 60, .hw_value = 0x04,},
  88. {.bitrate = 90, .hw_value = 0x05,},
  89. {.bitrate = 120, .hw_value = 0x06,},
  90. {.bitrate = 180, .hw_value = 0x07,},
  91. {.bitrate = 240, .hw_value = 0x08,},
  92. {.bitrate = 360, .hw_value = 0x09,},
  93. {.bitrate = 480, .hw_value = 0x0a,},
  94. {.bitrate = 540, .hw_value = 0x0b,},
  95. };
  96. u16 rtw_desc_to_bitrate(u8 desc_rate)
  97. {
  98. struct ieee80211_rate rate;
  99. if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
  100. return 0;
  101. rate = rtw_ratetable[desc_rate];
  102. return rate.bitrate;
  103. }
  104. static struct ieee80211_supported_band rtw_band_2ghz = {
  105. .band = NL80211_BAND_2GHZ,
  106. .channels = rtw_channeltable_2g,
  107. .n_channels = ARRAY_SIZE(rtw_channeltable_2g),
  108. .bitrates = rtw_ratetable,
  109. .n_bitrates = ARRAY_SIZE(rtw_ratetable),
  110. .ht_cap = {0},
  111. .vht_cap = {0},
  112. };
  113. static struct ieee80211_supported_band rtw_band_5ghz = {
  114. .band = NL80211_BAND_5GHZ,
  115. .channels = rtw_channeltable_5g,
  116. .n_channels = ARRAY_SIZE(rtw_channeltable_5g),
  117. /* 5G has no CCK rates */
  118. .bitrates = rtw_ratetable + 4,
  119. .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
  120. .ht_cap = {0},
  121. .vht_cap = {0},
  122. };
  123. struct rtw_watch_dog_iter_data {
  124. struct rtw_dev *rtwdev;
  125. struct rtw_vif *rtwvif;
  126. };
  127. static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
  128. {
  129. struct rtw_bf_info *bf_info = &rtwdev->bf_info;
  130. u8 fix_rate_enable = 0;
  131. u8 new_csi_rate_idx;
  132. if (rtwvif->bfee.role != RTW_BFEE_SU &&
  133. rtwvif->bfee.role != RTW_BFEE_MU)
  134. return;
  135. rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
  136. bf_info->cur_csi_rpt_rate,
  137. fix_rate_enable, &new_csi_rate_idx);
  138. if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
  139. bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
  140. }
  141. static void rtw_vif_watch_dog_iter(void *data, u8 *mac,
  142. struct ieee80211_vif *vif)
  143. {
  144. struct rtw_watch_dog_iter_data *iter_data = data;
  145. struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
  146. if (vif->type == NL80211_IFTYPE_STATION)
  147. if (vif->cfg.assoc)
  148. iter_data->rtwvif = rtwvif;
  149. rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
  150. rtwvif->stats.tx_unicast = 0;
  151. rtwvif->stats.rx_unicast = 0;
  152. rtwvif->stats.tx_cnt = 0;
  153. rtwvif->stats.rx_cnt = 0;
  154. }
  155. /* process TX/RX statistics periodically for hardware,
  156. * the information helps hardware to enhance performance
  157. */
  158. static void rtw_watch_dog_work(struct work_struct *work)
  159. {
  160. struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
  161. watch_dog_work.work);
  162. struct rtw_traffic_stats *stats = &rtwdev->stats;
  163. struct rtw_watch_dog_iter_data data = {};
  164. bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
  165. bool ps_active;
  166. mutex_lock(&rtwdev->mutex);
  167. if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
  168. goto unlock;
  169. ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
  170. RTW_WATCH_DOG_DELAY_TIME);
  171. if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
  172. set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
  173. else
  174. clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
  175. rtw_coex_wl_status_check(rtwdev);
  176. rtw_coex_query_bt_hid_list(rtwdev);
  177. if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
  178. rtw_coex_wl_status_change_notify(rtwdev, 0);
  179. if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
  180. stats->rx_cnt > RTW_LPS_THRESHOLD)
  181. ps_active = true;
  182. else
  183. ps_active = false;
  184. ewma_tp_add(&stats->tx_ewma_tp,
  185. (u32)(stats->tx_unicast >> RTW_TP_SHIFT));
  186. ewma_tp_add(&stats->rx_ewma_tp,
  187. (u32)(stats->rx_unicast >> RTW_TP_SHIFT));
  188. stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
  189. stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
  190. /* reset tx/rx statictics */
  191. stats->tx_unicast = 0;
  192. stats->rx_unicast = 0;
  193. stats->tx_cnt = 0;
  194. stats->rx_cnt = 0;
  195. if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
  196. goto unlock;
  197. /* make sure BB/RF is working for dynamic mech */
  198. rtw_leave_lps(rtwdev);
  199. rtw_phy_dynamic_mechanism(rtwdev);
  200. data.rtwdev = rtwdev;
  201. /* use atomic version to avoid taking local->iflist_mtx mutex */
  202. rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data);
  203. /* fw supports only one station associated to enter lps, if there are
  204. * more than two stations associated to the AP, then we can not enter
  205. * lps, because fw does not handle the overlapped beacon interval
  206. *
  207. * rtw_recalc_lps() iterate vifs and determine if driver can enter
  208. * ps by vif->type and vif->cfg.ps, all we need to do here is to
  209. * get that vif and check if device is having traffic more than the
  210. * threshold.
  211. */
  212. if (rtwdev->ps_enabled && data.rtwvif && !ps_active &&
  213. !rtwdev->beacon_loss)
  214. rtw_enter_lps(rtwdev, data.rtwvif->port);
  215. rtwdev->watch_dog_cnt++;
  216. unlock:
  217. mutex_unlock(&rtwdev->mutex);
  218. }
  219. static void rtw_c2h_work(struct work_struct *work)
  220. {
  221. struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
  222. struct sk_buff *skb, *tmp;
  223. skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
  224. skb_unlink(skb, &rtwdev->c2h_queue);
  225. rtw_fw_c2h_cmd_handle(rtwdev, skb);
  226. dev_kfree_skb_any(skb);
  227. }
  228. }
  229. static void rtw_ips_work(struct work_struct *work)
  230. {
  231. struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work);
  232. mutex_lock(&rtwdev->mutex);
  233. if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)
  234. rtw_enter_ips(rtwdev);
  235. mutex_unlock(&rtwdev->mutex);
  236. }
  237. static u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
  238. {
  239. unsigned long mac_id;
  240. mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
  241. if (mac_id < RTW_MAX_MAC_ID_NUM)
  242. set_bit(mac_id, rtwdev->mac_id_map);
  243. return mac_id;
  244. }
  245. static void rtw_sta_rc_work(struct work_struct *work)
  246. {
  247. struct rtw_sta_info *si = container_of(work, struct rtw_sta_info,
  248. rc_work);
  249. struct rtw_dev *rtwdev = si->rtwdev;
  250. mutex_lock(&rtwdev->mutex);
  251. rtw_update_sta_info(rtwdev, si, true);
  252. mutex_unlock(&rtwdev->mutex);
  253. }
  254. int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
  255. struct ieee80211_vif *vif)
  256. {
  257. struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
  258. int i;
  259. si->mac_id = rtw_acquire_macid(rtwdev);
  260. if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
  261. return -ENOSPC;
  262. si->rtwdev = rtwdev;
  263. si->sta = sta;
  264. si->vif = vif;
  265. si->init_ra_lv = 1;
  266. ewma_rssi_init(&si->avg_rssi);
  267. for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
  268. rtw_txq_init(rtwdev, sta->txq[i]);
  269. INIT_WORK(&si->rc_work, rtw_sta_rc_work);
  270. rtw_update_sta_info(rtwdev, si, true);
  271. rtw_fw_media_status_report(rtwdev, si->mac_id, true);
  272. rtwdev->sta_cnt++;
  273. rtwdev->beacon_loss = false;
  274. rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n",
  275. sta->addr, si->mac_id);
  276. return 0;
  277. }
  278. void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
  279. bool fw_exist)
  280. {
  281. struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
  282. int i;
  283. cancel_work_sync(&si->rc_work);
  284. rtw_release_macid(rtwdev, si->mac_id);
  285. if (fw_exist)
  286. rtw_fw_media_status_report(rtwdev, si->mac_id, false);
  287. for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
  288. rtw_txq_cleanup(rtwdev, sta->txq[i]);
  289. kfree(si->mask);
  290. rtwdev->sta_cnt--;
  291. rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n",
  292. sta->addr, si->mac_id);
  293. }
  294. struct rtw_fwcd_hdr {
  295. u32 item;
  296. u32 size;
  297. u32 padding1;
  298. u32 padding2;
  299. } __packed;
  300. static int rtw_fwcd_prep(struct rtw_dev *rtwdev)
  301. {
  302. const struct rtw_chip_info *chip = rtwdev->chip;
  303. struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
  304. const struct rtw_fwcd_segs *segs = chip->fwcd_segs;
  305. u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr);
  306. u8 i;
  307. if (segs) {
  308. prep_size += segs->num * sizeof(struct rtw_fwcd_hdr);
  309. for (i = 0; i < segs->num; i++)
  310. prep_size += segs->segs[i];
  311. }
  312. desc->data = vmalloc(prep_size);
  313. if (!desc->data)
  314. return -ENOMEM;
  315. desc->size = prep_size;
  316. desc->next = desc->data;
  317. return 0;
  318. }
  319. static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size)
  320. {
  321. struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
  322. struct rtw_fwcd_hdr *hdr;
  323. u8 *next;
  324. if (!desc->data) {
  325. rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n");
  326. return NULL;
  327. }
  328. next = desc->next + sizeof(struct rtw_fwcd_hdr);
  329. if (next - desc->data + size > desc->size) {
  330. rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n");
  331. return NULL;
  332. }
  333. hdr = (struct rtw_fwcd_hdr *)(desc->next);
  334. hdr->item = item;
  335. hdr->size = size;
  336. hdr->padding1 = 0x01234567;
  337. hdr->padding2 = 0x89abcdef;
  338. desc->next = next + size;
  339. return next;
  340. }
  341. static void rtw_fwcd_dump(struct rtw_dev *rtwdev)
  342. {
  343. struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
  344. rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n");
  345. /* Data will be freed after lifetime of device coredump. After calling
  346. * dev_coredump, data is supposed to be handled by the device coredump
  347. * framework. Note that a new dump will be discarded if a previous one
  348. * hasn't been released yet.
  349. */
  350. dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL);
  351. }
  352. static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self)
  353. {
  354. struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
  355. if (free_self) {
  356. rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n");
  357. vfree(desc->data);
  358. }
  359. desc->data = NULL;
  360. desc->next = NULL;
  361. }
  362. static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
  363. {
  364. u32 size = rtwdev->chip->fw_rxff_size;
  365. u32 *buf;
  366. u8 seq;
  367. buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size);
  368. if (!buf)
  369. return -ENOMEM;
  370. if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
  371. rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
  372. return -EINVAL;
  373. }
  374. if (GET_FW_DUMP_LEN(buf) == 0) {
  375. rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
  376. return -EINVAL;
  377. }
  378. seq = GET_FW_DUMP_SEQ(buf);
  379. if (seq > 0) {
  380. rtw_dbg(rtwdev, RTW_DBG_FW,
  381. "fw crash dump's seq is wrong: %d\n", seq);
  382. return -EINVAL;
  383. }
  384. return 0;
  385. }
  386. int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
  387. u32 fwcd_item)
  388. {
  389. u32 rxff = rtwdev->chip->fw_rxff_size;
  390. u32 dump_size, done_size = 0;
  391. u8 *buf;
  392. int ret;
  393. buf = rtw_fwcd_next(rtwdev, fwcd_item, size);
  394. if (!buf)
  395. return -ENOMEM;
  396. while (size) {
  397. dump_size = size > rxff ? rxff : size;
  398. ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size,
  399. dump_size);
  400. if (ret) {
  401. rtw_err(rtwdev,
  402. "ddma fw 0x%x [+0x%x] to fw fifo fail\n",
  403. ocp_src, done_size);
  404. return ret;
  405. }
  406. ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0,
  407. dump_size, (u32 *)(buf + done_size));
  408. if (ret) {
  409. rtw_err(rtwdev,
  410. "dump fw 0x%x [+0x%x] from fw fifo fail\n",
  411. ocp_src, done_size);
  412. return ret;
  413. }
  414. size -= dump_size;
  415. done_size += dump_size;
  416. }
  417. return 0;
  418. }
  419. EXPORT_SYMBOL(rtw_dump_fw);
  420. int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size)
  421. {
  422. u8 *buf;
  423. u32 i;
  424. if (addr & 0x3) {
  425. WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);
  426. return -EINVAL;
  427. }
  428. buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size);
  429. if (!buf)
  430. return -ENOMEM;
  431. for (i = 0; i < size; i += 4)
  432. *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i);
  433. return 0;
  434. }
  435. EXPORT_SYMBOL(rtw_dump_reg);
  436. void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
  437. struct ieee80211_bss_conf *conf)
  438. {
  439. struct ieee80211_vif *vif = NULL;
  440. if (conf)
  441. vif = container_of(conf, struct ieee80211_vif, bss_conf);
  442. if (conf && vif->cfg.assoc) {
  443. rtwvif->aid = vif->cfg.aid;
  444. rtwvif->net_type = RTW_NET_MGD_LINKED;
  445. } else {
  446. rtwvif->aid = 0;
  447. rtwvif->net_type = RTW_NET_NO_LINK;
  448. }
  449. }
  450. static void rtw_reset_key_iter(struct ieee80211_hw *hw,
  451. struct ieee80211_vif *vif,
  452. struct ieee80211_sta *sta,
  453. struct ieee80211_key_conf *key,
  454. void *data)
  455. {
  456. struct rtw_dev *rtwdev = (struct rtw_dev *)data;
  457. struct rtw_sec_desc *sec = &rtwdev->sec;
  458. rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
  459. }
  460. static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
  461. {
  462. struct rtw_dev *rtwdev = (struct rtw_dev *)data;
  463. if (rtwdev->sta_cnt == 0) {
  464. rtw_warn(rtwdev, "sta count before reset should not be 0\n");
  465. return;
  466. }
  467. rtw_sta_remove(rtwdev, sta, false);
  468. }
  469. static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  470. {
  471. struct rtw_dev *rtwdev = (struct rtw_dev *)data;
  472. struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
  473. rtw_bf_disassoc(rtwdev, vif, NULL);
  474. rtw_vif_assoc_changed(rtwvif, NULL);
  475. rtw_txq_cleanup(rtwdev, vif->txq);
  476. }
  477. void rtw_fw_recovery(struct rtw_dev *rtwdev)
  478. {
  479. if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
  480. ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
  481. }
  482. static void __fw_recovery_work(struct rtw_dev *rtwdev)
  483. {
  484. int ret = 0;
  485. set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
  486. clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags);
  487. ret = rtw_fwcd_prep(rtwdev);
  488. if (ret)
  489. goto free;
  490. ret = rtw_fw_dump_crash_log(rtwdev);
  491. if (ret)
  492. goto free;
  493. ret = rtw_chip_dump_fw_crash(rtwdev);
  494. if (ret)
  495. goto free;
  496. rtw_fwcd_dump(rtwdev);
  497. free:
  498. rtw_fwcd_free(rtwdev, !!ret);
  499. rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
  500. WARN(1, "firmware crash, start reset and recover\n");
  501. rcu_read_lock();
  502. rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
  503. rcu_read_unlock();
  504. rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
  505. rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
  506. rtw_enter_ips(rtwdev);
  507. }
  508. static void rtw_fw_recovery_work(struct work_struct *work)
  509. {
  510. struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
  511. fw_recovery_work);
  512. mutex_lock(&rtwdev->mutex);
  513. __fw_recovery_work(rtwdev);
  514. mutex_unlock(&rtwdev->mutex);
  515. ieee80211_restart_hw(rtwdev->hw);
  516. }
  517. struct rtw_txq_ba_iter_data {
  518. };
  519. static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
  520. {
  521. struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
  522. int ret;
  523. u8 tid;
  524. tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
  525. while (tid != IEEE80211_NUM_TIDS) {
  526. clear_bit(tid, si->tid_ba);
  527. ret = ieee80211_start_tx_ba_session(sta, tid, 0);
  528. if (ret == -EINVAL) {
  529. struct ieee80211_txq *txq;
  530. struct rtw_txq *rtwtxq;
  531. txq = sta->txq[tid];
  532. rtwtxq = (struct rtw_txq *)txq->drv_priv;
  533. set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
  534. }
  535. tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
  536. }
  537. }
  538. static void rtw_txq_ba_work(struct work_struct *work)
  539. {
  540. struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
  541. struct rtw_txq_ba_iter_data data;
  542. rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
  543. }
  544. void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel)
  545. {
  546. if (IS_CH_2G_BAND(channel))
  547. pkt_stat->band = NL80211_BAND_2GHZ;
  548. else if (IS_CH_5G_BAND(channel))
  549. pkt_stat->band = NL80211_BAND_5GHZ;
  550. else
  551. return;
  552. pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band);
  553. }
  554. EXPORT_SYMBOL(rtw_set_rx_freq_band);
  555. void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period)
  556. {
  557. rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE);
  558. rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1);
  559. }
  560. void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
  561. u8 primary_channel, enum rtw_supported_band band,
  562. enum rtw_bandwidth bandwidth)
  563. {
  564. enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band);
  565. struct rtw_hal *hal = &rtwdev->hal;
  566. u8 *cch_by_bw = hal->cch_by_bw;
  567. u32 center_freq, primary_freq;
  568. enum rtw_sar_bands sar_band;
  569. u8 primary_channel_idx;
  570. center_freq = ieee80211_channel_to_frequency(center_channel, nl_band);
  571. primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band);
  572. /* assign the center channel used while 20M bw is selected */
  573. cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel;
  574. /* assign the center channel used while current bw is selected */
  575. cch_by_bw[bandwidth] = center_channel;
  576. switch (bandwidth) {
  577. case RTW_CHANNEL_WIDTH_20:
  578. default:
  579. primary_channel_idx = RTW_SC_DONT_CARE;
  580. break;
  581. case RTW_CHANNEL_WIDTH_40:
  582. if (primary_freq > center_freq)
  583. primary_channel_idx = RTW_SC_20_UPPER;
  584. else
  585. primary_channel_idx = RTW_SC_20_LOWER;
  586. break;
  587. case RTW_CHANNEL_WIDTH_80:
  588. if (primary_freq > center_freq) {
  589. if (primary_freq - center_freq == 10)
  590. primary_channel_idx = RTW_SC_20_UPPER;
  591. else
  592. primary_channel_idx = RTW_SC_20_UPMOST;
  593. /* assign the center channel used
  594. * while 40M bw is selected
  595. */
  596. cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4;
  597. } else {
  598. if (center_freq - primary_freq == 10)
  599. primary_channel_idx = RTW_SC_20_LOWER;
  600. else
  601. primary_channel_idx = RTW_SC_20_LOWEST;
  602. /* assign the center channel used
  603. * while 40M bw is selected
  604. */
  605. cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4;
  606. }
  607. break;
  608. }
  609. switch (center_channel) {
  610. case 1 ... 14:
  611. sar_band = RTW_SAR_BAND_0;
  612. break;
  613. case 36 ... 64:
  614. sar_band = RTW_SAR_BAND_1;
  615. break;
  616. case 100 ... 144:
  617. sar_band = RTW_SAR_BAND_3;
  618. break;
  619. case 149 ... 177:
  620. sar_band = RTW_SAR_BAND_4;
  621. break;
  622. default:
  623. WARN(1, "unknown ch(%u) to SAR band\n", center_channel);
  624. sar_band = RTW_SAR_BAND_0;
  625. break;
  626. }
  627. hal->current_primary_channel_index = primary_channel_idx;
  628. hal->current_band_width = bandwidth;
  629. hal->primary_channel = primary_channel;
  630. hal->current_channel = center_channel;
  631. hal->current_band_type = band;
  632. hal->sar_band = sar_band;
  633. }
  634. void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
  635. struct rtw_channel_params *chan_params)
  636. {
  637. struct ieee80211_channel *channel = chandef->chan;
  638. enum nl80211_chan_width width = chandef->width;
  639. u32 primary_freq, center_freq;
  640. u8 center_chan;
  641. u8 bandwidth = RTW_CHANNEL_WIDTH_20;
  642. center_chan = channel->hw_value;
  643. primary_freq = channel->center_freq;
  644. center_freq = chandef->center_freq1;
  645. switch (width) {
  646. case NL80211_CHAN_WIDTH_20_NOHT:
  647. case NL80211_CHAN_WIDTH_20:
  648. bandwidth = RTW_CHANNEL_WIDTH_20;
  649. break;
  650. case NL80211_CHAN_WIDTH_40:
  651. bandwidth = RTW_CHANNEL_WIDTH_40;
  652. if (primary_freq > center_freq)
  653. center_chan -= 2;
  654. else
  655. center_chan += 2;
  656. break;
  657. case NL80211_CHAN_WIDTH_80:
  658. bandwidth = RTW_CHANNEL_WIDTH_80;
  659. if (primary_freq > center_freq) {
  660. if (primary_freq - center_freq == 10)
  661. center_chan -= 2;
  662. else
  663. center_chan -= 6;
  664. } else {
  665. if (center_freq - primary_freq == 10)
  666. center_chan += 2;
  667. else
  668. center_chan += 6;
  669. }
  670. break;
  671. default:
  672. center_chan = 0;
  673. break;
  674. }
  675. chan_params->center_chan = center_chan;
  676. chan_params->bandwidth = bandwidth;
  677. chan_params->primary_chan = channel->hw_value;
  678. }
  679. void rtw_set_channel(struct rtw_dev *rtwdev)
  680. {
  681. const struct rtw_chip_info *chip = rtwdev->chip;
  682. struct ieee80211_hw *hw = rtwdev->hw;
  683. struct rtw_hal *hal = &rtwdev->hal;
  684. struct rtw_channel_params ch_param;
  685. u8 center_chan, primary_chan, bandwidth, band;
  686. rtw_get_channel_params(&hw->conf.chandef, &ch_param);
  687. if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
  688. return;
  689. center_chan = ch_param.center_chan;
  690. primary_chan = ch_param.primary_chan;
  691. bandwidth = ch_param.bandwidth;
  692. band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
  693. rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth);
  694. chip->ops->set_channel(rtwdev, center_chan, bandwidth,
  695. hal->current_primary_channel_index);
  696. if (hal->current_band_type == RTW_BAND_5G) {
  697. rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
  698. } else {
  699. if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
  700. rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
  701. else
  702. rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
  703. }
  704. rtw_phy_set_tx_power_level(rtwdev, center_chan);
  705. /* if the channel isn't set for scanning, we will do RF calibration
  706. * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration
  707. * during scanning on each channel takes too long.
  708. */
  709. if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
  710. rtwdev->need_rfk = true;
  711. }
  712. void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
  713. {
  714. const struct rtw_chip_info *chip = rtwdev->chip;
  715. if (rtwdev->need_rfk) {
  716. rtwdev->need_rfk = false;
  717. chip->ops->phy_calibration(rtwdev);
  718. }
  719. }
  720. static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
  721. {
  722. int i;
  723. for (i = 0; i < ETH_ALEN; i++)
  724. rtw_write8(rtwdev, start + i, addr[i]);
  725. }
  726. void rtw_vif_port_config(struct rtw_dev *rtwdev,
  727. struct rtw_vif *rtwvif,
  728. u32 config)
  729. {
  730. u32 addr, mask;
  731. if (config & PORT_SET_MAC_ADDR) {
  732. addr = rtwvif->conf->mac_addr.addr;
  733. rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
  734. }
  735. if (config & PORT_SET_BSSID) {
  736. addr = rtwvif->conf->bssid.addr;
  737. rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
  738. }
  739. if (config & PORT_SET_NET_TYPE) {
  740. addr = rtwvif->conf->net_type.addr;
  741. mask = rtwvif->conf->net_type.mask;
  742. rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
  743. }
  744. if (config & PORT_SET_AID) {
  745. addr = rtwvif->conf->aid.addr;
  746. mask = rtwvif->conf->aid.mask;
  747. rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
  748. }
  749. if (config & PORT_SET_BCN_CTRL) {
  750. addr = rtwvif->conf->bcn_ctrl.addr;
  751. mask = rtwvif->conf->bcn_ctrl.mask;
  752. rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
  753. }
  754. }
  755. static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
  756. {
  757. u8 bw = 0;
  758. switch (bw_cap) {
  759. case EFUSE_HW_CAP_IGNORE:
  760. case EFUSE_HW_CAP_SUPP_BW80:
  761. bw |= BIT(RTW_CHANNEL_WIDTH_80);
  762. fallthrough;
  763. case EFUSE_HW_CAP_SUPP_BW40:
  764. bw |= BIT(RTW_CHANNEL_WIDTH_40);
  765. fallthrough;
  766. default:
  767. bw |= BIT(RTW_CHANNEL_WIDTH_20);
  768. break;
  769. }
  770. return bw;
  771. }
  772. static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
  773. {
  774. const struct rtw_chip_info *chip = rtwdev->chip;
  775. struct rtw_hal *hal = &rtwdev->hal;
  776. if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
  777. hw_ant_num >= hal->rf_path_num)
  778. return;
  779. switch (hw_ant_num) {
  780. case 1:
  781. hal->rf_type = RF_1T1R;
  782. hal->rf_path_num = 1;
  783. if (!chip->fix_rf_phy_num)
  784. hal->rf_phy_num = hal->rf_path_num;
  785. hal->antenna_tx = BB_PATH_A;
  786. hal->antenna_rx = BB_PATH_A;
  787. break;
  788. default:
  789. WARN(1, "invalid hw configuration from efuse\n");
  790. break;
  791. }
  792. }
  793. static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
  794. {
  795. u64 ra_mask = 0;
  796. u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
  797. u8 vht_mcs_cap;
  798. int i, nss;
  799. /* 4SS, every two bits for MCS7/8/9 */
  800. for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
  801. vht_mcs_cap = mcs_map & 0x3;
  802. switch (vht_mcs_cap) {
  803. case 2: /* MCS9 */
  804. ra_mask |= 0x3ffULL << nss;
  805. break;
  806. case 1: /* MCS8 */
  807. ra_mask |= 0x1ffULL << nss;
  808. break;
  809. case 0: /* MCS7 */
  810. ra_mask |= 0x0ffULL << nss;
  811. break;
  812. default:
  813. break;
  814. }
  815. }
  816. return ra_mask;
  817. }
  818. static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
  819. {
  820. u8 rate_id = 0;
  821. switch (wireless_set) {
  822. case WIRELESS_CCK:
  823. rate_id = RTW_RATEID_B_20M;
  824. break;
  825. case WIRELESS_OFDM:
  826. rate_id = RTW_RATEID_G;
  827. break;
  828. case WIRELESS_CCK | WIRELESS_OFDM:
  829. rate_id = RTW_RATEID_BG;
  830. break;
  831. case WIRELESS_OFDM | WIRELESS_HT:
  832. if (tx_num == 1)
  833. rate_id = RTW_RATEID_GN_N1SS;
  834. else if (tx_num == 2)
  835. rate_id = RTW_RATEID_GN_N2SS;
  836. else if (tx_num == 3)
  837. rate_id = RTW_RATEID_ARFR5_N_3SS;
  838. break;
  839. case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
  840. if (bw_mode == RTW_CHANNEL_WIDTH_40) {
  841. if (tx_num == 1)
  842. rate_id = RTW_RATEID_BGN_40M_1SS;
  843. else if (tx_num == 2)
  844. rate_id = RTW_RATEID_BGN_40M_2SS;
  845. else if (tx_num == 3)
  846. rate_id = RTW_RATEID_ARFR5_N_3SS;
  847. else if (tx_num == 4)
  848. rate_id = RTW_RATEID_ARFR7_N_4SS;
  849. } else {
  850. if (tx_num == 1)
  851. rate_id = RTW_RATEID_BGN_20M_1SS;
  852. else if (tx_num == 2)
  853. rate_id = RTW_RATEID_BGN_20M_2SS;
  854. else if (tx_num == 3)
  855. rate_id = RTW_RATEID_ARFR5_N_3SS;
  856. else if (tx_num == 4)
  857. rate_id = RTW_RATEID_ARFR7_N_4SS;
  858. }
  859. break;
  860. case WIRELESS_OFDM | WIRELESS_VHT:
  861. if (tx_num == 1)
  862. rate_id = RTW_RATEID_ARFR1_AC_1SS;
  863. else if (tx_num == 2)
  864. rate_id = RTW_RATEID_ARFR0_AC_2SS;
  865. else if (tx_num == 3)
  866. rate_id = RTW_RATEID_ARFR4_AC_3SS;
  867. else if (tx_num == 4)
  868. rate_id = RTW_RATEID_ARFR6_AC_4SS;
  869. break;
  870. case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
  871. if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
  872. if (tx_num == 1)
  873. rate_id = RTW_RATEID_ARFR1_AC_1SS;
  874. else if (tx_num == 2)
  875. rate_id = RTW_RATEID_ARFR0_AC_2SS;
  876. else if (tx_num == 3)
  877. rate_id = RTW_RATEID_ARFR4_AC_3SS;
  878. else if (tx_num == 4)
  879. rate_id = RTW_RATEID_ARFR6_AC_4SS;
  880. } else {
  881. if (tx_num == 1)
  882. rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
  883. else if (tx_num == 2)
  884. rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
  885. else if (tx_num == 3)
  886. rate_id = RTW_RATEID_ARFR4_AC_3SS;
  887. else if (tx_num == 4)
  888. rate_id = RTW_RATEID_ARFR6_AC_4SS;
  889. }
  890. break;
  891. default:
  892. break;
  893. }
  894. return rate_id;
  895. }
  896. #define RA_MASK_CCK_RATES 0x0000f
  897. #define RA_MASK_OFDM_RATES 0x00ff0
  898. #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0)
  899. #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8)
  900. #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16)
  901. #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \
  902. RA_MASK_HT_RATES_2SS | \
  903. RA_MASK_HT_RATES_3SS)
  904. #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0)
  905. #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10)
  906. #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20)
  907. #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \
  908. RA_MASK_VHT_RATES_2SS | \
  909. RA_MASK_VHT_RATES_3SS)
  910. #define RA_MASK_CCK_IN_BG 0x00005
  911. #define RA_MASK_CCK_IN_HT 0x00005
  912. #define RA_MASK_CCK_IN_VHT 0x00005
  913. #define RA_MASK_OFDM_IN_VHT 0x00010
  914. #define RA_MASK_OFDM_IN_HT_2G 0x00010
  915. #define RA_MASK_OFDM_IN_HT_5G 0x00030
  916. static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set)
  917. {
  918. u8 rssi_level = si->rssi_level;
  919. if (wireless_set == WIRELESS_CCK)
  920. return 0xffffffffffffffffULL;
  921. if (rssi_level == 0)
  922. return 0xffffffffffffffffULL;
  923. else if (rssi_level == 1)
  924. return 0xfffffffffffffff0ULL;
  925. else if (rssi_level == 2)
  926. return 0xffffffffffffefe0ULL;
  927. else if (rssi_level == 3)
  928. return 0xffffffffffffcfc0ULL;
  929. else if (rssi_level == 4)
  930. return 0xffffffffffff8f80ULL;
  931. else
  932. return 0xffffffffffff0f00ULL;
  933. }
  934. static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak)
  935. {
  936. if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
  937. ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
  938. if (ra_mask == 0)
  939. ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
  940. return ra_mask;
  941. }
  942. static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
  943. u64 ra_mask, bool is_vht_enable)
  944. {
  945. struct rtw_hal *hal = &rtwdev->hal;
  946. const struct cfg80211_bitrate_mask *mask = si->mask;
  947. u64 cfg_mask = GENMASK_ULL(63, 0);
  948. u8 band;
  949. if (!si->use_cfg_mask)
  950. return ra_mask;
  951. band = hal->current_band_type;
  952. if (band == RTW_BAND_2G) {
  953. band = NL80211_BAND_2GHZ;
  954. cfg_mask = mask->control[band].legacy;
  955. } else if (band == RTW_BAND_5G) {
  956. band = NL80211_BAND_5GHZ;
  957. cfg_mask = u64_encode_bits(mask->control[band].legacy,
  958. RA_MASK_OFDM_RATES);
  959. }
  960. if (!is_vht_enable) {
  961. if (ra_mask & RA_MASK_HT_RATES_1SS)
  962. cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
  963. RA_MASK_HT_RATES_1SS);
  964. if (ra_mask & RA_MASK_HT_RATES_2SS)
  965. cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
  966. RA_MASK_HT_RATES_2SS);
  967. } else {
  968. if (ra_mask & RA_MASK_VHT_RATES_1SS)
  969. cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
  970. RA_MASK_VHT_RATES_1SS);
  971. if (ra_mask & RA_MASK_VHT_RATES_2SS)
  972. cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
  973. RA_MASK_VHT_RATES_2SS);
  974. }
  975. ra_mask &= cfg_mask;
  976. return ra_mask;
  977. }
  978. void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
  979. bool reset_ra_mask)
  980. {
  981. struct rtw_dm_info *dm_info = &rtwdev->dm_info;
  982. struct ieee80211_sta *sta = si->sta;
  983. struct rtw_efuse *efuse = &rtwdev->efuse;
  984. struct rtw_hal *hal = &rtwdev->hal;
  985. u8 wireless_set;
  986. u8 bw_mode;
  987. u8 rate_id;
  988. u8 rf_type = RF_1T1R;
  989. u8 stbc_en = 0;
  990. u8 ldpc_en = 0;
  991. u8 tx_num = 1;
  992. u64 ra_mask = 0;
  993. u64 ra_mask_bak = 0;
  994. bool is_vht_enable = false;
  995. bool is_support_sgi = false;
  996. if (sta->deflink.vht_cap.vht_supported) {
  997. is_vht_enable = true;
  998. ra_mask |= get_vht_ra_mask(sta);
  999. if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
  1000. stbc_en = VHT_STBC_EN;
  1001. if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
  1002. ldpc_en = VHT_LDPC_EN;
  1003. } else if (sta->deflink.ht_cap.ht_supported) {
  1004. ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) |
  1005. (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
  1006. if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
  1007. stbc_en = HT_STBC_EN;
  1008. if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
  1009. ldpc_en = HT_LDPC_EN;
  1010. }
  1011. if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss)
  1012. ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
  1013. if (hal->current_band_type == RTW_BAND_5G) {
  1014. ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
  1015. ra_mask_bak = ra_mask;
  1016. if (sta->deflink.vht_cap.vht_supported) {
  1017. ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
  1018. wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
  1019. } else if (sta->deflink.ht_cap.ht_supported) {
  1020. ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
  1021. wireless_set = WIRELESS_OFDM | WIRELESS_HT;
  1022. } else {
  1023. wireless_set = WIRELESS_OFDM;
  1024. }
  1025. dm_info->rrsr_val_init = RRSR_INIT_5G;
  1026. } else if (hal->current_band_type == RTW_BAND_2G) {
  1027. ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
  1028. ra_mask_bak = ra_mask;
  1029. if (sta->deflink.vht_cap.vht_supported) {
  1030. ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
  1031. RA_MASK_OFDM_IN_VHT;
  1032. wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
  1033. WIRELESS_HT | WIRELESS_VHT;
  1034. } else if (sta->deflink.ht_cap.ht_supported) {
  1035. ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
  1036. RA_MASK_OFDM_IN_HT_2G;
  1037. wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
  1038. WIRELESS_HT;
  1039. } else if (sta->deflink.supp_rates[0] <= 0xf) {
  1040. wireless_set = WIRELESS_CCK;
  1041. } else {
  1042. ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG;
  1043. wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
  1044. }
  1045. dm_info->rrsr_val_init = RRSR_INIT_2G;
  1046. } else {
  1047. rtw_err(rtwdev, "Unknown band type\n");
  1048. ra_mask_bak = ra_mask;
  1049. wireless_set = 0;
  1050. }
  1051. switch (sta->deflink.bandwidth) {
  1052. case IEEE80211_STA_RX_BW_80:
  1053. bw_mode = RTW_CHANNEL_WIDTH_80;
  1054. is_support_sgi = sta->deflink.vht_cap.vht_supported &&
  1055. (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
  1056. break;
  1057. case IEEE80211_STA_RX_BW_40:
  1058. bw_mode = RTW_CHANNEL_WIDTH_40;
  1059. is_support_sgi = sta->deflink.ht_cap.ht_supported &&
  1060. (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
  1061. break;
  1062. default:
  1063. bw_mode = RTW_CHANNEL_WIDTH_20;
  1064. is_support_sgi = sta->deflink.ht_cap.ht_supported &&
  1065. (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
  1066. break;
  1067. }
  1068. if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) {
  1069. tx_num = 2;
  1070. rf_type = RF_2T2R;
  1071. } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) {
  1072. tx_num = 2;
  1073. rf_type = RF_2T2R;
  1074. }
  1075. rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
  1076. ra_mask &= rtw_rate_mask_rssi(si, wireless_set);
  1077. ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak);
  1078. ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable);
  1079. si->bw_mode = bw_mode;
  1080. si->stbc_en = stbc_en;
  1081. si->ldpc_en = ldpc_en;
  1082. si->rf_type = rf_type;
  1083. si->wireless_set = wireless_set;
  1084. si->sgi_enable = is_support_sgi;
  1085. si->vht_enable = is_vht_enable;
  1086. si->ra_mask = ra_mask;
  1087. si->rate_id = rate_id;
  1088. rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask);
  1089. }
  1090. static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
  1091. {
  1092. const struct rtw_chip_info *chip = rtwdev->chip;
  1093. struct rtw_fw_state *fw;
  1094. fw = &rtwdev->fw;
  1095. wait_for_completion(&fw->completion);
  1096. if (!fw->firmware)
  1097. return -EINVAL;
  1098. if (chip->wow_fw_name) {
  1099. fw = &rtwdev->wow_fw;
  1100. wait_for_completion(&fw->completion);
  1101. if (!fw->firmware)
  1102. return -EINVAL;
  1103. }
  1104. return 0;
  1105. }
  1106. static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev,
  1107. struct rtw_fw_state *fw)
  1108. {
  1109. const struct rtw_chip_info *chip = rtwdev->chip;
  1110. if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
  1111. !fw->feature)
  1112. return LPS_DEEP_MODE_NONE;
  1113. if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
  1114. rtw_fw_feature_check(fw, FW_FEATURE_PG))
  1115. return LPS_DEEP_MODE_PG;
  1116. if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
  1117. rtw_fw_feature_check(fw, FW_FEATURE_LCLK))
  1118. return LPS_DEEP_MODE_LCLK;
  1119. return LPS_DEEP_MODE_NONE;
  1120. }
  1121. static int rtw_power_on(struct rtw_dev *rtwdev)
  1122. {
  1123. const struct rtw_chip_info *chip = rtwdev->chip;
  1124. struct rtw_fw_state *fw = &rtwdev->fw;
  1125. bool wifi_only;
  1126. int ret;
  1127. ret = rtw_hci_setup(rtwdev);
  1128. if (ret) {
  1129. rtw_err(rtwdev, "failed to setup hci\n");
  1130. goto err;
  1131. }
  1132. /* power on MAC before firmware downloaded */
  1133. ret = rtw_mac_power_on(rtwdev);
  1134. if (ret) {
  1135. rtw_err(rtwdev, "failed to power on mac\n");
  1136. goto err;
  1137. }
  1138. ret = rtw_wait_firmware_completion(rtwdev);
  1139. if (ret) {
  1140. rtw_err(rtwdev, "failed to wait firmware completion\n");
  1141. goto err_off;
  1142. }
  1143. ret = rtw_download_firmware(rtwdev, fw);
  1144. if (ret) {
  1145. rtw_err(rtwdev, "failed to download firmware\n");
  1146. goto err_off;
  1147. }
  1148. /* config mac after firmware downloaded */
  1149. ret = rtw_mac_init(rtwdev);
  1150. if (ret) {
  1151. rtw_err(rtwdev, "failed to configure mac\n");
  1152. goto err_off;
  1153. }
  1154. chip->ops->phy_set_param(rtwdev);
  1155. ret = rtw_hci_start(rtwdev);
  1156. if (ret) {
  1157. rtw_err(rtwdev, "failed to start hci\n");
  1158. goto err_off;
  1159. }
  1160. /* send H2C after HCI has started */
  1161. rtw_fw_send_general_info(rtwdev);
  1162. rtw_fw_send_phydm_info(rtwdev);
  1163. wifi_only = !rtwdev->efuse.btcoex;
  1164. rtw_coex_power_on_setting(rtwdev);
  1165. rtw_coex_init_hw_config(rtwdev, wifi_only);
  1166. return 0;
  1167. err_off:
  1168. rtw_mac_power_off(rtwdev);
  1169. err:
  1170. return ret;
  1171. }
  1172. void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start)
  1173. {
  1174. if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN))
  1175. return;
  1176. if (start) {
  1177. rtw_fw_scan_notify(rtwdev, true);
  1178. } else {
  1179. reinit_completion(&rtwdev->fw_scan_density);
  1180. rtw_fw_scan_notify(rtwdev, false);
  1181. if (!wait_for_completion_timeout(&rtwdev->fw_scan_density,
  1182. SCAN_NOTIFY_TIMEOUT))
  1183. rtw_warn(rtwdev, "firmware failed to report density after scan\n");
  1184. }
  1185. }
  1186. void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
  1187. const u8 *mac_addr, bool hw_scan)
  1188. {
  1189. u32 config = 0;
  1190. int ret = 0;
  1191. rtw_leave_lps(rtwdev);
  1192. if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) {
  1193. ret = rtw_leave_ips(rtwdev);
  1194. if (ret) {
  1195. rtw_err(rtwdev, "failed to leave idle state\n");
  1196. return;
  1197. }
  1198. }
  1199. ether_addr_copy(rtwvif->mac_addr, mac_addr);
  1200. config |= PORT_SET_MAC_ADDR;
  1201. rtw_vif_port_config(rtwdev, rtwvif, config);
  1202. rtw_coex_scan_notify(rtwdev, COEX_SCAN_START);
  1203. rtw_core_fw_scan_notify(rtwdev, true);
  1204. set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
  1205. set_bit(RTW_FLAG_SCANNING, rtwdev->flags);
  1206. }
  1207. void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
  1208. bool hw_scan)
  1209. {
  1210. struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL;
  1211. u32 config = 0;
  1212. if (!rtwvif)
  1213. return;
  1214. clear_bit(RTW_FLAG_SCANNING, rtwdev->flags);
  1215. clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
  1216. rtw_core_fw_scan_notify(rtwdev, false);
  1217. ether_addr_copy(rtwvif->mac_addr, vif->addr);
  1218. config |= PORT_SET_MAC_ADDR;
  1219. rtw_vif_port_config(rtwdev, rtwvif, config);
  1220. rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH);
  1221. if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
  1222. ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
  1223. }
  1224. int rtw_core_start(struct rtw_dev *rtwdev)
  1225. {
  1226. int ret;
  1227. ret = rtw_power_on(rtwdev);
  1228. if (ret)
  1229. return ret;
  1230. rtw_sec_enable_sec_engine(rtwdev);
  1231. rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
  1232. rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
  1233. /* rcr reset after powered on */
  1234. rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
  1235. ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
  1236. RTW_WATCH_DOG_DELAY_TIME);
  1237. set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
  1238. return 0;
  1239. }
  1240. static void rtw_power_off(struct rtw_dev *rtwdev)
  1241. {
  1242. rtw_hci_stop(rtwdev);
  1243. rtw_coex_power_off_setting(rtwdev);
  1244. rtw_mac_power_off(rtwdev);
  1245. }
  1246. void rtw_core_stop(struct rtw_dev *rtwdev)
  1247. {
  1248. struct rtw_coex *coex = &rtwdev->coex;
  1249. clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
  1250. clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
  1251. mutex_unlock(&rtwdev->mutex);
  1252. cancel_work_sync(&rtwdev->c2h_work);
  1253. cancel_work_sync(&rtwdev->update_beacon_work);
  1254. cancel_delayed_work_sync(&rtwdev->watch_dog_work);
  1255. cancel_delayed_work_sync(&coex->bt_relink_work);
  1256. cancel_delayed_work_sync(&coex->bt_reenable_work);
  1257. cancel_delayed_work_sync(&coex->defreeze_work);
  1258. cancel_delayed_work_sync(&coex->wl_remain_work);
  1259. cancel_delayed_work_sync(&coex->bt_remain_work);
  1260. cancel_delayed_work_sync(&coex->wl_connecting_work);
  1261. cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
  1262. cancel_delayed_work_sync(&coex->wl_ccklock_work);
  1263. mutex_lock(&rtwdev->mutex);
  1264. rtw_power_off(rtwdev);
  1265. }
  1266. static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
  1267. struct ieee80211_sta_ht_cap *ht_cap)
  1268. {
  1269. const struct rtw_chip_info *chip = rtwdev->chip;
  1270. struct rtw_efuse *efuse = &rtwdev->efuse;
  1271. ht_cap->ht_supported = true;
  1272. ht_cap->cap = 0;
  1273. ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
  1274. IEEE80211_HT_CAP_MAX_AMSDU |
  1275. (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
  1276. if (rtw_chip_has_rx_ldpc(rtwdev))
  1277. ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
  1278. if (rtw_chip_has_tx_stbc(rtwdev))
  1279. ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
  1280. if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
  1281. ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  1282. IEEE80211_HT_CAP_DSSSCCK40 |
  1283. IEEE80211_HT_CAP_SGI_40;
  1284. ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  1285. ht_cap->ampdu_density = chip->ampdu_density;
  1286. ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  1287. if (efuse->hw_cap.nss > 1) {
  1288. ht_cap->mcs.rx_mask[0] = 0xFF;
  1289. ht_cap->mcs.rx_mask[1] = 0xFF;
  1290. ht_cap->mcs.rx_mask[4] = 0x01;
  1291. ht_cap->mcs.rx_highest = cpu_to_le16(300);
  1292. } else {
  1293. ht_cap->mcs.rx_mask[0] = 0xFF;
  1294. ht_cap->mcs.rx_mask[1] = 0x00;
  1295. ht_cap->mcs.rx_mask[4] = 0x01;
  1296. ht_cap->mcs.rx_highest = cpu_to_le16(150);
  1297. }
  1298. }
  1299. static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
  1300. struct ieee80211_sta_vht_cap *vht_cap)
  1301. {
  1302. struct rtw_efuse *efuse = &rtwdev->efuse;
  1303. u16 mcs_map;
  1304. __le16 highest;
  1305. if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
  1306. efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
  1307. return;
  1308. vht_cap->vht_supported = true;
  1309. vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
  1310. IEEE80211_VHT_CAP_SHORT_GI_80 |
  1311. IEEE80211_VHT_CAP_RXSTBC_1 |
  1312. IEEE80211_VHT_CAP_HTC_VHT |
  1313. IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
  1314. 0;
  1315. if (rtwdev->hal.rf_path_num > 1)
  1316. vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
  1317. vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
  1318. IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
  1319. vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
  1320. IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
  1321. if (rtw_chip_has_rx_ldpc(rtwdev))
  1322. vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
  1323. mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
  1324. IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
  1325. IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
  1326. IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
  1327. IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
  1328. IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
  1329. IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
  1330. if (efuse->hw_cap.nss > 1) {
  1331. highest = cpu_to_le16(780);
  1332. mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2;
  1333. } else {
  1334. highest = cpu_to_le16(390);
  1335. mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2;
  1336. }
  1337. vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
  1338. vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
  1339. vht_cap->vht_mcs.rx_highest = highest;
  1340. vht_cap->vht_mcs.tx_highest = highest;
  1341. }
  1342. static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev)
  1343. {
  1344. u16 len;
  1345. len = rtwdev->chip->max_scan_ie_len;
  1346. if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) &&
  1347. rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
  1348. len = IEEE80211_MAX_DATA_LEN;
  1349. else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM))
  1350. len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE;
  1351. return len;
  1352. }
  1353. static void rtw_set_supported_band(struct ieee80211_hw *hw,
  1354. const struct rtw_chip_info *chip)
  1355. {
  1356. struct rtw_dev *rtwdev = hw->priv;
  1357. struct ieee80211_supported_band *sband;
  1358. if (chip->band & RTW_BAND_2G) {
  1359. sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
  1360. if (!sband)
  1361. goto err_out;
  1362. if (chip->ht_supported)
  1363. rtw_init_ht_cap(rtwdev, &sband->ht_cap);
  1364. hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
  1365. }
  1366. if (chip->band & RTW_BAND_5G) {
  1367. sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
  1368. if (!sband)
  1369. goto err_out;
  1370. if (chip->ht_supported)
  1371. rtw_init_ht_cap(rtwdev, &sband->ht_cap);
  1372. if (chip->vht_supported)
  1373. rtw_init_vht_cap(rtwdev, &sband->vht_cap);
  1374. hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
  1375. }
  1376. return;
  1377. err_out:
  1378. rtw_err(rtwdev, "failed to set supported band\n");
  1379. }
  1380. static void rtw_unset_supported_band(struct ieee80211_hw *hw,
  1381. const struct rtw_chip_info *chip)
  1382. {
  1383. kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
  1384. kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
  1385. }
  1386. static void rtw_vif_smps_iter(void *data, u8 *mac,
  1387. struct ieee80211_vif *vif)
  1388. {
  1389. struct rtw_dev *rtwdev = (struct rtw_dev *)data;
  1390. if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
  1391. return;
  1392. if (rtwdev->hal.txrx_1ss)
  1393. ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC);
  1394. else
  1395. ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF);
  1396. }
  1397. void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss)
  1398. {
  1399. const struct rtw_chip_info *chip = rtwdev->chip;
  1400. struct rtw_hal *hal = &rtwdev->hal;
  1401. if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss)
  1402. return;
  1403. rtwdev->hal.txrx_1ss = txrx_1ss;
  1404. if (txrx_1ss)
  1405. chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false);
  1406. else
  1407. chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx,
  1408. hal->antenna_rx, false);
  1409. rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev);
  1410. }
  1411. static void __update_firmware_feature(struct rtw_dev *rtwdev,
  1412. struct rtw_fw_state *fw)
  1413. {
  1414. u32 feature;
  1415. const struct rtw_fw_hdr *fw_hdr =
  1416. (const struct rtw_fw_hdr *)fw->firmware->data;
  1417. feature = le32_to_cpu(fw_hdr->feature);
  1418. fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
  1419. if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C &&
  1420. RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13))
  1421. fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM;
  1422. }
  1423. static void __update_firmware_info(struct rtw_dev *rtwdev,
  1424. struct rtw_fw_state *fw)
  1425. {
  1426. const struct rtw_fw_hdr *fw_hdr =
  1427. (const struct rtw_fw_hdr *)fw->firmware->data;
  1428. fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
  1429. fw->version = le16_to_cpu(fw_hdr->version);
  1430. fw->sub_version = fw_hdr->subversion;
  1431. fw->sub_index = fw_hdr->subindex;
  1432. __update_firmware_feature(rtwdev, fw);
  1433. }
  1434. static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
  1435. struct rtw_fw_state *fw)
  1436. {
  1437. struct rtw_fw_hdr_legacy *legacy =
  1438. (struct rtw_fw_hdr_legacy *)fw->firmware->data;
  1439. fw->h2c_version = 0;
  1440. fw->version = le16_to_cpu(legacy->version);
  1441. fw->sub_version = legacy->subversion1;
  1442. fw->sub_index = legacy->subversion2;
  1443. }
  1444. static void update_firmware_info(struct rtw_dev *rtwdev,
  1445. struct rtw_fw_state *fw)
  1446. {
  1447. if (rtw_chip_wcpu_11n(rtwdev))
  1448. __update_firmware_info_legacy(rtwdev, fw);
  1449. else
  1450. __update_firmware_info(rtwdev, fw);
  1451. }
  1452. static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
  1453. {
  1454. struct rtw_fw_state *fw = context;
  1455. struct rtw_dev *rtwdev = fw->rtwdev;
  1456. if (!firmware || !firmware->data) {
  1457. rtw_err(rtwdev, "failed to request firmware\n");
  1458. complete_all(&fw->completion);
  1459. return;
  1460. }
  1461. fw->firmware = firmware;
  1462. update_firmware_info(rtwdev, fw);
  1463. complete_all(&fw->completion);
  1464. rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n",
  1465. fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
  1466. }
  1467. static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
  1468. {
  1469. const char *fw_name;
  1470. struct rtw_fw_state *fw;
  1471. int ret;
  1472. switch (type) {
  1473. case RTW_WOWLAN_FW:
  1474. fw = &rtwdev->wow_fw;
  1475. fw_name = rtwdev->chip->wow_fw_name;
  1476. break;
  1477. case RTW_NORMAL_FW:
  1478. fw = &rtwdev->fw;
  1479. fw_name = rtwdev->chip->fw_name;
  1480. break;
  1481. default:
  1482. rtw_warn(rtwdev, "unsupported firmware type\n");
  1483. return -ENOENT;
  1484. }
  1485. fw->rtwdev = rtwdev;
  1486. init_completion(&fw->completion);
  1487. ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
  1488. GFP_KERNEL, fw, rtw_load_firmware_cb);
  1489. if (ret) {
  1490. rtw_err(rtwdev, "failed to async firmware request\n");
  1491. return ret;
  1492. }
  1493. return 0;
  1494. }
  1495. static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
  1496. {
  1497. const struct rtw_chip_info *chip = rtwdev->chip;
  1498. struct rtw_hal *hal = &rtwdev->hal;
  1499. struct rtw_efuse *efuse = &rtwdev->efuse;
  1500. switch (rtw_hci_type(rtwdev)) {
  1501. case RTW_HCI_TYPE_PCIE:
  1502. rtwdev->hci.rpwm_addr = 0x03d9;
  1503. rtwdev->hci.cpwm_addr = 0x03da;
  1504. break;
  1505. default:
  1506. rtw_err(rtwdev, "unsupported hci type\n");
  1507. return -EINVAL;
  1508. }
  1509. hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
  1510. hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
  1511. hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
  1512. if (hal->chip_version & BIT_RF_TYPE_ID) {
  1513. hal->rf_type = RF_2T2R;
  1514. hal->rf_path_num = 2;
  1515. hal->antenna_tx = BB_PATH_AB;
  1516. hal->antenna_rx = BB_PATH_AB;
  1517. } else {
  1518. hal->rf_type = RF_1T1R;
  1519. hal->rf_path_num = 1;
  1520. hal->antenna_tx = BB_PATH_A;
  1521. hal->antenna_rx = BB_PATH_A;
  1522. }
  1523. hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
  1524. hal->rf_path_num;
  1525. efuse->physical_size = chip->phy_efuse_size;
  1526. efuse->logical_size = chip->log_efuse_size;
  1527. efuse->protect_size = chip->ptct_efuse_size;
  1528. /* default use ack */
  1529. rtwdev->hal.rcr |= BIT_VHT_DACK;
  1530. hal->bfee_sts_cap = 3;
  1531. return 0;
  1532. }
  1533. static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
  1534. {
  1535. struct rtw_fw_state *fw = &rtwdev->fw;
  1536. int ret;
  1537. ret = rtw_hci_setup(rtwdev);
  1538. if (ret) {
  1539. rtw_err(rtwdev, "failed to setup hci\n");
  1540. goto err;
  1541. }
  1542. ret = rtw_mac_power_on(rtwdev);
  1543. if (ret) {
  1544. rtw_err(rtwdev, "failed to power on mac\n");
  1545. goto err;
  1546. }
  1547. rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
  1548. wait_for_completion(&fw->completion);
  1549. if (!fw->firmware) {
  1550. ret = -EINVAL;
  1551. rtw_err(rtwdev, "failed to load firmware\n");
  1552. goto err;
  1553. }
  1554. ret = rtw_download_firmware(rtwdev, fw);
  1555. if (ret) {
  1556. rtw_err(rtwdev, "failed to download firmware\n");
  1557. goto err_off;
  1558. }
  1559. return 0;
  1560. err_off:
  1561. rtw_mac_power_off(rtwdev);
  1562. err:
  1563. return ret;
  1564. }
  1565. static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
  1566. {
  1567. struct rtw_efuse *efuse = &rtwdev->efuse;
  1568. u8 hw_feature[HW_FEATURE_LEN];
  1569. u8 id;
  1570. u8 bw;
  1571. int i;
  1572. id = rtw_read8(rtwdev, REG_C2HEVT);
  1573. if (id != C2H_HW_FEATURE_REPORT) {
  1574. rtw_err(rtwdev, "failed to read hw feature report\n");
  1575. return -EBUSY;
  1576. }
  1577. for (i = 0; i < HW_FEATURE_LEN; i++)
  1578. hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
  1579. rtw_write8(rtwdev, REG_C2HEVT, 0);
  1580. bw = GET_EFUSE_HW_CAP_BW(hw_feature);
  1581. efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
  1582. efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
  1583. efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
  1584. efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
  1585. efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
  1586. rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
  1587. if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
  1588. efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
  1589. efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
  1590. rtw_dbg(rtwdev, RTW_DBG_EFUSE,
  1591. "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
  1592. efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
  1593. efuse->hw_cap.ant_num, efuse->hw_cap.nss);
  1594. return 0;
  1595. }
  1596. static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
  1597. {
  1598. rtw_hci_stop(rtwdev);
  1599. rtw_mac_power_off(rtwdev);
  1600. }
  1601. static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
  1602. {
  1603. struct rtw_efuse *efuse = &rtwdev->efuse;
  1604. int ret;
  1605. mutex_lock(&rtwdev->mutex);
  1606. /* power on mac to read efuse */
  1607. ret = rtw_chip_efuse_enable(rtwdev);
  1608. if (ret)
  1609. goto out_unlock;
  1610. ret = rtw_parse_efuse_map(rtwdev);
  1611. if (ret)
  1612. goto out_disable;
  1613. ret = rtw_dump_hw_feature(rtwdev);
  1614. if (ret)
  1615. goto out_disable;
  1616. ret = rtw_check_supported_rfe(rtwdev);
  1617. if (ret)
  1618. goto out_disable;
  1619. if (efuse->crystal_cap == 0xff)
  1620. efuse->crystal_cap = 0;
  1621. if (efuse->pa_type_2g == 0xff)
  1622. efuse->pa_type_2g = 0;
  1623. if (efuse->pa_type_5g == 0xff)
  1624. efuse->pa_type_5g = 0;
  1625. if (efuse->lna_type_2g == 0xff)
  1626. efuse->lna_type_2g = 0;
  1627. if (efuse->lna_type_5g == 0xff)
  1628. efuse->lna_type_5g = 0;
  1629. if (efuse->channel_plan == 0xff)
  1630. efuse->channel_plan = 0x7f;
  1631. if (efuse->rf_board_option == 0xff)
  1632. efuse->rf_board_option = 0;
  1633. if (efuse->bt_setting & BIT(0))
  1634. efuse->share_ant = true;
  1635. if (efuse->regd == 0xff)
  1636. efuse->regd = 0;
  1637. if (efuse->tx_bb_swing_setting_2g == 0xff)
  1638. efuse->tx_bb_swing_setting_2g = 0;
  1639. if (efuse->tx_bb_swing_setting_5g == 0xff)
  1640. efuse->tx_bb_swing_setting_5g = 0;
  1641. efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
  1642. efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
  1643. efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
  1644. efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
  1645. efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
  1646. out_disable:
  1647. rtw_chip_efuse_disable(rtwdev);
  1648. out_unlock:
  1649. mutex_unlock(&rtwdev->mutex);
  1650. return ret;
  1651. }
  1652. static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
  1653. {
  1654. struct rtw_hal *hal = &rtwdev->hal;
  1655. const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
  1656. if (!rfe_def)
  1657. return -ENODEV;
  1658. rtw_phy_setup_phy_cond(rtwdev, 0);
  1659. rtw_phy_init_tx_power(rtwdev);
  1660. if (rfe_def->agc_btg_tbl)
  1661. rtw_load_table(rtwdev, rfe_def->agc_btg_tbl);
  1662. rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
  1663. rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
  1664. rtw_phy_tx_power_by_rate_config(hal);
  1665. rtw_phy_tx_power_limit_config(hal);
  1666. return 0;
  1667. }
  1668. int rtw_chip_info_setup(struct rtw_dev *rtwdev)
  1669. {
  1670. int ret;
  1671. ret = rtw_chip_parameter_setup(rtwdev);
  1672. if (ret) {
  1673. rtw_err(rtwdev, "failed to setup chip parameters\n");
  1674. goto err_out;
  1675. }
  1676. ret = rtw_chip_efuse_info_setup(rtwdev);
  1677. if (ret) {
  1678. rtw_err(rtwdev, "failed to setup chip efuse info\n");
  1679. goto err_out;
  1680. }
  1681. ret = rtw_chip_board_info_setup(rtwdev);
  1682. if (ret) {
  1683. rtw_err(rtwdev, "failed to setup chip board info\n");
  1684. goto err_out;
  1685. }
  1686. return 0;
  1687. err_out:
  1688. return ret;
  1689. }
  1690. EXPORT_SYMBOL(rtw_chip_info_setup);
  1691. static void rtw_stats_init(struct rtw_dev *rtwdev)
  1692. {
  1693. struct rtw_traffic_stats *stats = &rtwdev->stats;
  1694. struct rtw_dm_info *dm_info = &rtwdev->dm_info;
  1695. int i;
  1696. ewma_tp_init(&stats->tx_ewma_tp);
  1697. ewma_tp_init(&stats->rx_ewma_tp);
  1698. for (i = 0; i < RTW_EVM_NUM; i++)
  1699. ewma_evm_init(&dm_info->ewma_evm[i]);
  1700. for (i = 0; i < RTW_SNR_NUM; i++)
  1701. ewma_snr_init(&dm_info->ewma_snr[i]);
  1702. }
  1703. int rtw_core_init(struct rtw_dev *rtwdev)
  1704. {
  1705. const struct rtw_chip_info *chip = rtwdev->chip;
  1706. struct rtw_coex *coex = &rtwdev->coex;
  1707. int ret;
  1708. INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
  1709. INIT_LIST_HEAD(&rtwdev->txqs);
  1710. timer_setup(&rtwdev->tx_report.purge_timer,
  1711. rtw_tx_report_purge_timer, 0);
  1712. rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
  1713. if (!rtwdev->tx_wq) {
  1714. rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n");
  1715. return -ENOMEM;
  1716. }
  1717. INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
  1718. INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
  1719. INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
  1720. INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
  1721. INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
  1722. INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
  1723. INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
  1724. INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
  1725. rtw_coex_bt_multi_link_remain_work);
  1726. INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
  1727. INIT_WORK(&rtwdev->tx_work, rtw_tx_work);
  1728. INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
  1729. INIT_WORK(&rtwdev->ips_work, rtw_ips_work);
  1730. INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
  1731. INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work);
  1732. INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
  1733. skb_queue_head_init(&rtwdev->c2h_queue);
  1734. skb_queue_head_init(&rtwdev->coex.queue);
  1735. skb_queue_head_init(&rtwdev->tx_report.queue);
  1736. spin_lock_init(&rtwdev->rf_lock);
  1737. spin_lock_init(&rtwdev->h2c.lock);
  1738. spin_lock_init(&rtwdev->txq_lock);
  1739. spin_lock_init(&rtwdev->tx_report.q_lock);
  1740. mutex_init(&rtwdev->mutex);
  1741. mutex_init(&rtwdev->coex.mutex);
  1742. mutex_init(&rtwdev->hal.tx_power_mutex);
  1743. init_waitqueue_head(&rtwdev->coex.wait);
  1744. init_completion(&rtwdev->lps_leave_check);
  1745. init_completion(&rtwdev->fw_scan_density);
  1746. rtwdev->sec.total_cam_num = 32;
  1747. rtwdev->hal.current_channel = 1;
  1748. rtwdev->dm_info.fix_rate = U8_MAX;
  1749. set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
  1750. rtw_stats_init(rtwdev);
  1751. /* default rx filter setting */
  1752. rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
  1753. BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
  1754. BIT_AB | BIT_AM | BIT_APM;
  1755. ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
  1756. if (ret) {
  1757. rtw_warn(rtwdev, "no firmware loaded\n");
  1758. goto out;
  1759. }
  1760. if (chip->wow_fw_name) {
  1761. ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
  1762. if (ret) {
  1763. rtw_warn(rtwdev, "no wow firmware loaded\n");
  1764. wait_for_completion(&rtwdev->fw.completion);
  1765. if (rtwdev->fw.firmware)
  1766. release_firmware(rtwdev->fw.firmware);
  1767. goto out;
  1768. }
  1769. }
  1770. return 0;
  1771. out:
  1772. destroy_workqueue(rtwdev->tx_wq);
  1773. return ret;
  1774. }
  1775. EXPORT_SYMBOL(rtw_core_init);
  1776. void rtw_core_deinit(struct rtw_dev *rtwdev)
  1777. {
  1778. struct rtw_fw_state *fw = &rtwdev->fw;
  1779. struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
  1780. struct rtw_rsvd_page *rsvd_pkt, *tmp;
  1781. unsigned long flags;
  1782. rtw_wait_firmware_completion(rtwdev);
  1783. if (fw->firmware)
  1784. release_firmware(fw->firmware);
  1785. if (wow_fw->firmware)
  1786. release_firmware(wow_fw->firmware);
  1787. destroy_workqueue(rtwdev->tx_wq);
  1788. spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
  1789. skb_queue_purge(&rtwdev->tx_report.queue);
  1790. skb_queue_purge(&rtwdev->coex.queue);
  1791. spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
  1792. list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
  1793. build_list) {
  1794. list_del(&rsvd_pkt->build_list);
  1795. kfree(rsvd_pkt);
  1796. }
  1797. mutex_destroy(&rtwdev->mutex);
  1798. mutex_destroy(&rtwdev->coex.mutex);
  1799. mutex_destroy(&rtwdev->hal.tx_power_mutex);
  1800. }
  1801. EXPORT_SYMBOL(rtw_core_deinit);
  1802. int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
  1803. {
  1804. struct rtw_hal *hal = &rtwdev->hal;
  1805. int max_tx_headroom = 0;
  1806. int ret;
  1807. /* TODO: USB & SDIO may need extra room? */
  1808. max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
  1809. hw->extra_tx_headroom = max_tx_headroom;
  1810. hw->queues = IEEE80211_NUM_ACS;
  1811. hw->txq_data_size = sizeof(struct rtw_txq);
  1812. hw->sta_data_size = sizeof(struct rtw_sta_info);
  1813. hw->vif_data_size = sizeof(struct rtw_vif);
  1814. ieee80211_hw_set(hw, SIGNAL_DBM);
  1815. ieee80211_hw_set(hw, RX_INCLUDES_FCS);
  1816. ieee80211_hw_set(hw, AMPDU_AGGREGATION);
  1817. ieee80211_hw_set(hw, MFP_CAPABLE);
  1818. ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
  1819. ieee80211_hw_set(hw, SUPPORTS_PS);
  1820. ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
  1821. ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
  1822. ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
  1823. ieee80211_hw_set(hw, HAS_RATE_CONTROL);
  1824. ieee80211_hw_set(hw, TX_AMSDU);
  1825. ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
  1826. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
  1827. BIT(NL80211_IFTYPE_AP) |
  1828. BIT(NL80211_IFTYPE_ADHOC) |
  1829. BIT(NL80211_IFTYPE_MESH_POINT);
  1830. hw->wiphy->available_antennas_tx = hal->antenna_tx;
  1831. hw->wiphy->available_antennas_rx = hal->antenna_rx;
  1832. hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
  1833. WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
  1834. hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
  1835. hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS;
  1836. hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev);
  1837. wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
  1838. wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
  1839. wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
  1840. #ifdef CONFIG_PM
  1841. hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
  1842. hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
  1843. #endif
  1844. rtw_set_supported_band(hw, rtwdev->chip);
  1845. SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
  1846. hw->wiphy->sar_capa = &rtw_sar_capa;
  1847. ret = rtw_regd_init(rtwdev);
  1848. if (ret) {
  1849. rtw_err(rtwdev, "failed to init regd\n");
  1850. return ret;
  1851. }
  1852. ret = ieee80211_register_hw(hw);
  1853. if (ret) {
  1854. rtw_err(rtwdev, "failed to register hw\n");
  1855. return ret;
  1856. }
  1857. ret = rtw_regd_hint(rtwdev);
  1858. if (ret) {
  1859. rtw_err(rtwdev, "failed to hint regd\n");
  1860. return ret;
  1861. }
  1862. rtw_debugfs_init(rtwdev);
  1863. rtwdev->bf_info.bfer_mu_cnt = 0;
  1864. rtwdev->bf_info.bfer_su_cnt = 0;
  1865. return 0;
  1866. }
  1867. EXPORT_SYMBOL(rtw_register_hw);
  1868. void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
  1869. {
  1870. const struct rtw_chip_info *chip = rtwdev->chip;
  1871. ieee80211_unregister_hw(hw);
  1872. rtw_unset_supported_band(hw, chip);
  1873. }
  1874. EXPORT_SYMBOL(rtw_unregister_hw);
  1875. MODULE_AUTHOR("Realtek Corporation");
  1876. MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
  1877. MODULE_LICENSE("Dual BSD/GPL");