rt2400pci.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. Copyright (C) 2004 - 2009 Ivo van Doorn <[email protected]>
  4. <http://rt2x00.serialmonkey.com>
  5. */
  6. /*
  7. Module: rt2400pci
  8. Abstract: rt2400pci device specific routines.
  9. Supported chipsets: RT2460.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/etherdevice.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/pci.h>
  16. #include <linux/eeprom_93cx6.h>
  17. #include <linux/slab.h>
  18. #include "rt2x00.h"
  19. #include "rt2x00mmio.h"
  20. #include "rt2x00pci.h"
  21. #include "rt2400pci.h"
  22. /*
  23. * Register access.
  24. * All access to the CSR registers will go through the methods
  25. * rt2x00mmio_register_read and rt2x00mmio_register_write.
  26. * BBP and RF register require indirect register access,
  27. * and use the CSR registers BBPCSR and RFCSR to achieve this.
  28. * These indirect registers work with busy bits,
  29. * and we will try maximal REGISTER_BUSY_COUNT times to access
  30. * the register while taking a REGISTER_BUSY_DELAY us delay
  31. * between each attempt. When the busy bit is still set at that time,
  32. * the access attempt is considered to have failed,
  33. * and we will print an error.
  34. */
  35. #define WAIT_FOR_BBP(__dev, __reg) \
  36. rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  37. #define WAIT_FOR_RF(__dev, __reg) \
  38. rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  39. static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  40. const unsigned int word, const u8 value)
  41. {
  42. u32 reg;
  43. mutex_lock(&rt2x00dev->csr_mutex);
  44. /*
  45. * Wait until the BBP becomes available, afterwards we
  46. * can safely write the new data into the register.
  47. */
  48. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  49. reg = 0;
  50. rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  51. rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  52. rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  53. rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  54. rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
  55. }
  56. mutex_unlock(&rt2x00dev->csr_mutex);
  57. }
  58. static u8 rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  59. const unsigned int word)
  60. {
  61. u32 reg;
  62. u8 value;
  63. mutex_lock(&rt2x00dev->csr_mutex);
  64. /*
  65. * Wait until the BBP becomes available, afterwards we
  66. * can safely write the read request into the register.
  67. * After the data has been written, we wait until hardware
  68. * returns the correct value, if at any time the register
  69. * doesn't become available in time, reg will be 0xffffffff
  70. * which means we return 0xff to the caller.
  71. */
  72. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  73. reg = 0;
  74. rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  75. rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  76. rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
  77. rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
  78. WAIT_FOR_BBP(rt2x00dev, &reg);
  79. }
  80. value = rt2x00_get_field32(reg, BBPCSR_VALUE);
  81. mutex_unlock(&rt2x00dev->csr_mutex);
  82. return value;
  83. }
  84. static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
  85. const unsigned int word, const u32 value)
  86. {
  87. u32 reg;
  88. mutex_lock(&rt2x00dev->csr_mutex);
  89. /*
  90. * Wait until the RF becomes available, afterwards we
  91. * can safely write the new data into the register.
  92. */
  93. if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  94. reg = 0;
  95. rt2x00_set_field32(&reg, RFCSR_VALUE, value);
  96. rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
  97. rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
  98. rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
  99. rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
  100. rt2x00_rf_write(rt2x00dev, word, value);
  101. }
  102. mutex_unlock(&rt2x00dev->csr_mutex);
  103. }
  104. static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  105. {
  106. struct rt2x00_dev *rt2x00dev = eeprom->data;
  107. u32 reg;
  108. reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
  109. eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
  110. eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
  111. eeprom->reg_data_clock =
  112. !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
  113. eeprom->reg_chip_select =
  114. !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
  115. }
  116. static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  117. {
  118. struct rt2x00_dev *rt2x00dev = eeprom->data;
  119. u32 reg = 0;
  120. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
  121. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
  122. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
  123. !!eeprom->reg_data_clock);
  124. rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
  125. !!eeprom->reg_chip_select);
  126. rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
  127. }
  128. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  129. static const struct rt2x00debug rt2400pci_rt2x00debug = {
  130. .owner = THIS_MODULE,
  131. .csr = {
  132. .read = rt2x00mmio_register_read,
  133. .write = rt2x00mmio_register_write,
  134. .flags = RT2X00DEBUGFS_OFFSET,
  135. .word_base = CSR_REG_BASE,
  136. .word_size = sizeof(u32),
  137. .word_count = CSR_REG_SIZE / sizeof(u32),
  138. },
  139. .eeprom = {
  140. .read = rt2x00_eeprom_read,
  141. .write = rt2x00_eeprom_write,
  142. .word_base = EEPROM_BASE,
  143. .word_size = sizeof(u16),
  144. .word_count = EEPROM_SIZE / sizeof(u16),
  145. },
  146. .bbp = {
  147. .read = rt2400pci_bbp_read,
  148. .write = rt2400pci_bbp_write,
  149. .word_base = BBP_BASE,
  150. .word_size = sizeof(u8),
  151. .word_count = BBP_SIZE / sizeof(u8),
  152. },
  153. .rf = {
  154. .read = rt2x00_rf_read,
  155. .write = rt2400pci_rf_write,
  156. .word_base = RF_BASE,
  157. .word_size = sizeof(u32),
  158. .word_count = RF_SIZE / sizeof(u32),
  159. },
  160. };
  161. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  162. static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  163. {
  164. u32 reg;
  165. reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
  166. return rt2x00_get_field32(reg, GPIOCSR_VAL0);
  167. }
  168. #ifdef CONFIG_RT2X00_LIB_LEDS
  169. static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
  170. enum led_brightness brightness)
  171. {
  172. struct rt2x00_led *led =
  173. container_of(led_cdev, struct rt2x00_led, led_dev);
  174. unsigned int enabled = brightness != LED_OFF;
  175. u32 reg;
  176. reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
  177. if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
  178. rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
  179. else if (led->type == LED_TYPE_ACTIVITY)
  180. rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
  181. rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
  182. }
  183. static int rt2400pci_blink_set(struct led_classdev *led_cdev,
  184. unsigned long *delay_on,
  185. unsigned long *delay_off)
  186. {
  187. struct rt2x00_led *led =
  188. container_of(led_cdev, struct rt2x00_led, led_dev);
  189. u32 reg;
  190. reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
  191. rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
  192. rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
  193. rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
  194. return 0;
  195. }
  196. static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
  197. struct rt2x00_led *led,
  198. enum led_type type)
  199. {
  200. led->rt2x00dev = rt2x00dev;
  201. led->type = type;
  202. led->led_dev.brightness_set = rt2400pci_brightness_set;
  203. led->led_dev.blink_set = rt2400pci_blink_set;
  204. led->flags = LED_INITIALIZED;
  205. }
  206. #endif /* CONFIG_RT2X00_LIB_LEDS */
  207. /*
  208. * Configuration handlers.
  209. */
  210. static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
  211. const unsigned int filter_flags)
  212. {
  213. u32 reg;
  214. /*
  215. * Start configuration steps.
  216. * Note that the version error will always be dropped
  217. * since there is no filter for it at this time.
  218. */
  219. reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
  220. rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
  221. !(filter_flags & FIF_FCSFAIL));
  222. rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
  223. !(filter_flags & FIF_PLCPFAIL));
  224. rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
  225. !(filter_flags & FIF_CONTROL));
  226. rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
  227. !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
  228. rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
  229. !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
  230. !rt2x00dev->intf_ap_count);
  231. rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
  232. rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
  233. }
  234. static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
  235. struct rt2x00_intf *intf,
  236. struct rt2x00intf_conf *conf,
  237. const unsigned int flags)
  238. {
  239. unsigned int bcn_preload;
  240. u32 reg;
  241. if (flags & CONFIG_UPDATE_TYPE) {
  242. /*
  243. * Enable beacon config
  244. */
  245. bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
  246. reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);
  247. rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
  248. rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
  249. /*
  250. * Enable synchronisation.
  251. */
  252. reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
  253. rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
  254. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  255. }
  256. if (flags & CONFIG_UPDATE_MAC)
  257. rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
  258. conf->mac, sizeof(conf->mac));
  259. if (flags & CONFIG_UPDATE_BSSID)
  260. rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
  261. conf->bssid,
  262. sizeof(conf->bssid));
  263. }
  264. static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
  265. struct rt2x00lib_erp *erp,
  266. u32 changed)
  267. {
  268. int preamble_mask;
  269. u32 reg;
  270. /*
  271. * When short preamble is enabled, we should set bit 0x08
  272. */
  273. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  274. preamble_mask = erp->short_preamble << 3;
  275. reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);
  276. rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
  277. rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
  278. rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
  279. rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
  280. rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
  281. reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);
  282. rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
  283. rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
  284. rt2x00_set_field32(&reg, ARCSR2_LENGTH,
  285. GET_DURATION(ACK_SIZE, 10));
  286. rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
  287. reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);
  288. rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
  289. rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
  290. rt2x00_set_field32(&reg, ARCSR2_LENGTH,
  291. GET_DURATION(ACK_SIZE, 20));
  292. rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
  293. reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);
  294. rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
  295. rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
  296. rt2x00_set_field32(&reg, ARCSR2_LENGTH,
  297. GET_DURATION(ACK_SIZE, 55));
  298. rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
  299. reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);
  300. rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
  301. rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
  302. rt2x00_set_field32(&reg, ARCSR2_LENGTH,
  303. GET_DURATION(ACK_SIZE, 110));
  304. rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
  305. }
  306. if (changed & BSS_CHANGED_BASIC_RATES)
  307. rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
  308. if (changed & BSS_CHANGED_ERP_SLOT) {
  309. reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
  310. rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
  311. rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
  312. reg = rt2x00mmio_register_read(rt2x00dev, CSR18);
  313. rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
  314. rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
  315. rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
  316. reg = rt2x00mmio_register_read(rt2x00dev, CSR19);
  317. rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
  318. rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
  319. rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
  320. }
  321. if (changed & BSS_CHANGED_BEACON_INT) {
  322. reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
  323. rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
  324. erp->beacon_int * 16);
  325. rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
  326. erp->beacon_int * 16);
  327. rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
  328. }
  329. }
  330. static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
  331. struct antenna_setup *ant)
  332. {
  333. u8 r1;
  334. u8 r4;
  335. /*
  336. * We should never come here because rt2x00lib is supposed
  337. * to catch this and send us the correct antenna explicitely.
  338. */
  339. BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
  340. ant->tx == ANTENNA_SW_DIVERSITY);
  341. r4 = rt2400pci_bbp_read(rt2x00dev, 4);
  342. r1 = rt2400pci_bbp_read(rt2x00dev, 1);
  343. /*
  344. * Configure the TX antenna.
  345. */
  346. switch (ant->tx) {
  347. case ANTENNA_HW_DIVERSITY:
  348. rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
  349. break;
  350. case ANTENNA_A:
  351. rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
  352. break;
  353. case ANTENNA_B:
  354. default:
  355. rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
  356. break;
  357. }
  358. /*
  359. * Configure the RX antenna.
  360. */
  361. switch (ant->rx) {
  362. case ANTENNA_HW_DIVERSITY:
  363. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
  364. break;
  365. case ANTENNA_A:
  366. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
  367. break;
  368. case ANTENNA_B:
  369. default:
  370. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
  371. break;
  372. }
  373. rt2400pci_bbp_write(rt2x00dev, 4, r4);
  374. rt2400pci_bbp_write(rt2x00dev, 1, r1);
  375. }
  376. static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
  377. struct rf_channel *rf)
  378. {
  379. /*
  380. * Switch on tuning bits.
  381. */
  382. rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
  383. rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
  384. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  385. rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
  386. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  387. /*
  388. * RF2420 chipset don't need any additional actions.
  389. */
  390. if (rt2x00_rf(rt2x00dev, RF2420))
  391. return;
  392. /*
  393. * For the RT2421 chipsets we need to write an invalid
  394. * reference clock rate to activate auto_tune.
  395. * After that we set the value back to the correct channel.
  396. */
  397. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  398. rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
  399. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  400. msleep(1);
  401. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  402. rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
  403. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  404. msleep(1);
  405. /*
  406. * Switch off tuning bits.
  407. */
  408. rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
  409. rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
  410. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  411. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  412. /*
  413. * Clear false CRC during channel switch.
  414. */
  415. rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0);
  416. }
  417. static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
  418. {
  419. rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
  420. }
  421. static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
  422. struct rt2x00lib_conf *libconf)
  423. {
  424. u32 reg;
  425. reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
  426. rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
  427. libconf->conf->long_frame_max_tx_count);
  428. rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
  429. libconf->conf->short_frame_max_tx_count);
  430. rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
  431. }
  432. static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
  433. struct rt2x00lib_conf *libconf)
  434. {
  435. enum dev_state state =
  436. (libconf->conf->flags & IEEE80211_CONF_PS) ?
  437. STATE_SLEEP : STATE_AWAKE;
  438. u32 reg;
  439. if (state == STATE_SLEEP) {
  440. reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
  441. rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
  442. (rt2x00dev->beacon_int - 20) * 16);
  443. rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
  444. libconf->conf->listen_interval - 1);
  445. /* We must first disable autowake before it can be enabled */
  446. rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
  447. rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
  448. rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
  449. rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
  450. } else {
  451. reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
  452. rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
  453. rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
  454. }
  455. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  456. }
  457. static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
  458. struct rt2x00lib_conf *libconf,
  459. const unsigned int flags)
  460. {
  461. if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
  462. rt2400pci_config_channel(rt2x00dev, &libconf->rf);
  463. if (flags & IEEE80211_CONF_CHANGE_POWER)
  464. rt2400pci_config_txpower(rt2x00dev,
  465. libconf->conf->power_level);
  466. if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  467. rt2400pci_config_retry_limit(rt2x00dev, libconf);
  468. if (flags & IEEE80211_CONF_CHANGE_PS)
  469. rt2400pci_config_ps(rt2x00dev, libconf);
  470. }
  471. static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
  472. const int cw_min, const int cw_max)
  473. {
  474. u32 reg;
  475. reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
  476. rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
  477. rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
  478. rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
  479. }
  480. /*
  481. * Link tuning
  482. */
  483. static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
  484. struct link_qual *qual)
  485. {
  486. u32 reg;
  487. u8 bbp;
  488. /*
  489. * Update FCS error count from register.
  490. */
  491. reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
  492. qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
  493. /*
  494. * Update False CCA count from register.
  495. */
  496. bbp = rt2400pci_bbp_read(rt2x00dev, 39);
  497. qual->false_cca = bbp;
  498. }
  499. static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
  500. struct link_qual *qual, u8 vgc_level)
  501. {
  502. if (qual->vgc_level_reg != vgc_level) {
  503. rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
  504. qual->vgc_level = vgc_level;
  505. qual->vgc_level_reg = vgc_level;
  506. }
  507. }
  508. static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
  509. struct link_qual *qual)
  510. {
  511. rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
  512. }
  513. static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
  514. struct link_qual *qual, const u32 count)
  515. {
  516. /*
  517. * The link tuner should not run longer then 60 seconds,
  518. * and should run once every 2 seconds.
  519. */
  520. if (count > 60 || !(count & 1))
  521. return;
  522. /*
  523. * Base r13 link tuning on the false cca count.
  524. */
  525. if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
  526. rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
  527. else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
  528. rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
  529. }
  530. /*
  531. * Queue handlers.
  532. */
  533. static void rt2400pci_start_queue(struct data_queue *queue)
  534. {
  535. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  536. u32 reg;
  537. switch (queue->qid) {
  538. case QID_RX:
  539. reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
  540. rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
  541. rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
  542. break;
  543. case QID_BEACON:
  544. reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
  545. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
  546. rt2x00_set_field32(&reg, CSR14_TBCN, 1);
  547. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
  548. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  549. break;
  550. default:
  551. break;
  552. }
  553. }
  554. static void rt2400pci_kick_queue(struct data_queue *queue)
  555. {
  556. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  557. u32 reg;
  558. switch (queue->qid) {
  559. case QID_AC_VO:
  560. reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
  561. rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
  562. rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
  563. break;
  564. case QID_AC_VI:
  565. reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
  566. rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
  567. rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
  568. break;
  569. case QID_ATIM:
  570. reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
  571. rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
  572. rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
  573. break;
  574. default:
  575. break;
  576. }
  577. }
  578. static void rt2400pci_stop_queue(struct data_queue *queue)
  579. {
  580. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  581. u32 reg;
  582. switch (queue->qid) {
  583. case QID_AC_VO:
  584. case QID_AC_VI:
  585. case QID_ATIM:
  586. reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
  587. rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
  588. rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
  589. break;
  590. case QID_RX:
  591. reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
  592. rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
  593. rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
  594. break;
  595. case QID_BEACON:
  596. reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
  597. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
  598. rt2x00_set_field32(&reg, CSR14_TBCN, 0);
  599. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
  600. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  601. /*
  602. * Wait for possibly running tbtt tasklets.
  603. */
  604. tasklet_kill(&rt2x00dev->tbtt_tasklet);
  605. break;
  606. default:
  607. break;
  608. }
  609. }
  610. /*
  611. * Initialization functions.
  612. */
  613. static bool rt2400pci_get_entry_state(struct queue_entry *entry)
  614. {
  615. struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
  616. u32 word;
  617. if (entry->queue->qid == QID_RX) {
  618. word = rt2x00_desc_read(entry_priv->desc, 0);
  619. return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
  620. } else {
  621. word = rt2x00_desc_read(entry_priv->desc, 0);
  622. return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  623. rt2x00_get_field32(word, TXD_W0_VALID));
  624. }
  625. }
  626. static void rt2400pci_clear_entry(struct queue_entry *entry)
  627. {
  628. struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
  629. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  630. u32 word;
  631. if (entry->queue->qid == QID_RX) {
  632. word = rt2x00_desc_read(entry_priv->desc, 2);
  633. rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
  634. rt2x00_desc_write(entry_priv->desc, 2, word);
  635. word = rt2x00_desc_read(entry_priv->desc, 1);
  636. rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
  637. rt2x00_desc_write(entry_priv->desc, 1, word);
  638. word = rt2x00_desc_read(entry_priv->desc, 0);
  639. rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
  640. rt2x00_desc_write(entry_priv->desc, 0, word);
  641. } else {
  642. word = rt2x00_desc_read(entry_priv->desc, 0);
  643. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  644. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
  645. rt2x00_desc_write(entry_priv->desc, 0, word);
  646. }
  647. }
  648. static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
  649. {
  650. struct queue_entry_priv_mmio *entry_priv;
  651. u32 reg;
  652. /*
  653. * Initialize registers.
  654. */
  655. reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);
  656. rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
  657. rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
  658. rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
  659. rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
  660. rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
  661. entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
  662. reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);
  663. rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
  664. entry_priv->desc_dma);
  665. rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
  666. entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
  667. reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);
  668. rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
  669. entry_priv->desc_dma);
  670. rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
  671. entry_priv = rt2x00dev->atim->entries[0].priv_data;
  672. reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);
  673. rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
  674. entry_priv->desc_dma);
  675. rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
  676. entry_priv = rt2x00dev->bcn->entries[0].priv_data;
  677. reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);
  678. rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
  679. entry_priv->desc_dma);
  680. rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
  681. reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);
  682. rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
  683. rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
  684. rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
  685. entry_priv = rt2x00dev->rx->entries[0].priv_data;
  686. reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);
  687. rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
  688. entry_priv->desc_dma);
  689. rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
  690. return 0;
  691. }
  692. static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
  693. {
  694. u32 reg;
  695. rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
  696. rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
  697. rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
  698. rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
  699. reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);
  700. rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
  701. rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
  702. rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
  703. rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
  704. reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
  705. rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
  706. (rt2x00dev->rx->data_size / 128));
  707. rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
  708. reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
  709. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
  710. rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
  711. rt2x00_set_field32(&reg, CSR14_TBCN, 0);
  712. rt2x00_set_field32(&reg, CSR14_TCFP, 0);
  713. rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
  714. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
  715. rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
  716. rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
  717. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  718. rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
  719. reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0);
  720. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
  721. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
  722. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
  723. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
  724. rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
  725. reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);
  726. rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
  727. rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
  728. rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
  729. rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
  730. rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
  731. rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
  732. rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
  733. rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
  734. if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
  735. return -EBUSY;
  736. rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
  737. rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
  738. reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);
  739. rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
  740. rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
  741. reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);
  742. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
  743. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
  744. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
  745. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
  746. rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
  747. reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
  748. rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
  749. rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
  750. rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
  751. rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
  752. reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
  753. rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
  754. rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
  755. rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
  756. /*
  757. * We must clear the FCS and FIFO error count.
  758. * These registers are cleared on read,
  759. * so we may pass a useless variable to store the value.
  760. */
  761. reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
  762. reg = rt2x00mmio_register_read(rt2x00dev, CNT4);
  763. return 0;
  764. }
  765. static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
  766. {
  767. unsigned int i;
  768. u8 value;
  769. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  770. value = rt2400pci_bbp_read(rt2x00dev, 0);
  771. if ((value != 0xff) && (value != 0x00))
  772. return 0;
  773. udelay(REGISTER_BUSY_DELAY);
  774. }
  775. rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
  776. return -EACCES;
  777. }
  778. static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
  779. {
  780. unsigned int i;
  781. u16 eeprom;
  782. u8 reg_id;
  783. u8 value;
  784. if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
  785. return -EACCES;
  786. rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
  787. rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
  788. rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
  789. rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
  790. rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
  791. rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
  792. rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
  793. rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
  794. rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
  795. rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
  796. rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
  797. rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
  798. rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
  799. rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
  800. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  801. eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
  802. if (eeprom != 0xffff && eeprom != 0x0000) {
  803. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  804. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  805. rt2400pci_bbp_write(rt2x00dev, reg_id, value);
  806. }
  807. }
  808. return 0;
  809. }
  810. /*
  811. * Device state switch handlers.
  812. */
  813. static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  814. enum dev_state state)
  815. {
  816. int mask = (state == STATE_RADIO_IRQ_OFF);
  817. u32 reg;
  818. unsigned long flags;
  819. /*
  820. * When interrupts are being enabled, the interrupt registers
  821. * should clear the register to assure a clean state.
  822. */
  823. if (state == STATE_RADIO_IRQ_ON) {
  824. reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
  825. rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
  826. }
  827. /*
  828. * Only toggle the interrupts bits we are going to use.
  829. * Non-checked interrupt bits are disabled by default.
  830. */
  831. spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
  832. reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
  833. rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
  834. rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
  835. rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
  836. rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
  837. rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
  838. rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
  839. spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
  840. if (state == STATE_RADIO_IRQ_OFF) {
  841. /*
  842. * Ensure that all tasklets are finished before
  843. * disabling the interrupts.
  844. */
  845. tasklet_kill(&rt2x00dev->txstatus_tasklet);
  846. tasklet_kill(&rt2x00dev->rxdone_tasklet);
  847. tasklet_kill(&rt2x00dev->tbtt_tasklet);
  848. }
  849. }
  850. static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  851. {
  852. /*
  853. * Initialize all registers.
  854. */
  855. if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
  856. rt2400pci_init_registers(rt2x00dev) ||
  857. rt2400pci_init_bbp(rt2x00dev)))
  858. return -EIO;
  859. return 0;
  860. }
  861. static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  862. {
  863. /*
  864. * Disable power
  865. */
  866. rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
  867. }
  868. static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
  869. enum dev_state state)
  870. {
  871. u32 reg, reg2;
  872. unsigned int i;
  873. bool put_to_sleep;
  874. u8 bbp_state;
  875. u8 rf_state;
  876. put_to_sleep = (state != STATE_AWAKE);
  877. reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
  878. rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
  879. rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
  880. rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
  881. rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
  882. rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
  883. /*
  884. * Device is not guaranteed to be in the requested state yet.
  885. * We must wait until the register indicates that the
  886. * device has entered the correct state.
  887. */
  888. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  889. reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
  890. bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
  891. rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
  892. if (bbp_state == state && rf_state == state)
  893. return 0;
  894. rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
  895. msleep(10);
  896. }
  897. return -EBUSY;
  898. }
  899. static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  900. enum dev_state state)
  901. {
  902. int retval = 0;
  903. switch (state) {
  904. case STATE_RADIO_ON:
  905. retval = rt2400pci_enable_radio(rt2x00dev);
  906. break;
  907. case STATE_RADIO_OFF:
  908. rt2400pci_disable_radio(rt2x00dev);
  909. break;
  910. case STATE_RADIO_IRQ_ON:
  911. case STATE_RADIO_IRQ_OFF:
  912. rt2400pci_toggle_irq(rt2x00dev, state);
  913. break;
  914. case STATE_DEEP_SLEEP:
  915. case STATE_SLEEP:
  916. case STATE_STANDBY:
  917. case STATE_AWAKE:
  918. retval = rt2400pci_set_state(rt2x00dev, state);
  919. break;
  920. default:
  921. retval = -ENOTSUPP;
  922. break;
  923. }
  924. if (unlikely(retval))
  925. rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
  926. state, retval);
  927. return retval;
  928. }
  929. /*
  930. * TX descriptor initialization
  931. */
  932. static void rt2400pci_write_tx_desc(struct queue_entry *entry,
  933. struct txentry_desc *txdesc)
  934. {
  935. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  936. struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
  937. __le32 *txd = entry_priv->desc;
  938. u32 word;
  939. /*
  940. * Start writing the descriptor words.
  941. */
  942. word = rt2x00_desc_read(txd, 1);
  943. rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
  944. rt2x00_desc_write(txd, 1, word);
  945. word = rt2x00_desc_read(txd, 2);
  946. rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
  947. rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
  948. rt2x00_desc_write(txd, 2, word);
  949. word = rt2x00_desc_read(txd, 3);
  950. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
  951. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
  952. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
  953. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
  954. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
  955. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
  956. rt2x00_desc_write(txd, 3, word);
  957. word = rt2x00_desc_read(txd, 4);
  958. rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
  959. txdesc->u.plcp.length_low);
  960. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
  961. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
  962. rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
  963. txdesc->u.plcp.length_high);
  964. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
  965. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
  966. rt2x00_desc_write(txd, 4, word);
  967. /*
  968. * Writing TXD word 0 must the last to prevent a race condition with
  969. * the device, whereby the device may take hold of the TXD before we
  970. * finished updating it.
  971. */
  972. word = rt2x00_desc_read(txd, 0);
  973. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
  974. rt2x00_set_field32(&word, TXD_W0_VALID, 1);
  975. rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
  976. test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  977. rt2x00_set_field32(&word, TXD_W0_ACK,
  978. test_bit(ENTRY_TXD_ACK, &txdesc->flags));
  979. rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
  980. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
  981. rt2x00_set_field32(&word, TXD_W0_RTS,
  982. test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
  983. rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
  984. rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
  985. test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
  986. rt2x00_desc_write(txd, 0, word);
  987. /*
  988. * Register descriptor details in skb frame descriptor.
  989. */
  990. skbdesc->desc = txd;
  991. skbdesc->desc_len = TXD_DESC_SIZE;
  992. }
  993. /*
  994. * TX data initialization
  995. */
  996. static void rt2400pci_write_beacon(struct queue_entry *entry,
  997. struct txentry_desc *txdesc)
  998. {
  999. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  1000. u32 reg;
  1001. /*
  1002. * Disable beaconing while we are reloading the beacon data,
  1003. * otherwise we might be sending out invalid data.
  1004. */
  1005. reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
  1006. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
  1007. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  1008. if (rt2x00queue_map_txskb(entry)) {
  1009. rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
  1010. goto out;
  1011. }
  1012. /*
  1013. * Enable beaconing again.
  1014. */
  1015. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
  1016. /*
  1017. * Write the TX descriptor for the beacon.
  1018. */
  1019. rt2400pci_write_tx_desc(entry, txdesc);
  1020. /*
  1021. * Dump beacon to userspace through debugfs.
  1022. */
  1023. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
  1024. out:
  1025. /*
  1026. * Enable beaconing again.
  1027. */
  1028. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
  1029. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  1030. }
  1031. /*
  1032. * RX control handlers
  1033. */
  1034. static void rt2400pci_fill_rxdone(struct queue_entry *entry,
  1035. struct rxdone_entry_desc *rxdesc)
  1036. {
  1037. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  1038. struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
  1039. u32 word0;
  1040. u32 word2;
  1041. u32 word3;
  1042. u32 word4;
  1043. u64 tsf;
  1044. u32 rx_low;
  1045. u32 rx_high;
  1046. word0 = rt2x00_desc_read(entry_priv->desc, 0);
  1047. word2 = rt2x00_desc_read(entry_priv->desc, 2);
  1048. word3 = rt2x00_desc_read(entry_priv->desc, 3);
  1049. word4 = rt2x00_desc_read(entry_priv->desc, 4);
  1050. if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
  1051. rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
  1052. if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
  1053. rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
  1054. /*
  1055. * We only get the lower 32bits from the timestamp,
  1056. * to get the full 64bits we must complement it with
  1057. * the timestamp from get_tsf().
  1058. * Note that when a wraparound of the lower 32bits
  1059. * has occurred between the frame arrival and the get_tsf()
  1060. * call, we must decrease the higher 32bits with 1 to get
  1061. * to correct value.
  1062. */
  1063. tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
  1064. rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
  1065. rx_high = upper_32_bits(tsf);
  1066. if ((u32)tsf <= rx_low)
  1067. rx_high--;
  1068. /*
  1069. * Obtain the status about this packet.
  1070. * The signal is the PLCP value, and needs to be stripped
  1071. * of the preamble bit (0x08).
  1072. */
  1073. rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
  1074. rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
  1075. rxdesc->rssi = rt2x00_get_field32(word3, RXD_W3_RSSI) -
  1076. entry->queue->rt2x00dev->rssi_offset;
  1077. rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
  1078. rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
  1079. if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
  1080. rxdesc->dev_flags |= RXDONE_MY_BSS;
  1081. }
  1082. /*
  1083. * Interrupt functions.
  1084. */
  1085. static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
  1086. const enum data_queue_qid queue_idx)
  1087. {
  1088. struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
  1089. struct queue_entry_priv_mmio *entry_priv;
  1090. struct queue_entry *entry;
  1091. struct txdone_entry_desc txdesc;
  1092. u32 word;
  1093. while (!rt2x00queue_empty(queue)) {
  1094. entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
  1095. entry_priv = entry->priv_data;
  1096. word = rt2x00_desc_read(entry_priv->desc, 0);
  1097. if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1098. !rt2x00_get_field32(word, TXD_W0_VALID))
  1099. break;
  1100. /*
  1101. * Obtain the status about this packet.
  1102. */
  1103. txdesc.flags = 0;
  1104. switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
  1105. case 0: /* Success */
  1106. case 1: /* Success with retry */
  1107. __set_bit(TXDONE_SUCCESS, &txdesc.flags);
  1108. break;
  1109. case 2: /* Failure, excessive retries */
  1110. __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
  1111. fallthrough; /* this is a failed frame! */
  1112. default: /* Failure */
  1113. __set_bit(TXDONE_FAILURE, &txdesc.flags);
  1114. }
  1115. txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
  1116. rt2x00lib_txdone(entry, &txdesc);
  1117. }
  1118. }
  1119. static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
  1120. struct rt2x00_field32 irq_field)
  1121. {
  1122. u32 reg;
  1123. /*
  1124. * Enable a single interrupt. The interrupt mask register
  1125. * access needs locking.
  1126. */
  1127. spin_lock_irq(&rt2x00dev->irqmask_lock);
  1128. reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
  1129. rt2x00_set_field32(&reg, irq_field, 0);
  1130. rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
  1131. spin_unlock_irq(&rt2x00dev->irqmask_lock);
  1132. }
  1133. static void rt2400pci_txstatus_tasklet(struct tasklet_struct *t)
  1134. {
  1135. struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
  1136. txstatus_tasklet);
  1137. u32 reg;
  1138. /*
  1139. * Handle all tx queues.
  1140. */
  1141. rt2400pci_txdone(rt2x00dev, QID_ATIM);
  1142. rt2400pci_txdone(rt2x00dev, QID_AC_VO);
  1143. rt2400pci_txdone(rt2x00dev, QID_AC_VI);
  1144. /*
  1145. * Enable all TXDONE interrupts again.
  1146. */
  1147. if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
  1148. spin_lock_irq(&rt2x00dev->irqmask_lock);
  1149. reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
  1150. rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
  1151. rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
  1152. rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
  1153. rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
  1154. spin_unlock_irq(&rt2x00dev->irqmask_lock);
  1155. }
  1156. }
  1157. static void rt2400pci_tbtt_tasklet(struct tasklet_struct *t)
  1158. {
  1159. struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);
  1160. rt2x00lib_beacondone(rt2x00dev);
  1161. if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  1162. rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
  1163. }
  1164. static void rt2400pci_rxdone_tasklet(struct tasklet_struct *t)
  1165. {
  1166. struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
  1167. rxdone_tasklet);
  1168. if (rt2x00mmio_rxdone(rt2x00dev))
  1169. tasklet_schedule(&rt2x00dev->rxdone_tasklet);
  1170. else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  1171. rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
  1172. }
  1173. static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
  1174. {
  1175. struct rt2x00_dev *rt2x00dev = dev_instance;
  1176. u32 reg, mask;
  1177. /*
  1178. * Get the interrupt sources & saved to local variable.
  1179. * Write register value back to clear pending interrupts.
  1180. */
  1181. reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
  1182. rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
  1183. if (!reg)
  1184. return IRQ_NONE;
  1185. if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  1186. return IRQ_HANDLED;
  1187. mask = reg;
  1188. /*
  1189. * Schedule tasklets for interrupt handling.
  1190. */
  1191. if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
  1192. tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
  1193. if (rt2x00_get_field32(reg, CSR7_RXDONE))
  1194. tasklet_schedule(&rt2x00dev->rxdone_tasklet);
  1195. if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
  1196. rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
  1197. rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
  1198. tasklet_schedule(&rt2x00dev->txstatus_tasklet);
  1199. /*
  1200. * Mask out all txdone interrupts.
  1201. */
  1202. rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
  1203. rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
  1204. rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
  1205. }
  1206. /*
  1207. * Disable all interrupts for which a tasklet was scheduled right now,
  1208. * the tasklet will reenable the appropriate interrupts.
  1209. */
  1210. spin_lock(&rt2x00dev->irqmask_lock);
  1211. reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
  1212. reg |= mask;
  1213. rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
  1214. spin_unlock(&rt2x00dev->irqmask_lock);
  1215. return IRQ_HANDLED;
  1216. }
  1217. /*
  1218. * Device probe functions.
  1219. */
  1220. static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1221. {
  1222. struct eeprom_93cx6 eeprom;
  1223. u32 reg;
  1224. u16 word;
  1225. u8 *mac;
  1226. reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
  1227. eeprom.data = rt2x00dev;
  1228. eeprom.register_read = rt2400pci_eepromregister_read;
  1229. eeprom.register_write = rt2400pci_eepromregister_write;
  1230. eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
  1231. PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
  1232. eeprom.reg_data_in = 0;
  1233. eeprom.reg_data_out = 0;
  1234. eeprom.reg_data_clock = 0;
  1235. eeprom.reg_chip_select = 0;
  1236. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  1237. EEPROM_SIZE / sizeof(u16));
  1238. /*
  1239. * Start validation of the data that has been read.
  1240. */
  1241. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1242. rt2x00lib_set_mac_address(rt2x00dev, mac);
  1243. word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
  1244. if (word == 0xffff) {
  1245. rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
  1246. return -EINVAL;
  1247. }
  1248. return 0;
  1249. }
  1250. static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1251. {
  1252. u32 reg;
  1253. u16 value;
  1254. u16 eeprom;
  1255. /*
  1256. * Read EEPROM word for configuration.
  1257. */
  1258. eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
  1259. /*
  1260. * Identify RF chipset.
  1261. */
  1262. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1263. reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
  1264. rt2x00_set_chip(rt2x00dev, RT2460, value,
  1265. rt2x00_get_field32(reg, CSR0_REVISION));
  1266. if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
  1267. rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
  1268. return -ENODEV;
  1269. }
  1270. /*
  1271. * Identify default antenna configuration.
  1272. */
  1273. rt2x00dev->default_ant.tx =
  1274. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
  1275. rt2x00dev->default_ant.rx =
  1276. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
  1277. /*
  1278. * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
  1279. * I am not 100% sure about this, but the legacy drivers do not
  1280. * indicate antenna swapping in software is required when
  1281. * diversity is enabled.
  1282. */
  1283. if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
  1284. rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
  1285. if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
  1286. rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
  1287. /*
  1288. * Store led mode, for correct led behaviour.
  1289. */
  1290. #ifdef CONFIG_RT2X00_LIB_LEDS
  1291. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
  1292. rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
  1293. if (value == LED_MODE_TXRX_ACTIVITY ||
  1294. value == LED_MODE_DEFAULT ||
  1295. value == LED_MODE_ASUS)
  1296. rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
  1297. LED_TYPE_ACTIVITY);
  1298. #endif /* CONFIG_RT2X00_LIB_LEDS */
  1299. /*
  1300. * Detect if this device has an hardware controlled radio.
  1301. */
  1302. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
  1303. __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
  1304. /*
  1305. * Check if the BBP tuning should be enabled.
  1306. */
  1307. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
  1308. __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
  1309. return 0;
  1310. }
  1311. /*
  1312. * RF value list for RF2420 & RF2421
  1313. * Supports: 2.4 GHz
  1314. */
  1315. static const struct rf_channel rf_vals_b[] = {
  1316. { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
  1317. { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
  1318. { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
  1319. { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
  1320. { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
  1321. { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
  1322. { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
  1323. { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
  1324. { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
  1325. { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
  1326. { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
  1327. { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
  1328. { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
  1329. { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
  1330. };
  1331. static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1332. {
  1333. struct hw_mode_spec *spec = &rt2x00dev->spec;
  1334. struct channel_info *info;
  1335. u8 *tx_power;
  1336. unsigned int i;
  1337. /*
  1338. * Initialize all hw fields.
  1339. */
  1340. ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
  1341. ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
  1342. ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
  1343. ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
  1344. SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
  1345. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  1346. rt2x00_eeprom_addr(rt2x00dev,
  1347. EEPROM_MAC_ADDR_0));
  1348. /*
  1349. * Initialize hw_mode information.
  1350. */
  1351. spec->supported_bands = SUPPORT_BAND_2GHZ;
  1352. spec->supported_rates = SUPPORT_RATE_CCK;
  1353. spec->num_channels = ARRAY_SIZE(rf_vals_b);
  1354. spec->channels = rf_vals_b;
  1355. /*
  1356. * Create channel information array
  1357. */
  1358. info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
  1359. if (!info)
  1360. return -ENOMEM;
  1361. spec->channels_info = info;
  1362. tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
  1363. for (i = 0; i < 14; i++) {
  1364. info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
  1365. info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
  1366. }
  1367. return 0;
  1368. }
  1369. static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
  1370. {
  1371. int retval;
  1372. u32 reg;
  1373. /*
  1374. * Allocate eeprom data.
  1375. */
  1376. retval = rt2400pci_validate_eeprom(rt2x00dev);
  1377. if (retval)
  1378. return retval;
  1379. retval = rt2400pci_init_eeprom(rt2x00dev);
  1380. if (retval)
  1381. return retval;
  1382. /*
  1383. * Enable rfkill polling by setting GPIO direction of the
  1384. * rfkill switch GPIO pin correctly.
  1385. */
  1386. reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
  1387. rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
  1388. rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
  1389. /*
  1390. * Initialize hw specifications.
  1391. */
  1392. retval = rt2400pci_probe_hw_mode(rt2x00dev);
  1393. if (retval)
  1394. return retval;
  1395. /*
  1396. * This device requires the atim queue and DMA-mapped skbs.
  1397. */
  1398. __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
  1399. __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
  1400. __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
  1401. /*
  1402. * Set the rssi offset.
  1403. */
  1404. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  1405. return 0;
  1406. }
  1407. /*
  1408. * IEEE80211 stack callback functions.
  1409. */
  1410. static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
  1411. struct ieee80211_vif *vif,
  1412. unsigned int link_id, u16 queue,
  1413. const struct ieee80211_tx_queue_params *params)
  1414. {
  1415. struct rt2x00_dev *rt2x00dev = hw->priv;
  1416. /*
  1417. * We don't support variating cw_min and cw_max variables
  1418. * per queue. So by default we only configure the TX queue,
  1419. * and ignore all other configurations.
  1420. */
  1421. if (queue != 0)
  1422. return -EINVAL;
  1423. if (rt2x00mac_conf_tx(hw, vif, link_id, queue, params))
  1424. return -EINVAL;
  1425. /*
  1426. * Write configuration to register.
  1427. */
  1428. rt2400pci_config_cw(rt2x00dev,
  1429. rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
  1430. return 0;
  1431. }
  1432. static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
  1433. struct ieee80211_vif *vif)
  1434. {
  1435. struct rt2x00_dev *rt2x00dev = hw->priv;
  1436. u64 tsf;
  1437. u32 reg;
  1438. reg = rt2x00mmio_register_read(rt2x00dev, CSR17);
  1439. tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
  1440. reg = rt2x00mmio_register_read(rt2x00dev, CSR16);
  1441. tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
  1442. return tsf;
  1443. }
  1444. static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
  1445. {
  1446. struct rt2x00_dev *rt2x00dev = hw->priv;
  1447. u32 reg;
  1448. reg = rt2x00mmio_register_read(rt2x00dev, CSR15);
  1449. return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
  1450. }
  1451. static const struct ieee80211_ops rt2400pci_mac80211_ops = {
  1452. .tx = rt2x00mac_tx,
  1453. .start = rt2x00mac_start,
  1454. .stop = rt2x00mac_stop,
  1455. .add_interface = rt2x00mac_add_interface,
  1456. .remove_interface = rt2x00mac_remove_interface,
  1457. .config = rt2x00mac_config,
  1458. .configure_filter = rt2x00mac_configure_filter,
  1459. .sw_scan_start = rt2x00mac_sw_scan_start,
  1460. .sw_scan_complete = rt2x00mac_sw_scan_complete,
  1461. .get_stats = rt2x00mac_get_stats,
  1462. .bss_info_changed = rt2x00mac_bss_info_changed,
  1463. .conf_tx = rt2400pci_conf_tx,
  1464. .get_tsf = rt2400pci_get_tsf,
  1465. .tx_last_beacon = rt2400pci_tx_last_beacon,
  1466. .rfkill_poll = rt2x00mac_rfkill_poll,
  1467. .flush = rt2x00mac_flush,
  1468. .set_antenna = rt2x00mac_set_antenna,
  1469. .get_antenna = rt2x00mac_get_antenna,
  1470. .get_ringparam = rt2x00mac_get_ringparam,
  1471. .tx_frames_pending = rt2x00mac_tx_frames_pending,
  1472. };
  1473. static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
  1474. .irq_handler = rt2400pci_interrupt,
  1475. .txstatus_tasklet = rt2400pci_txstatus_tasklet,
  1476. .tbtt_tasklet = rt2400pci_tbtt_tasklet,
  1477. .rxdone_tasklet = rt2400pci_rxdone_tasklet,
  1478. .probe_hw = rt2400pci_probe_hw,
  1479. .initialize = rt2x00mmio_initialize,
  1480. .uninitialize = rt2x00mmio_uninitialize,
  1481. .get_entry_state = rt2400pci_get_entry_state,
  1482. .clear_entry = rt2400pci_clear_entry,
  1483. .set_device_state = rt2400pci_set_device_state,
  1484. .rfkill_poll = rt2400pci_rfkill_poll,
  1485. .link_stats = rt2400pci_link_stats,
  1486. .reset_tuner = rt2400pci_reset_tuner,
  1487. .link_tuner = rt2400pci_link_tuner,
  1488. .start_queue = rt2400pci_start_queue,
  1489. .kick_queue = rt2400pci_kick_queue,
  1490. .stop_queue = rt2400pci_stop_queue,
  1491. .flush_queue = rt2x00mmio_flush_queue,
  1492. .write_tx_desc = rt2400pci_write_tx_desc,
  1493. .write_beacon = rt2400pci_write_beacon,
  1494. .fill_rxdone = rt2400pci_fill_rxdone,
  1495. .config_filter = rt2400pci_config_filter,
  1496. .config_intf = rt2400pci_config_intf,
  1497. .config_erp = rt2400pci_config_erp,
  1498. .config_ant = rt2400pci_config_ant,
  1499. .config = rt2400pci_config,
  1500. };
  1501. static void rt2400pci_queue_init(struct data_queue *queue)
  1502. {
  1503. switch (queue->qid) {
  1504. case QID_RX:
  1505. queue->limit = 24;
  1506. queue->data_size = DATA_FRAME_SIZE;
  1507. queue->desc_size = RXD_DESC_SIZE;
  1508. queue->priv_size = sizeof(struct queue_entry_priv_mmio);
  1509. break;
  1510. case QID_AC_VO:
  1511. case QID_AC_VI:
  1512. case QID_AC_BE:
  1513. case QID_AC_BK:
  1514. queue->limit = 24;
  1515. queue->data_size = DATA_FRAME_SIZE;
  1516. queue->desc_size = TXD_DESC_SIZE;
  1517. queue->priv_size = sizeof(struct queue_entry_priv_mmio);
  1518. break;
  1519. case QID_BEACON:
  1520. queue->limit = 1;
  1521. queue->data_size = MGMT_FRAME_SIZE;
  1522. queue->desc_size = TXD_DESC_SIZE;
  1523. queue->priv_size = sizeof(struct queue_entry_priv_mmio);
  1524. break;
  1525. case QID_ATIM:
  1526. queue->limit = 8;
  1527. queue->data_size = DATA_FRAME_SIZE;
  1528. queue->desc_size = TXD_DESC_SIZE;
  1529. queue->priv_size = sizeof(struct queue_entry_priv_mmio);
  1530. break;
  1531. default:
  1532. BUG();
  1533. break;
  1534. }
  1535. }
  1536. static const struct rt2x00_ops rt2400pci_ops = {
  1537. .name = KBUILD_MODNAME,
  1538. .max_ap_intf = 1,
  1539. .eeprom_size = EEPROM_SIZE,
  1540. .rf_size = RF_SIZE,
  1541. .tx_queues = NUM_TX_QUEUES,
  1542. .queue_init = rt2400pci_queue_init,
  1543. .lib = &rt2400pci_rt2x00_ops,
  1544. .hw = &rt2400pci_mac80211_ops,
  1545. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  1546. .debugfs = &rt2400pci_rt2x00debug,
  1547. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  1548. };
  1549. /*
  1550. * RT2400pci module information.
  1551. */
  1552. static const struct pci_device_id rt2400pci_device_table[] = {
  1553. { PCI_DEVICE(0x1814, 0x0101) },
  1554. { 0, }
  1555. };
  1556. MODULE_AUTHOR(DRV_PROJECT);
  1557. MODULE_VERSION(DRV_VERSION);
  1558. MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
  1559. MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
  1560. MODULE_LICENSE("GPL");
  1561. static int rt2400pci_probe(struct pci_dev *pci_dev,
  1562. const struct pci_device_id *id)
  1563. {
  1564. return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
  1565. }
  1566. static struct pci_driver rt2400pci_driver = {
  1567. .name = KBUILD_MODNAME,
  1568. .id_table = rt2400pci_device_table,
  1569. .probe = rt2400pci_probe,
  1570. .remove = rt2x00pci_remove,
  1571. .driver.pm = &rt2x00pci_pm_ops,
  1572. };
  1573. module_pci_driver(rt2400pci_driver);