pio.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. Broadcom B43 wireless driver
  4. PIO data transfer
  5. Copyright (c) 2005-2008 Michael Buesch <[email protected]>
  6. */
  7. #include "b43.h"
  8. #include "pio.h"
  9. #include "dma.h"
  10. #include "main.h"
  11. #include "xmit.h"
  12. #include <linux/delay.h>
  13. #include <linux/sched.h>
  14. #include <linux/slab.h>
  15. static u16 generate_cookie(struct b43_pio_txqueue *q,
  16. struct b43_pio_txpacket *pack)
  17. {
  18. u16 cookie;
  19. /* Use the upper 4 bits of the cookie as
  20. * PIO controller ID and store the packet index number
  21. * in the lower 12 bits.
  22. * Note that the cookie must never be 0, as this
  23. * is a special value used in RX path.
  24. * It can also not be 0xFFFF because that is special
  25. * for multicast frames.
  26. */
  27. cookie = (((u16)q->index + 1) << 12);
  28. cookie |= pack->index;
  29. return cookie;
  30. }
  31. static
  32. struct b43_pio_txqueue *parse_cookie(struct b43_wldev *dev,
  33. u16 cookie,
  34. struct b43_pio_txpacket **pack)
  35. {
  36. struct b43_pio *pio = &dev->pio;
  37. struct b43_pio_txqueue *q = NULL;
  38. unsigned int pack_index;
  39. switch (cookie & 0xF000) {
  40. case 0x1000:
  41. q = pio->tx_queue_AC_BK;
  42. break;
  43. case 0x2000:
  44. q = pio->tx_queue_AC_BE;
  45. break;
  46. case 0x3000:
  47. q = pio->tx_queue_AC_VI;
  48. break;
  49. case 0x4000:
  50. q = pio->tx_queue_AC_VO;
  51. break;
  52. case 0x5000:
  53. q = pio->tx_queue_mcast;
  54. break;
  55. }
  56. if (B43_WARN_ON(!q))
  57. return NULL;
  58. pack_index = (cookie & 0x0FFF);
  59. if (B43_WARN_ON(pack_index >= ARRAY_SIZE(q->packets)))
  60. return NULL;
  61. *pack = &q->packets[pack_index];
  62. return q;
  63. }
  64. static u16 index_to_pioqueue_base(struct b43_wldev *dev,
  65. unsigned int index)
  66. {
  67. static const u16 bases[] = {
  68. B43_MMIO_PIO_BASE0,
  69. B43_MMIO_PIO_BASE1,
  70. B43_MMIO_PIO_BASE2,
  71. B43_MMIO_PIO_BASE3,
  72. B43_MMIO_PIO_BASE4,
  73. B43_MMIO_PIO_BASE5,
  74. B43_MMIO_PIO_BASE6,
  75. B43_MMIO_PIO_BASE7,
  76. };
  77. static const u16 bases_rev11[] = {
  78. B43_MMIO_PIO11_BASE0,
  79. B43_MMIO_PIO11_BASE1,
  80. B43_MMIO_PIO11_BASE2,
  81. B43_MMIO_PIO11_BASE3,
  82. B43_MMIO_PIO11_BASE4,
  83. B43_MMIO_PIO11_BASE5,
  84. };
  85. if (dev->dev->core_rev >= 11) {
  86. B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11));
  87. return bases_rev11[index];
  88. }
  89. B43_WARN_ON(index >= ARRAY_SIZE(bases));
  90. return bases[index];
  91. }
  92. static u16 pio_txqueue_offset(struct b43_wldev *dev)
  93. {
  94. if (dev->dev->core_rev >= 11)
  95. return 0x18;
  96. return 0;
  97. }
  98. static u16 pio_rxqueue_offset(struct b43_wldev *dev)
  99. {
  100. if (dev->dev->core_rev >= 11)
  101. return 0x38;
  102. return 8;
  103. }
  104. static struct b43_pio_txqueue *b43_setup_pioqueue_tx(struct b43_wldev *dev,
  105. unsigned int index)
  106. {
  107. struct b43_pio_txqueue *q;
  108. struct b43_pio_txpacket *p;
  109. unsigned int i;
  110. q = kzalloc(sizeof(*q), GFP_KERNEL);
  111. if (!q)
  112. return NULL;
  113. q->dev = dev;
  114. q->rev = dev->dev->core_rev;
  115. q->mmio_base = index_to_pioqueue_base(dev, index) +
  116. pio_txqueue_offset(dev);
  117. q->index = index;
  118. q->free_packet_slots = B43_PIO_MAX_NR_TXPACKETS;
  119. if (q->rev >= 8) {
  120. q->buffer_size = 1920; //FIXME this constant is wrong.
  121. } else {
  122. q->buffer_size = b43_piotx_read16(q, B43_PIO_TXQBUFSIZE);
  123. q->buffer_size -= 80;
  124. }
  125. INIT_LIST_HEAD(&q->packets_list);
  126. for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
  127. p = &(q->packets[i]);
  128. INIT_LIST_HEAD(&p->list);
  129. p->index = i;
  130. p->queue = q;
  131. list_add(&p->list, &q->packets_list);
  132. }
  133. return q;
  134. }
  135. static struct b43_pio_rxqueue *b43_setup_pioqueue_rx(struct b43_wldev *dev,
  136. unsigned int index)
  137. {
  138. struct b43_pio_rxqueue *q;
  139. q = kzalloc(sizeof(*q), GFP_KERNEL);
  140. if (!q)
  141. return NULL;
  142. q->dev = dev;
  143. q->rev = dev->dev->core_rev;
  144. q->mmio_base = index_to_pioqueue_base(dev, index) +
  145. pio_rxqueue_offset(dev);
  146. /* Enable Direct FIFO RX (PIO) on the engine. */
  147. b43_dma_direct_fifo_rx(dev, index, 1);
  148. return q;
  149. }
  150. static void b43_pio_cancel_tx_packets(struct b43_pio_txqueue *q)
  151. {
  152. struct b43_pio_txpacket *pack;
  153. unsigned int i;
  154. for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
  155. pack = &(q->packets[i]);
  156. if (pack->skb) {
  157. ieee80211_free_txskb(q->dev->wl->hw, pack->skb);
  158. pack->skb = NULL;
  159. }
  160. }
  161. }
  162. static void b43_destroy_pioqueue_tx(struct b43_pio_txqueue *q,
  163. const char *name)
  164. {
  165. if (!q)
  166. return;
  167. b43_pio_cancel_tx_packets(q);
  168. kfree(q);
  169. }
  170. static void b43_destroy_pioqueue_rx(struct b43_pio_rxqueue *q,
  171. const char *name)
  172. {
  173. if (!q)
  174. return;
  175. kfree(q);
  176. }
  177. #define destroy_queue_tx(pio, queue) do { \
  178. b43_destroy_pioqueue_tx((pio)->queue, __stringify(queue)); \
  179. (pio)->queue = NULL; \
  180. } while (0)
  181. #define destroy_queue_rx(pio, queue) do { \
  182. b43_destroy_pioqueue_rx((pio)->queue, __stringify(queue)); \
  183. (pio)->queue = NULL; \
  184. } while (0)
  185. void b43_pio_free(struct b43_wldev *dev)
  186. {
  187. struct b43_pio *pio;
  188. if (!b43_using_pio_transfers(dev))
  189. return;
  190. pio = &dev->pio;
  191. destroy_queue_rx(pio, rx_queue);
  192. destroy_queue_tx(pio, tx_queue_mcast);
  193. destroy_queue_tx(pio, tx_queue_AC_VO);
  194. destroy_queue_tx(pio, tx_queue_AC_VI);
  195. destroy_queue_tx(pio, tx_queue_AC_BE);
  196. destroy_queue_tx(pio, tx_queue_AC_BK);
  197. }
  198. int b43_pio_init(struct b43_wldev *dev)
  199. {
  200. struct b43_pio *pio = &dev->pio;
  201. int err = -ENOMEM;
  202. b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
  203. & ~B43_MACCTL_BE);
  204. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RXPADOFF, 0);
  205. pio->tx_queue_AC_BK = b43_setup_pioqueue_tx(dev, 0);
  206. if (!pio->tx_queue_AC_BK)
  207. goto out;
  208. pio->tx_queue_AC_BE = b43_setup_pioqueue_tx(dev, 1);
  209. if (!pio->tx_queue_AC_BE)
  210. goto err_destroy_bk;
  211. pio->tx_queue_AC_VI = b43_setup_pioqueue_tx(dev, 2);
  212. if (!pio->tx_queue_AC_VI)
  213. goto err_destroy_be;
  214. pio->tx_queue_AC_VO = b43_setup_pioqueue_tx(dev, 3);
  215. if (!pio->tx_queue_AC_VO)
  216. goto err_destroy_vi;
  217. pio->tx_queue_mcast = b43_setup_pioqueue_tx(dev, 4);
  218. if (!pio->tx_queue_mcast)
  219. goto err_destroy_vo;
  220. pio->rx_queue = b43_setup_pioqueue_rx(dev, 0);
  221. if (!pio->rx_queue)
  222. goto err_destroy_mcast;
  223. b43dbg(dev->wl, "PIO initialized\n");
  224. err = 0;
  225. out:
  226. return err;
  227. err_destroy_mcast:
  228. destroy_queue_tx(pio, tx_queue_mcast);
  229. err_destroy_vo:
  230. destroy_queue_tx(pio, tx_queue_AC_VO);
  231. err_destroy_vi:
  232. destroy_queue_tx(pio, tx_queue_AC_VI);
  233. err_destroy_be:
  234. destroy_queue_tx(pio, tx_queue_AC_BE);
  235. err_destroy_bk:
  236. destroy_queue_tx(pio, tx_queue_AC_BK);
  237. return err;
  238. }
  239. /* Static mapping of mac80211's queues (priorities) to b43 PIO queues. */
  240. static struct b43_pio_txqueue *select_queue_by_priority(struct b43_wldev *dev,
  241. u8 queue_prio)
  242. {
  243. struct b43_pio_txqueue *q;
  244. if (dev->qos_enabled) {
  245. /* 0 = highest priority */
  246. switch (queue_prio) {
  247. default:
  248. B43_WARN_ON(1);
  249. fallthrough;
  250. case 0:
  251. q = dev->pio.tx_queue_AC_VO;
  252. break;
  253. case 1:
  254. q = dev->pio.tx_queue_AC_VI;
  255. break;
  256. case 2:
  257. q = dev->pio.tx_queue_AC_BE;
  258. break;
  259. case 3:
  260. q = dev->pio.tx_queue_AC_BK;
  261. break;
  262. }
  263. } else
  264. q = dev->pio.tx_queue_AC_BE;
  265. return q;
  266. }
  267. static u16 tx_write_2byte_queue(struct b43_pio_txqueue *q,
  268. u16 ctl,
  269. const void *_data,
  270. unsigned int data_len)
  271. {
  272. struct b43_wldev *dev = q->dev;
  273. struct b43_wl *wl = dev->wl;
  274. const u8 *data = _data;
  275. ctl |= B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI;
  276. b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
  277. b43_block_write(dev, data, (data_len & ~1),
  278. q->mmio_base + B43_PIO_TXDATA,
  279. sizeof(u16));
  280. if (data_len & 1) {
  281. u8 *tail = wl->pio_tailspace;
  282. BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 2);
  283. /* Write the last byte. */
  284. ctl &= ~B43_PIO_TXCTL_WRITEHI;
  285. b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
  286. tail[0] = data[data_len - 1];
  287. tail[1] = 0;
  288. b43_block_write(dev, tail, 2,
  289. q->mmio_base + B43_PIO_TXDATA,
  290. sizeof(u16));
  291. }
  292. return ctl;
  293. }
  294. static void pio_tx_frame_2byte_queue(struct b43_pio_txpacket *pack,
  295. const u8 *hdr, unsigned int hdrlen)
  296. {
  297. struct b43_pio_txqueue *q = pack->queue;
  298. const char *frame = pack->skb->data;
  299. unsigned int frame_len = pack->skb->len;
  300. u16 ctl;
  301. ctl = b43_piotx_read16(q, B43_PIO_TXCTL);
  302. ctl |= B43_PIO_TXCTL_FREADY;
  303. ctl &= ~B43_PIO_TXCTL_EOF;
  304. /* Transfer the header data. */
  305. ctl = tx_write_2byte_queue(q, ctl, hdr, hdrlen);
  306. /* Transfer the frame data. */
  307. ctl = tx_write_2byte_queue(q, ctl, frame, frame_len);
  308. ctl |= B43_PIO_TXCTL_EOF;
  309. b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
  310. }
  311. static u32 tx_write_4byte_queue(struct b43_pio_txqueue *q,
  312. u32 ctl,
  313. const void *_data,
  314. unsigned int data_len)
  315. {
  316. struct b43_wldev *dev = q->dev;
  317. struct b43_wl *wl = dev->wl;
  318. const u8 *data = _data;
  319. ctl |= B43_PIO8_TXCTL_0_7 | B43_PIO8_TXCTL_8_15 |
  320. B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_24_31;
  321. b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
  322. b43_block_write(dev, data, (data_len & ~3),
  323. q->mmio_base + B43_PIO8_TXDATA,
  324. sizeof(u32));
  325. if (data_len & 3) {
  326. u8 *tail = wl->pio_tailspace;
  327. BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 4);
  328. memset(tail, 0, 4);
  329. /* Write the last few bytes. */
  330. ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 |
  331. B43_PIO8_TXCTL_24_31);
  332. switch (data_len & 3) {
  333. case 3:
  334. ctl |= B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_8_15;
  335. tail[0] = data[data_len - 3];
  336. tail[1] = data[data_len - 2];
  337. tail[2] = data[data_len - 1];
  338. break;
  339. case 2:
  340. ctl |= B43_PIO8_TXCTL_8_15;
  341. tail[0] = data[data_len - 2];
  342. tail[1] = data[data_len - 1];
  343. break;
  344. case 1:
  345. tail[0] = data[data_len - 1];
  346. break;
  347. }
  348. b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
  349. b43_block_write(dev, tail, 4,
  350. q->mmio_base + B43_PIO8_TXDATA,
  351. sizeof(u32));
  352. }
  353. return ctl;
  354. }
  355. static void pio_tx_frame_4byte_queue(struct b43_pio_txpacket *pack,
  356. const u8 *hdr, unsigned int hdrlen)
  357. {
  358. struct b43_pio_txqueue *q = pack->queue;
  359. const char *frame = pack->skb->data;
  360. unsigned int frame_len = pack->skb->len;
  361. u32 ctl;
  362. ctl = b43_piotx_read32(q, B43_PIO8_TXCTL);
  363. ctl |= B43_PIO8_TXCTL_FREADY;
  364. ctl &= ~B43_PIO8_TXCTL_EOF;
  365. /* Transfer the header data. */
  366. ctl = tx_write_4byte_queue(q, ctl, hdr, hdrlen);
  367. /* Transfer the frame data. */
  368. ctl = tx_write_4byte_queue(q, ctl, frame, frame_len);
  369. ctl |= B43_PIO8_TXCTL_EOF;
  370. b43_piotx_write32(q, B43_PIO_TXCTL, ctl);
  371. }
  372. static int pio_tx_frame(struct b43_pio_txqueue *q,
  373. struct sk_buff *skb)
  374. {
  375. struct b43_wldev *dev = q->dev;
  376. struct b43_wl *wl = dev->wl;
  377. struct b43_pio_txpacket *pack;
  378. u16 cookie;
  379. int err;
  380. unsigned int hdrlen;
  381. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  382. struct b43_txhdr *txhdr = (struct b43_txhdr *)wl->pio_scratchspace;
  383. B43_WARN_ON(list_empty(&q->packets_list));
  384. pack = list_entry(q->packets_list.next,
  385. struct b43_pio_txpacket, list);
  386. cookie = generate_cookie(q, pack);
  387. hdrlen = b43_txhdr_size(dev);
  388. BUILD_BUG_ON(sizeof(wl->pio_scratchspace) < sizeof(struct b43_txhdr));
  389. B43_WARN_ON(sizeof(wl->pio_scratchspace) < hdrlen);
  390. err = b43_generate_txhdr(dev, (u8 *)txhdr, skb,
  391. info, cookie);
  392. if (err)
  393. return err;
  394. if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
  395. /* Tell the firmware about the cookie of the last
  396. * mcast frame, so it can clear the more-data bit in it. */
  397. b43_shm_write16(dev, B43_SHM_SHARED,
  398. B43_SHM_SH_MCASTCOOKIE, cookie);
  399. }
  400. pack->skb = skb;
  401. if (q->rev >= 8)
  402. pio_tx_frame_4byte_queue(pack, (const u8 *)txhdr, hdrlen);
  403. else
  404. pio_tx_frame_2byte_queue(pack, (const u8 *)txhdr, hdrlen);
  405. /* Remove it from the list of available packet slots.
  406. * It will be put back when we receive the status report. */
  407. list_del(&pack->list);
  408. /* Update the queue statistics. */
  409. q->buffer_used += roundup(skb->len + hdrlen, 4);
  410. q->free_packet_slots -= 1;
  411. return 0;
  412. }
  413. int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb)
  414. {
  415. struct b43_pio_txqueue *q;
  416. struct ieee80211_hdr *hdr;
  417. unsigned int hdrlen, total_len;
  418. int err = 0;
  419. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  420. hdr = (struct ieee80211_hdr *)skb->data;
  421. if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
  422. /* The multicast queue will be sent after the DTIM. */
  423. q = dev->pio.tx_queue_mcast;
  424. /* Set the frame More-Data bit. Ucode will clear it
  425. * for us on the last frame. */
  426. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
  427. } else {
  428. /* Decide by priority where to put this frame. */
  429. q = select_queue_by_priority(dev, skb_get_queue_mapping(skb));
  430. }
  431. hdrlen = b43_txhdr_size(dev);
  432. total_len = roundup(skb->len + hdrlen, 4);
  433. if (unlikely(total_len > q->buffer_size)) {
  434. err = -ENOBUFS;
  435. b43dbg(dev->wl, "PIO: TX packet longer than queue.\n");
  436. goto out;
  437. }
  438. if (unlikely(q->free_packet_slots == 0)) {
  439. err = -ENOBUFS;
  440. b43warn(dev->wl, "PIO: TX packet overflow.\n");
  441. goto out;
  442. }
  443. B43_WARN_ON(q->buffer_used > q->buffer_size);
  444. if (total_len > (q->buffer_size - q->buffer_used)) {
  445. /* Not enough memory on the queue. */
  446. err = -EBUSY;
  447. ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
  448. q->stopped = true;
  449. goto out;
  450. }
  451. /* Assign the queue number to the ring (if not already done before)
  452. * so TX status handling can use it. The mac80211-queue to b43-queue
  453. * mapping is static, so we don't need to store it per frame. */
  454. q->queue_prio = skb_get_queue_mapping(skb);
  455. err = pio_tx_frame(q, skb);
  456. if (unlikely(err == -ENOKEY)) {
  457. /* Drop this packet, as we don't have the encryption key
  458. * anymore and must not transmit it unencrypted. */
  459. ieee80211_free_txskb(dev->wl->hw, skb);
  460. err = 0;
  461. goto out;
  462. }
  463. if (unlikely(err)) {
  464. b43err(dev->wl, "PIO transmission failure\n");
  465. goto out;
  466. }
  467. B43_WARN_ON(q->buffer_used > q->buffer_size);
  468. if (((q->buffer_size - q->buffer_used) < roundup(2 + 2 + 6, 4)) ||
  469. (q->free_packet_slots == 0)) {
  470. /* The queue is full. */
  471. ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
  472. q->stopped = true;
  473. }
  474. out:
  475. return err;
  476. }
  477. void b43_pio_handle_txstatus(struct b43_wldev *dev,
  478. const struct b43_txstatus *status)
  479. {
  480. struct b43_pio_txqueue *q;
  481. struct b43_pio_txpacket *pack = NULL;
  482. unsigned int total_len;
  483. struct ieee80211_tx_info *info;
  484. q = parse_cookie(dev, status->cookie, &pack);
  485. if (unlikely(!q))
  486. return;
  487. B43_WARN_ON(!pack);
  488. info = IEEE80211_SKB_CB(pack->skb);
  489. b43_fill_txstatus_report(dev, info, status);
  490. total_len = pack->skb->len + b43_txhdr_size(dev);
  491. total_len = roundup(total_len, 4);
  492. q->buffer_used -= total_len;
  493. q->free_packet_slots += 1;
  494. ieee80211_tx_status(dev->wl->hw, pack->skb);
  495. pack->skb = NULL;
  496. list_add(&pack->list, &q->packets_list);
  497. if (q->stopped) {
  498. ieee80211_wake_queue(dev->wl->hw, q->queue_prio);
  499. q->stopped = false;
  500. }
  501. }
  502. /* Returns whether we should fetch another frame. */
  503. static bool pio_rx_frame(struct b43_pio_rxqueue *q)
  504. {
  505. struct b43_wldev *dev = q->dev;
  506. struct b43_wl *wl = dev->wl;
  507. u16 len;
  508. u32 macstat = 0;
  509. unsigned int i, padding;
  510. struct sk_buff *skb;
  511. const char *err_msg = NULL;
  512. struct b43_rxhdr_fw4 *rxhdr =
  513. (struct b43_rxhdr_fw4 *)wl->pio_scratchspace;
  514. size_t rxhdr_size = sizeof(*rxhdr);
  515. BUILD_BUG_ON(sizeof(wl->pio_scratchspace) < sizeof(*rxhdr));
  516. switch (dev->fw.hdr_format) {
  517. case B43_FW_HDR_410:
  518. case B43_FW_HDR_351:
  519. rxhdr_size -= sizeof(rxhdr->format_598) -
  520. sizeof(rxhdr->format_351);
  521. break;
  522. case B43_FW_HDR_598:
  523. break;
  524. }
  525. memset(rxhdr, 0, rxhdr_size);
  526. /* Check if we have data and wait for it to get ready. */
  527. if (q->rev >= 8) {
  528. u32 ctl;
  529. ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
  530. if (!(ctl & B43_PIO8_RXCTL_FRAMERDY))
  531. return false;
  532. b43_piorx_write32(q, B43_PIO8_RXCTL,
  533. B43_PIO8_RXCTL_FRAMERDY);
  534. for (i = 0; i < 10; i++) {
  535. ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
  536. if (ctl & B43_PIO8_RXCTL_DATARDY)
  537. goto data_ready;
  538. udelay(10);
  539. }
  540. } else {
  541. u16 ctl;
  542. ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
  543. if (!(ctl & B43_PIO_RXCTL_FRAMERDY))
  544. return false;
  545. b43_piorx_write16(q, B43_PIO_RXCTL,
  546. B43_PIO_RXCTL_FRAMERDY);
  547. for (i = 0; i < 10; i++) {
  548. ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
  549. if (ctl & B43_PIO_RXCTL_DATARDY)
  550. goto data_ready;
  551. udelay(10);
  552. }
  553. }
  554. b43dbg(q->dev->wl, "PIO RX timed out\n");
  555. return true;
  556. data_ready:
  557. /* Get the preamble (RX header) */
  558. if (q->rev >= 8) {
  559. b43_block_read(dev, rxhdr, rxhdr_size,
  560. q->mmio_base + B43_PIO8_RXDATA,
  561. sizeof(u32));
  562. } else {
  563. b43_block_read(dev, rxhdr, rxhdr_size,
  564. q->mmio_base + B43_PIO_RXDATA,
  565. sizeof(u16));
  566. }
  567. /* Sanity checks. */
  568. len = le16_to_cpu(rxhdr->frame_len);
  569. if (unlikely(len > 0x700)) {
  570. err_msg = "len > 0x700";
  571. goto rx_error;
  572. }
  573. if (unlikely(len == 0)) {
  574. err_msg = "len == 0";
  575. goto rx_error;
  576. }
  577. switch (dev->fw.hdr_format) {
  578. case B43_FW_HDR_598:
  579. macstat = le32_to_cpu(rxhdr->format_598.mac_status);
  580. break;
  581. case B43_FW_HDR_410:
  582. case B43_FW_HDR_351:
  583. macstat = le32_to_cpu(rxhdr->format_351.mac_status);
  584. break;
  585. }
  586. if (macstat & B43_RX_MAC_FCSERR) {
  587. if (!(q->dev->wl->filter_flags & FIF_FCSFAIL)) {
  588. /* Drop frames with failed FCS. */
  589. err_msg = "Frame FCS error";
  590. goto rx_error;
  591. }
  592. }
  593. /* We always pad 2 bytes, as that's what upstream code expects
  594. * due to the RX-header being 30 bytes. In case the frame is
  595. * unaligned, we pad another 2 bytes. */
  596. padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0;
  597. skb = dev_alloc_skb(len + padding + 2);
  598. if (unlikely(!skb)) {
  599. err_msg = "Out of memory";
  600. goto rx_error;
  601. }
  602. skb_reserve(skb, 2);
  603. skb_put(skb, len + padding);
  604. if (q->rev >= 8) {
  605. b43_block_read(dev, skb->data + padding, (len & ~3),
  606. q->mmio_base + B43_PIO8_RXDATA,
  607. sizeof(u32));
  608. if (len & 3) {
  609. u8 *tail = wl->pio_tailspace;
  610. BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 4);
  611. /* Read the last few bytes. */
  612. b43_block_read(dev, tail, 4,
  613. q->mmio_base + B43_PIO8_RXDATA,
  614. sizeof(u32));
  615. switch (len & 3) {
  616. case 3:
  617. skb->data[len + padding - 3] = tail[0];
  618. skb->data[len + padding - 2] = tail[1];
  619. skb->data[len + padding - 1] = tail[2];
  620. break;
  621. case 2:
  622. skb->data[len + padding - 2] = tail[0];
  623. skb->data[len + padding - 1] = tail[1];
  624. break;
  625. case 1:
  626. skb->data[len + padding - 1] = tail[0];
  627. break;
  628. }
  629. }
  630. } else {
  631. b43_block_read(dev, skb->data + padding, (len & ~1),
  632. q->mmio_base + B43_PIO_RXDATA,
  633. sizeof(u16));
  634. if (len & 1) {
  635. u8 *tail = wl->pio_tailspace;
  636. BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 2);
  637. /* Read the last byte. */
  638. b43_block_read(dev, tail, 2,
  639. q->mmio_base + B43_PIO_RXDATA,
  640. sizeof(u16));
  641. skb->data[len + padding - 1] = tail[0];
  642. }
  643. }
  644. b43_rx(q->dev, skb, rxhdr);
  645. return true;
  646. rx_error:
  647. if (err_msg)
  648. b43dbg(q->dev->wl, "PIO RX error: %s\n", err_msg);
  649. if (q->rev >= 8)
  650. b43_piorx_write32(q, B43_PIO8_RXCTL, B43_PIO8_RXCTL_DATARDY);
  651. else
  652. b43_piorx_write16(q, B43_PIO_RXCTL, B43_PIO_RXCTL_DATARDY);
  653. return true;
  654. }
  655. void b43_pio_rx(struct b43_pio_rxqueue *q)
  656. {
  657. unsigned int count = 0;
  658. bool stop;
  659. while (1) {
  660. stop = !pio_rx_frame(q);
  661. if (stop)
  662. break;
  663. cond_resched();
  664. if (WARN_ON_ONCE(++count > 10000))
  665. break;
  666. }
  667. }
  668. static void b43_pio_tx_suspend_queue(struct b43_pio_txqueue *q)
  669. {
  670. if (q->rev >= 8) {
  671. b43_piotx_write32(q, B43_PIO8_TXCTL,
  672. b43_piotx_read32(q, B43_PIO8_TXCTL)
  673. | B43_PIO8_TXCTL_SUSPREQ);
  674. } else {
  675. b43_piotx_write16(q, B43_PIO_TXCTL,
  676. b43_piotx_read16(q, B43_PIO_TXCTL)
  677. | B43_PIO_TXCTL_SUSPREQ);
  678. }
  679. }
  680. static void b43_pio_tx_resume_queue(struct b43_pio_txqueue *q)
  681. {
  682. if (q->rev >= 8) {
  683. b43_piotx_write32(q, B43_PIO8_TXCTL,
  684. b43_piotx_read32(q, B43_PIO8_TXCTL)
  685. & ~B43_PIO8_TXCTL_SUSPREQ);
  686. } else {
  687. b43_piotx_write16(q, B43_PIO_TXCTL,
  688. b43_piotx_read16(q, B43_PIO_TXCTL)
  689. & ~B43_PIO_TXCTL_SUSPREQ);
  690. }
  691. }
  692. void b43_pio_tx_suspend(struct b43_wldev *dev)
  693. {
  694. b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
  695. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BK);
  696. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BE);
  697. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VI);
  698. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VO);
  699. b43_pio_tx_suspend_queue(dev->pio.tx_queue_mcast);
  700. }
  701. void b43_pio_tx_resume(struct b43_wldev *dev)
  702. {
  703. b43_pio_tx_resume_queue(dev->pio.tx_queue_mcast);
  704. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VO);
  705. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VI);
  706. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BE);
  707. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BK);
  708. b43_power_saving_ctl_bits(dev, 0);
  709. }