android_kernel_samsung_sm8650_ksu/drivers/net/ethernet/toshiba/tc956x/dwxgmac2.h

/*
 * TC956X ethernet driver.
 *
 * dwxgmac2.h
 *
 * Copyright (C) 2018 Synopsys, Inc. and/or its affiliates.
 * Copyright (C) 2021 Toshiba Electronic Devices & Storage Corporation
 *
 * This file has been derived from the STMicro and Synopsys Linux driver,
 * and developed or modified for TC956X.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

/*! History:
 *  17 July 2020 : 1. Filtering updates
 *  VERSION	 : 00-01
 *
 *  15 Mar 2021 : Base lined
 *  VERSION     : 01-00
 *  29 Jul 2021 : 1. Add support to set MAC Address register
 *  VERSION     : 01-00-07
 *  14 Sep 2021 : 1. Synchronization between ethtool vlan features
 *  		  "rx-vlan-offload", "rx-vlan-filter", "tx-vlan-offload" output and register settings.
 * 		  2. Added ethtool support to update "rx-vlan-offload", "rx-vlan-filter",
 *  		  and "tx-vlan-offload".
 * 		  3. Removed IOCTL TC956XMAC_VLAN_STRIP_CONFIG.
 * 		  4. Removed "Disable VLAN Filter" option in IOCTL TC956XMAC_VLAN_FILTERING.
 *  VERSION     : 01-00-13
 *  19 Oct 2021 : 1. Adding M3 SRAM Debug counters to ethtool statistics
 * 		  2. Adding MTL RX Overflow/packet miss count, TX underflow counts,Rx Watchdog value to ethtool statistics.
 *  VERSION     : 01-00-17
 *  25 Oct 2021 : 1. Added EEE macros for MAC controlled EEE.
 *  VERSION     : 01-00-19
 *  31 Jan 2022 : 1. Additional macros defined for debug dump API usage.
 *  VERSION     : 01-00-39
 *  02 Feb 2022 : 1. Macros added for Tx Queue flush and Rx DMA flush
 *  VERSION     : 01-00-40
 */


#ifndef __TC956XMAC_DWXGMAC2_H__
#define __TC956XMAC_DWXGMAC2_H__

#include "common.h"

/* Misc */
#define XGMAC_JUMBO_LEN		(TC956XMAC_ALIGN(9000))

/* MAC Registers */
#define XGMAC_TX_CONFIG		(MAC_OFFSET + 0x00000000)
#define XGMAC_CONFIG_SS_OFF		29
#define XGMAC_CONFIG_SS_MASK		GENMASK(31, 29)
#define XGMAC_CONFIG_SS_10000		(0x0 << XGMAC_CONFIG_SS_OFF)
#define XGMAC_CONFIG_SS_2500_GMII	(0x2 << XGMAC_CONFIG_SS_OFF)
#define XGMAC_CONFIG_SS_1000_GMII	(0x3 << XGMAC_CONFIG_SS_OFF)
#define XGMAC_CONFIG_SS_100_MII	(0x4 << XGMAC_CONFIG_SS_OFF)
#define XGMAC_CONFIG_SS_5000		(0x5 << XGMAC_CONFIG_SS_OFF)
#define XGMAC_CONFIG_SS_2500		(0x6 << XGMAC_CONFIG_SS_OFF)
#define XGMAC_CONFIG_SS_10_MII		(0x7 << XGMAC_CONFIG_SS_OFF)
#define XGMAC_CONFIG_SARC		GENMASK(22, 20)
#define XGMAC_CONFIG_SARC_SHIFT	20
#define XGMAC_CONFIG_JD		BIT(16)
#define XGMAC_CONFIG_TE		BIT(0)
#define XGMAC_CORE_INIT_TX		(XGMAC_CONFIG_JD)
#define XGMAC_RX_CONFIG		(MAC_OFFSET + 0x00000004)
#define XGMAC_CONFIG_ARPEN		BIT(31)
#define XGMAC_CONFIG_GPSL		GENMASK(29, 16)
#define XGMAC_CONFIG_GPSL_SHIFT	16
#define XGMAC_CONFIG_HDSMS		GENMASK(14, 12)
#define XGMAC_CONFIG_HDSMS_SHIFT	12
#define XGMAC_CONFIG_HDSMS_256		(0x2 << XGMAC_CONFIG_HDSMS_SHIFT)
#define XGMAC_CONFIG_S2KP		BIT(11)
#define XGMAC_CONFIG_LM		BIT(10)
#define XGMAC_CONFIG_IPC		BIT(9)
#define XGMAC_CONFIG_JE		BIT(8)
#define XGMAC_CONFIG_WD		BIT(7)
#define XGMAC_CONFIG_GPSLCE		BIT(6)
#define XGMAC_CONFIG_DCRCC		BIT(3)
#define XGMAC_CONFIG_CST		BIT(2)
#define XGMAC_CONFIG_ACS		BIT(1)
#define XGMAC_CONFIG_RE		BIT(0)
#define XGMAC_CORE_INIT_RX		(XGMAC_CONFIG_GPSLCE | XGMAC_CONFIG_WD | \
					((XGMAC_JUMBO_LEN + ETH_HLEN + ETH_FCS_LEN + \
					  VLAN_HLEN) << XGMAC_CONFIG_GPSL_SHIFT))
#define XGMAC_PACKET_FILTER		(MAC_OFFSET + 0x00000008)
#define XGMAC_EXTENDED_REG		(MAC_OFFSET + 0x00000140)
#define XGMAC_PACKET_FILTER_DAIF	BIT(3)
#define XGMAC_PACKET_FILTER_DAIF_LPOS	(3)
#define XGMAC_PACKET_FILTER_SA			BIT(9)
#define XGMAC_PACKET_FILTER_SAIF			BIT(8)
#define XGMAC_SA							BIT(30)

#define XGMAC_PACKET_FILTER_MASK_PR_DIS    (0x7FFFFB6E)
#define XGMAC_PACKET_FILTER_MASK_PR_EN     (0xFFFFFB6E)
#define XGMAC_FILTER_DDS		BIT(7)
#define XGMAC_FILTER_RA		BIT(31)
#define XGMAC_FILTER_IPFE		BIT(20)
#define XGMAC_FILTER_VTFE		BIT(16)
#define XGMAC_FILTER_VTFE_LPOS		(16)
#define XGMAC_FILTER_HPF		BIT(10)
#define XGMAC_FILTER_PCF		BIT(7)
#define XGMAC_FILTER_PM		BIT(4)
#define XGMAC_FILTER_DAIF		BIT(3)
#define XGMAC_FILTER_DAIF_LPOS		(3)
#define XGMAC_FILTER_HMC		BIT(2)
#define XGMAC_FILTER_HUC		BIT(1)
#define XGMAC_FILTER_PR		BIT(0)
#define XGMAC_HASH_TABLE(x)		(MAC_OFFSET + (0x00000010 + (x) * 4))
#define XGMAC_HI_DCS_SHIFT		16
#define XGMAC_HI_REG_AE		BIT(31)
#define XGMAC_HI_REG_DCS_MASK		GENMASK(17, 16)
#define XGMAC_HI_REG_DCS1		BIT(16)
#define XGMAC_HI_REG_DCS2		BIT(17)
#define XGMAC_HI_REG_PF		(BIT(16) | BIT(17))
#define XGMAC_MAX_HASH_TABLE		2
#define XGMAC_HASH_TAB_0_31		(MAC_OFFSET + 0x00000010)
#define XGMAC_HASH_TAB_32_63		(MAC_OFFSET + 0x00000014)
#define XGMAC_VLAN_TAG			(MAC_OFFSET + 0x00000050)
#define XGMAC_VLAN_EVLRXS		BIT(24)
#define XGMAC_VLAN_EDVLP		BIT(26)
#define XGMAC_VLAN_ETV_LPOS		16
#define XGMAC_VLAN_EVLS			GENMASK(22, 21)
#define XGMAC_VLAN_EVLS_SHIFT		21
#define XGMAC_VLAN_VTHM			BIT(25)
#define XGMAC_VLANTR_VTHM_LPOS		(25)
#define XGMAC_VLANTR_VTIM		BIT(17)
#define XGMAC_VLANTR_VTIM_LPOS		(17)
#define XGMAC_VLAN_DOVLTC		BIT(20)
#define XGMAC_VLAN_ERSVLM		BIT(19)
#define XGMAC_VLAN_ESVL		BIT(18)
#define XGMAC_VLAN_ETV			BIT(16)
#define XGMAC_VLAN_ETV_DATA		BIT(17)
#define XGMAC_VLAN_VID			GENMASK(15, 0)
#define XGMAC_VLAN_VL_LPOS		(0)
#define XGMAC_VLAN_HASH_TABLE		(MAC_OFFSET + 0x00000058)
#define XGMAC_VLAN_INCL		(MAC_OFFSET + 0x00000060)
#define XGMAC_VLAN_VLTI		BIT(20)
#define XGMAC_VLAN_CSVL		BIT(19)
#define XGMAC_VLAN_VLC			GENMASK(17, 16)
#define XGMAC_VLAN_VLC_SHIFT		16
#define XGMAC_RXQ_CTRL0		(MAC_OFFSET + 0x000000a0)
#define XGMAC_RXQEN(x)			GENMASK((x) * 2 + 1, (x) * 2)
#define XGMAC_RXQEN_SHIFT(x)		((x) * 2)
#define XGMAC_RXQ_CTRL1		(MAC_OFFSET + 0x000000a4)
#define XGMAC_RQ			GENMASK(7, 4)
#define XGMAC_RQ_SHIFT			4
#define XGMAC_RXQ_CTRL2		(MAC_OFFSET + 0x000000a8)
#define XGMAC_RXQ_CTRL3		(MAC_OFFSET + 0x000000ac)
#define XGMAC_RXQ_CTRL4		(MAC_OFFSET + 0x00000094)
#define XGMAC_VFFQ_MASK			GENMASK(20, 17)
#define XGMAC_VFFQ_SHIFT		17
#define XGMAC_MFFQ_MASK			GENMASK(12, 9)
#define XGMAC_MFFQ_SHIFT		9
#define XGMAC_UFFQ_MASK			GENMASK(4, 1)
#define XGMAC_UFFQ_SHIFT		1
#define XGMAC_VFFQE			BIT(16)
#define XGMAC_MFFQE			BIT(8)
#define XGMAC_UFFQE			BIT(0)
#define XGMAC_PSRQ(x)			GENMASK((x) * 8 + 7, (x) * 8)
#define XGMAC_PSRQ_SHIFT(x)		((x) * 8)
#define XGMAC_INT_STATUS		(MAC_OFFSET + 0x000000b0)
#define XGMAC_TSIS			BIT(12)
#define XGMAC_LPIIS			BIT(5)
#define XGMAC_PMTIS			BIT(4)
#define XGMAC_INT_EN			(MAC_OFFSET + 0x000000b4)
#define XGMAC_TSIE			BIT(12)
#define XGMAC_LPIIE			BIT(5)
#define XGMAC_PMTIE			BIT(4)
#define XGMAC_AUXTSTRIG		BIT(2) /* MAC_Timestamp_Status register */
#ifndef TC956X
#define XGMAC_INT_DEFAULT_EN		(XGMAC_LPIIE | XGMAC_PMTIE)
#else
#define XGMAC_INT_DEFAULT_EN		(XGMAC_LPIIE)
#endif

#define XGMAC_RX_TX_STS			(MAC_OFFSET + 0x000000b8)
#define XGMAC_Qx_TX_FLOW_CTRL(x)	(MAC_OFFSET + (0x00000070 + (x) * 4))
#define XGMAC_PT			GENMASK(31, 16)
#define XGMAC_PT_SHIFT			16
#define XGMAC_TFE			BIT(1)
#define XGMAC_RX_FLOW_CTRL		(MAC_OFFSET + 0x00000090)
#define XGMAC_PFCE			BIT(8)
#define XGMAC_RFE			BIT(0)
#define XGMAC_PMT			(MAC_OFFSET + 0x000000c0)
#define XGMAC_GLBLUCAST		BIT(9)
#define XGMAC_RWKPKTEN			BIT(2)
#define XGMAC_MGKPKTEN			BIT(1)
#define XGMAC_PWRDWN			BIT(0)
#define XGMAC_LPI_CTRL			(MAC_OFFSET + 0x000000d0)
#define XGMAC_TXCGE			BIT(21)
#define XGMAC_LPITXA			BIT(19)

#ifdef EEE_MAC_CONTROLLED_MODE
#define XGMAC_PLSDIS			BIT(18)
#define XGMAC_LPIATE			BIT(20)
#endif
#define XGMAC_PLS			BIT(17)
#define XGMAC_LPITXEN			BIT(16)
#define XGMAC_RLPIEX			BIT(3)
#define XGMAC_RLPIEN			BIT(2)
#define XGMAC_TLPIEX			BIT(1)
#define XGMAC_TLPIEN			BIT(0)
#define XGMAC_LPI_TIMER_CTRL		(MAC_OFFSET + 0x000000d4)

#ifdef EEE_MAC_CONTROLLED_MODE
#define XGMAC_LPI_1US_Tic_Counter	(MAC_OFFSET + 0x000000dc)
#define XGMAC_LPI_Auto_Entry_Timer	(MAC_OFFSET + 0x000000d8)
#define XGMAC_LPIET			0xFFFF8
#endif
#define XGMAC_DEBUG			(MAC_OFFSET + 0x00000114)
#define XGMAC_HW_FEATURE0		(MAC_OFFSET + 0x0000011c)
#define XGMAC_HW_FEATURE0_BASE		(0x0000011c)
#define XGMAC_HWFEAT_SAVLANINS		BIT(27)
#define XGMAC_HWFEAT_RXCOESEL		BIT(16)
#define XGMAC_HWFEAT_TXCOESEL		BIT(14)
#define XGMAC_HWFEAT_EEESEL		BIT(13)
#define XGMAC_HWFEAT_TSSEL		BIT(12)
#define XGMAC_HWFEAT_AVSEL		BIT(11)
#define XGMAC_HWFEAT_RAVSEL		BIT(10)
#define XGMAC_HWFEAT_ARPOFFSEL		BIT(9)
#define XGMAC_HWFEAT_MMCSEL		BIT(8)
#define XGMAC_HWFEAT_MGKSEL		BIT(7)
#define XGMAC_HWFEAT_RWKSEL		BIT(6)
#ifdef TC956X_WITHOUT_MDIO
#define XGMAC_HWFEAT_SMASEL		BIT(5)
#endif
#define XGMAC_HWFEAT_VLHASH		BIT(4)
#define XGMAC_HWFEAT_GMIISEL		BIT(1)
#define XGMAC_HW_FEATURE1		(MAC_OFFSET + 0x00000120)
#define XGMAC_HW_FEATURE1_BASE		(0x00000120)
#define XGMAC_HWFEAT_L3L4FNUM		GENMASK(30, 27)
#define XGMAC_HWFEAT_HASHTBLSZ		GENMASK(25, 24)
#define XGMAC_HWFEAT_RSSEN		BIT(20)
#define XGMAC_HWFEAT_TSOEN		BIT(18)
#define XGMAC_HWFEAT_SPHEN		BIT(17)
#define XGMAC_HWFEAT_OSTEN		BIT(11)
#define XGMAC_HWFEAT_PTOEN		BIT(12)
#define XGMAC_HWFEAT_ADDR64		GENMASK(15, 14)
#define XGMAC_HWFEAT_TXFIFOSIZE	GENMASK(10, 6)
#define XGMAC_HWFEAT_RXFIFOSIZE	GENMASK(4, 0)
#define XGMAC_HW_FEATURE2		(MAC_OFFSET + 0x00000124)
#define XGMAC_HW_FEATURE2_BASE		(0x00000124)
#define XGMAC_HWFEAT_PPSOUTNUM		GENMASK(26, 24)
#define XGMAC_HWFEAT_TXCHCNT		GENMASK(21, 18)
#define XGMAC_HWFEAT_TXCHCNT_SHIFT	(18)
#define XGMAC_HWFEAT_RXCHCNT		GENMASK(15, 12)
#define XGMAC_HWFEAT_RXCHCNT_SHIFT	(12)
#define XGMAC_HWFEAT_TXQCNT		GENMASK(9, 6)
#define XGMAC_HWFEAT_RXQCNT		GENMASK(3, 0)
#define XGMAC_HW_FEATURE3		(MAC_OFFSET + 0x00000128)
#define XGMAC_HW_FEATURE3_BASE		(0x00000128)
#define XGMAC_HWFEAT_TBSSEL		BIT(27)
#define XGMAC_HWFEAT_FPESEL		BIT(26)
#define XGMAC_HWFEAT_ESTWID		GENMASK(24, 23)
#define XGMAC_HWFEAT_ESTDEP		GENMASK(22, 20)
#define XGMAC_HWFEAT_ESTSEL		BIT(19)
#define XGMAC_HWFEAT_ASP		GENMASK(15, 14)
#define XGMAC_HWFEAT_DVLAN		BIT(13)
#define XGMAC_HWFEAT_FRPES		GENMASK(12, 11)
#define XGMAC_HWFEAT_FRPPB		GENMASK(10, 9)
#define XGMAC_HWFEAT_FRPSEL		BIT(3)
#define XGMAC_MAC_DPP_FSM_INT_STATUS	(MAC_OFFSET + 0x00000150)
#define XGMAC_MAC_FSM_CONTROL		(MAC_OFFSET + 0x00000158)
#define XGMAC_PRTYEN			BIT(1)
#define XGMAC_TMOUTEN			BIT(0)
#define XGMAC_MDIO_ADDR		(MAC_OFFSET + 0x00000200)
#define XGMAC_MDIO_DATA		(MAC_OFFSET + 0x00000204)
#define XGMAC_MDIO_C22P		(MAC_OFFSET + 0x00000220)
#define XGMAC_FPE_CTRL_STS		(MAC_OFFSET + 0x00000280)
#define XGMAC_EFPE			BIT(0)
#define XGMAC_ADDRx_HIGH(x)		(MAC_OFFSET + (0x00000300 + (x) * 0x8))
#define XGMAC_VLAN_TAG_CTRL		(MAC_OFFSET + 0x00000050)
#define XGMAC_VLAN_TAG_DATA		(MAC_OFFSET + 0x00000054)
#define XGMAC_ADDR_OFFSET			GENMASK(6, 2)
#define XGMAC_ADDR_OFFSET_LPOS		2
#define XGMAC_VLAN_CT			BIT(1)
#define XGMAC_VLAN_OB			BIT(0)
#define XGMAC_VLAN_DMACHE		BIT(24)
#define XGMAC_VLAN_EN			BIT(16)
#define TC956X_VLAN_DMACH		BIT(25)	/* DMA CHANNEL = 1*/
#define XGMAC_DMA_In(x)		(MAC_OFFSET + (0x00000704 + (x) * 0x4))
#define XGMAC_INDR_ACC_CTRL		(MAC_OFFSET + 0x00000700)
#define XGMAC_INDR_ACC_CTRL_RSVD	BIT(31)
#define XGMAC_INDR_ACC_CTRL_MSEL	GENMASK(19, 16)
#define XGMAC_INDR_ACC_CTRL_MSEL_SHIFT	(16)
#define XGMAC_INDR_ACC_CTRL_AOFF	GENMASK(15, 8)
#define XGMAC_INDR_ACC_CTRL_AOFF_SHIFT	(8)
#define XGMAC_INDR_ACC_CTRL_AUTO	BIT(5)
#define XGMAC_INDR_ACC_CTRL_COM		BIT(1)
#define XGMAC_INDR_ACC_CTRL_COM_SHIFT	(1)
#define XGMAC_INDR_ACC_CTRL_OB		BIT(0)
#define XGMAC_INDR_ACC_CTRL_OB_SHIFT	(0)
#define XGMAC_DCHSEL			(0)
#define XGMAC_INDR_ACC_DATA		(MAC_OFFSET + 0x00000704)
#define XGMAC_MSEL_DCHSEL		(0)
#define XGMAC_COM_READ			(1)
#define XGMAC_COM_WRITE			(0)
#define XGMAC_ADDR_MAX			32
#define XGMAC_AE			BIT(31)
#define XGMAC_AE_SHIFT			31
#define XGMAC_MBC			GENSMASK(29, 24)
#define XGMAC_MBC_SHIFT		24
#define XGMAC_DCS			GENMASK(19, 16)
#define XGMAC_DCS_SHIFT		16
#define XGMAC_ADDRx_LOW(x)		(MAC_OFFSET + (0x00000304 + (x) * 0x8))
#define XGMAC_L3L4_ADDR_CTRL		(MAC_OFFSET + 0x00000c00)
#define XGMAC_IDDR			GENMASK(15, 8)
#define XGMAC_IDDR_SHIFT		8
#define XGMAC_IDDR_FNUM		4
#define XGMAC_TT			BIT(1)
#define XGMAC_XB			BIT(0)
#define XGMAC_L3L4_DATA		(MAC_OFFSET + 0x00000c04)
#define XGMAC_L3L4_CTRL		0x0
#define XGMAC_L4DPIM0			BIT(21)
#define XGMAC_L4DPM0			BIT(20)
#define XGMAC_L4SPIM0			BIT(19)
#define XGMAC_L4SPM0			BIT(18)
#define XGMAC_L4PEN0			BIT(16)
#define XGMAC_L3HDBM0			GENMASK(15, 11)
#define XGMAC_L3HSBM0			GENMASK(10, 6)
#define XGMAC_L3DAIM0			BIT(5)
#define XGMAC_L3DAM0			BIT(4)
#define XGMAC_L3SAIM0			BIT(3)
#define XGMAC_L3SAM0			BIT(2)
#define XGMAC_L3PEN0			BIT(0)
#define XGMAC_L4_ADDR			0x1
#define XGMAC_L4DP0			GENMASK(31, 16)
#define XGMAC_L4DP0_SHIFT		16
#define XGMAC_L4SP0			GENMASK(15, 0)
#define XGMAC_L3_ADDR0			0x4
#define XGMAC_L3_ADDR1			0x5
#define XGMAC_L3_ADDR2			0x6
#define XMGAC_L3_ADDR3			0x7
#define XGMAC_ARP_ADDR			(MAC_OFFSET + 0x00000c10)
#define XGMAC_RSS_CTRL			(MAC_OFFSET + 0x00000c80)
#define XGMAC_UDP4TE			BIT(3)
#define XGMAC_TCP4TE			BIT(2)
#define XGMAC_IP2TE			BIT(1)
#define XGMAC_RSSE			BIT(0)
#define XGMAC_RSS_ADDR			(MAC_OFFSET + 0x00000c88)
#define XGMAC_RSSIA_SHIFT		8
#define XGMAC_ADDRT			BIT(2)
#define XGMAC_CT			BIT(1)
#define XGMAC_OB			BIT(0)
#define XGMAC_RSS_DATA			(MAC_OFFSET + 0x00000c8c)
#define XGMAC_TIMESTAMP_STATUS		(MAC_OFFSET + 0x00000d20)
#define XGMAC_TXTSC			BIT(15)
#define XGMAC_TXTIMESTAMP_NSEC		(MAC_OFFSET + 0x00000d30)
#define XGMAC_TXTSSTSLO		GENMASK(30, 0)
#define XGMAC_TXTIMESTAMP_SEC		(MAC_OFFSET + 0x00000d34)
#define XGMAC_INGRESSTIMESTAMP_NSEC	(MAC_OFFSET + 0x00000d58)
#define XGMAC_INGRESSTIMESTAMP_SEC	(MAC_OFFSET + 0x00000d5c)
#define XGMAC_PPS_CONTROL		(MAC_OFFSET + 0x00000d70)
#define XGMAC_PPS_MAXIDX(x)		((((x) + 1) * 8) - 1)
#define XGMAC_PPS_MINIDX(x)		((x) * 8)
#define XGMAC_PPSx_MASK(x)		\
	(GENMASK(XGMAC_PPS_MAXIDX(x), XGMAC_PPS_MINIDX(x)))
#define XGMAC_TRGTMODSELx(x, val)	\
	(GENMASK(XGMAC_PPS_MAXIDX(x) - 1, XGMAC_PPS_MAXIDX(x) - 2) & \
	((val) << (XGMAC_PPS_MAXIDX(x) - 2)))
#define XGMAC_PPSCMDx(x, val)		\
	(GENMASK(XGMAC_PPS_MINIDX(x) + 3, XGMAC_PPS_MINIDX(x)) & \
	((val) << XGMAC_PPS_MINIDX(x)))
#define XGMAC_PPSCMD_START		0x2
#define XGMAC_PPSCMD_STOP		0x5
#define XGMAC_PPSEN0			BIT(4)
#define XGMAC_PPSx_TARGET_TIME_SEC(x)	(MAC_OFFSET + (0x00000d80 + (x) * 0x10))
#define XGMAC_PPSx_TARGET_TIME_NSEC(x)	(MAC_OFFSET + (0x00000d84 + (x) * 0x10))
#define XGMAC_TRGTBUSY0			BIT(31)
#define XGMAC_PPSx_INTERVAL(x)	(MAC_OFFSET + (0x00000d88 + (x) * 0x10))
#define XGMAC_PPSx_WIDTH(x)		(MAC_OFFSET + (0x00000d8c + (x) * 0x10))
#define XGMAC_PTO_CTRL			(MAC_OFFSET + 0x00000dc0)
#define XGMAC_APDREQEN			BIT(2)
#define XGMAC_ASYNCEN			BIT(1)
#define XGMAC_PTOEN			BIT(0)

#define ABSOLUTE_LEOS			0x2FAF1 /* Launch Expiry Offset ~50ms */
#define EST_LEOS			0x1E4 /* Launch expiry offset ~124us (CTR -1) */
#define LEGOS				7

#ifdef TC956X
#define XGMAC_MAC_AUX_CTRL		(MAC_OFFSET + 0x00000d40)
#endif
#define XGMAC_ATSEN3			BIT(7)
#define XGMAC_ATSEN2			BIT(6)
#define XGMAC_ATSEN1			BIT(5)
#define XGMAC_ATSEN0			BIT(4)
#define XGMAC_ATSFC			BIT(0)

/* MTL Registers */
#define XGMAC_MTL_OPMODE		(MAC_OFFSET + 0x00001000)
#define XGMAC_FRPE			BIT(15)
#define XGMAC_ETSALG			GENMASK(6, 5)
#define XGMAC_WRR			(0x0 << 5)
#define XGMAC_WFQ			(0x1 << 5)
#define XGMAC_DWRR			(0x2 << 5)
#define XGMAC_RAA			BIT(2)
#define XGMAC_MTL_INT_STATUS		(MAC_OFFSET + 0x00001020)
#define XGMAC_MTL_RXQ_DMA_MAP0		(MAC_OFFSET + 0x00001030)
#define XGMAC_MTL_RXQ_DMA_MAP1		(MAC_OFFSET + 0x00001034)
#define XGMAC_QxDDMACH_SHIFT(x)		((x * 8) + 7)
#define XGMAC_QxMDMACH(x)		GENMASK((x) * 8 + 7, (x) * 8)
#define XGMAC_QxMDMACH_SHIFT(x)	((x) * 8)
#define XGMAC_QDDMACH			BIT(7)
#define XGMAC_TC_PRTY_MAP0		(MAC_OFFSET + 0x00001040)
#define XGMAC_TC_PRTY_MAP1		(MAC_OFFSET + 0x00001044)
#define XGMAC_PSTC(x)			GENMASK((x) * 8 + 7, (x) * 8)
#define XGMAC_PSTC_SHIFT(x)		((x) * 8)
#define XGMAC_MTL_TBS_CTRL		(MAC_OFFSET + 0x00001048)
#define XGMAC_LEOS			GENMASK(31, 8)
#define XGMAC_LEOS_SHIFT		8
#define XGMAC_ESTM			BIT(0)
#define XGMAC_MTL_EST_CONTROL		(MAC_OFFSET + 0x00001050)
#define XGMAC_PTOV			GENMASK(31, 23)
#define XGMAC_PTOV_SHIFT		23
#define XGMAC_SSWL			BIT(1)
#define XGMAC_EEST			BIT(0)
#define XGMAC_MTL_EST_STATUS		(MAC_OFFSET + 0x00001058)
#define XGMAC_SWOL			BIT(7)
#define XGMAC_MTL_EST_GCL_CONTROL	(MAC_OFFSET + 0x00001080)
#define XGMAC_BTR_LOW			0x0
#define XGMAC_BTR_HIGH			0x1
#define XGMAC_CTR_LOW			0x2
#define XGMAC_CTR_HIGH			0x3
#define XGMAC_TER			0x4
#define XGMAC_LLR			0x5
#define XGMAC_ADDR_SHIFT		8
#define XGMAC_DBGM			BIT(4)
#define XGMAC_GCRR			BIT(2)
#define XGMAC_R1W0			BIT(1)
#define XGMAC_SRWO			BIT(0)
#define XGMAC_MTL_EST_GCL_DATA		(MAC_OFFSET + 0x00001084)
#define XGMAC_MTL_FPE_CTRL_STS		(MAC_OFFSET + 0x00001090)
#define XGMAC_MTL_FPE_PEC_MASK		GENMASK(15, 8)
#define XGMAC_MTL_FPE_PEC_SHIFT	8
#define XGMAC_MTL_FPE_AFSZ_MASK	GENMASK(1, 0)
#define XGMAC_MTL_FPE_ADVANCE		(MAC_OFFSET + 0x00001094)
#define XGMAC_MTL_FPE_HOLD_ADVANCE_MASK	GENMASK(15, 0)
#define XGMAC_MTL_FPE_RELEASE_ADVANCE_MASK	GENMASK(31, 16)
#define XGMAC_MTL_FPE_ADVANCE_SHIFT	16
#define XGMAC_MTL_RXP_CONTROL_STATUS	(MAC_OFFSET + 0x000010a0)
#define XGMAC_RXPI			BIT(31)
#define XGMAC_NPE			GENMASK(23, 16)
#define XGMAC_NVE			GENMASK(7, 0)
#define XGMAC_MTL_RXP_IACC_CTRL_ST	(MAC_OFFSET + 0x000010b0)
#define XGMAC_STARTBUSY		BIT(31)
#define XGMAC_ACCSEL		BIT(24)
#define XGMAC_WRRDN			BIT(16)
#define XGMAC_ADDR			GENMASK(9, 0)
#define XGMAC_MTL_RXP_IACC_DATA	(MAC_OFFSET + 0x000010b4)
#define XGMAC_MTL_ECC_CONTROL		(MAC_OFFSET + 0x000010c0)
#define XGMAC_MTL_SAFETY_INT_STATUS	(MAC_OFFSET + 0x000010c4)
#define XGMAC_MEUIS			BIT(1)
#define XGMAC_MECIS			BIT(0)
#define XGMAC_MTL_ECC_INT_ENABLE	(MAC_OFFSET + 0x000010c8)
#define XGMAC_RPCEIE			BIT(12)
#define XGMAC_ECEIE			BIT(8)
#define XGMAC_RXCEIE			BIT(4)
#define XGMAC_TXCEIE			BIT(0)
#define XGMAC_MTL_ECC_INT_STATUS	(MAC_OFFSET + 0x000010cc)
#define XGMAC_MTL_TXQ_OPMODE(x)	(MAC_OFFSET + (0x00001100 + (0x80 * (x))))
#define XGMAC_TQS			GENMASK(25, 16)
#define XGMAC_TQS_SHIFT		16
#define XGMAC_Q2TCMAP			GENMASK(10, 8)
#define XGMAC_Q2TCMAP_SHIFT		8
#define XGMAC_TTC			GENMASK(6, 4)
#define XGMAC_TTC_SHIFT		4
#define XGMAC_TXQEN			GENMASK(3, 2)
#define XGMAC_TXQEN_SHIFT		2
#define XGMAC_TSF			BIT(1)
#define XGMAC_FTQ			BIT(0)

#define XGMAC_MTL_TXQ_UF_OFFSET(x)	(MAC_OFFSET + (0x00001104 + (0x80 * (x))))
#define XGMAC_MTL_UFPKTCNT_MASK		GENMASK(10, 0)
#define XGMAC_MTL_TXQ_UFPKT_CNT(x)	((XGMAC_MTL_TXQ_UF_OFFSET(x)) & XGMAC_MTL_UFPKTCNT_MASK)

#define XGMAC_MTL_TXQ_Debug(x)		(MAC_OFFSET + (0x00001108 + (0x80 * (x))))
#define XGMAC_MTL_DEBUG_TXQSTS		BIT(4)
#define XGMAC_MTL_DEBUG_TWCSTS		BIT(3)
#define XGMAC_MTL_DEBUG_TRCSTS_MASK	GENMASK(2, 1)
#define XGMAC_MTL_DEBUG_TRCSTS_SHIFT	1
#define XGMAC_MTL_DEBUG_TRCSTS_IDLE	0
#define XGMAC_MTL_DEBUG_TRCSTS_READ	1
#define XGMAC_MTL_DEBUG_TRCSTS_TXW	2
#define XGMAC_MTL_DEBUG_TRCSTS_WRITE	3
#define XGMAC_MTL_DEBUG_TCPAUSED	BIT(0)
#define XGMAC_MTL_TCx_ETS_CONTROL(x)	(MAC_OFFSET + (0x00001110 + (0x80 * (x))))
#define XGMAC_MTL_TCx_QUANTUM_WEIGHT(x) (MAC_OFFSET + (0x00001118 + (0x80 * (x))))
#define XGMAC_MTL_TCx_SENDSLOPE(x)	(MAC_OFFSET + (0x0000111c + (0x80 * (x))))
#define XGMAC_MTL_TCx_HICREDIT(x)	(MAC_OFFSET + (0x00001120 + (0x80 * (x))))
#define XGMAC_MTL_TCx_LOCREDIT(x)	(MAC_OFFSET + (0x00001124 + (0x80 * (x))))
#define XGMAC_CC			BIT(3)
#define XGMAC_TSA			GENMASK(1, 0)
#define XGMAC_SP			(0x0 << 0)
#define XGMAC_CBS			(0x1 << 0)
#define XGMAC_ETS			(0x2 << 0)
#define XGMAC_MTL_RXQ_OPMODE(x)	(MAC_OFFSET + (0x00001140 + (0x80 * (x))))
#define XGMAC_RQS			GENMASK(25, 16)
#define XGMAC_RQS_SHIFT		16
#define XGMAC_EHFC			BIT(7)
#define XGMAC_RSF			BIT(5)
#define XGMAC_RTC			GENMASK(1, 0)
#define XGMAC_RTC_SHIFT		0
#define XGMAC_MTL_RXQ_MISS_PKT_OF_CNT_OFFSET(x)	(MAC_OFFSET + 0x00001144 + (0x80 * (x)))
#define XGMAC_OVFPKTCNT_MASK		GENMASK(10, 0)
#define XGMAC_MISPKTCNT_MASK		GENMASK(26, 16)
#define XGMAC_MISPKTCNT_SHIFT		16

#ifdef TC956X_SRIOV_PF
#define XGMAC_MTL_RXQ_Debug(x)		(MAC_OFFSET + (0x00001148 + (0x80 * (x))))
#elif defined TC956X_SRIOV_VF
#define XGMAC_MTL_RXQ_Debug(x)		(0x00001148 + (0x80 * (x)))
#endif
#define XGMAC_MTL_DEBUG_RXQSTS_MASK	GENMASK(5, 4)
#define XGMAC_MTL_DEBUG_RXQSTS_SHIFT	4
#define XGMAC_MTL_DEBUG_RXQSTS_EMPTY	0
#define XGMAC_MTL_DEBUG_RXQSTS_BT	1
#define XGMAC_MTL_DEBUG_RXQSTS_AT	2
#define XGMAC_MTL_DEBUG_RXQSTS_FULL	3
#define XGMAC_MTL_DEBUG_RRCSTS_MASK	GENMASK(2, 1)
#define XGMAC_MTL_DEBUG_RRCSTS_SHIFT	1
#define XGMAC_MTL_DEBUG_RRCSTS_IDLE	0
#define XGMAC_MTL_DEBUG_RRCSTS_RDATA	1
#define XGMAC_MTL_DEBUG_RRCSTS_RSTAT	2
#define XGMAC_MTL_DEBUG_RRCSTS_FLUSH	3
#define XGMAC_MTL_DEBUG_RWCSTS		BIT(0)
#define XGMAC_DEBUG_TFCSTS_MASK	GENMASK(18, 17)
#define XGMAC_DEBUG_TFCSTS_SHIFT	17
#define XGMAC_DEBUG_TFCSTS_IDLE	0
#define XGMAC_DEBUG_TFCSTS_WAIT	1
#define XGMAC_DEBUG_TFCSTS_GEN_PAUSE	2
#define XGMAC_DEBUG_TFCSTS_XFER	3
#define XGMAC_DEBUG_TPESTS		BIT(16)
#define XGMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
#define XGMAC_DEBUG_RFCFCSTS_SHIFT	1
#define XGMAC_DEBUG_RPESTS		BIT(0)
#define XGMAC_MTL_RXQ_FLOW_CONTROL(x)	(MAC_OFFSET + (0x00001150 + (0x80 * (x))))
#define XGMAC_RFD			GENMASK(31, 17)
#define XGMAC_RFD_SHIFT		17
#define XGMAC_RFA			GENMASK(15, 1)
#define XGMAC_RFA_SHIFT		1
#define XGMAC_MTL_QINTEN(x)		(MAC_OFFSET + (0x00001170 + (0x80 * (x))))
#define XGMAC_RXOIE			BIT(16)
#define XGMAC_MTL_QINT_STATUS(x)	(MAC_OFFSET + (0x00001174 + (0x80 * (x))))
#define XGMAC_RXOVFIS			BIT(16)
#define XGMAC_ABPSIS			BIT(1)
#define XGMAC_TXUNFIS			BIT(0)
#ifdef TC956X
#define XGMAC_MAC_REGSIZE		(XGMAC_MTL_QINT_STATUS(7) / 4)/*Total 7 queue*/
#else
#define XGMAC_MAC_REGSIZE		(XGMAC_MTL_QINT_STATUS(15) / 4)
#endif

/* Rx Queue Routing */
#define XGMAC_RXQCTRL_AVCPQ_MASK	GENMASK(31, 28)
#define XGMAC_RXQCTRL_AVCPQ_SHIFT	28
#define XGMAC_RXQCTRL_PTPQ_MASK	GENMASK(27, 24)
#define XGMAC_RXQCTRL_PTPQ_SHIFT	24
#define XGMAC_RXQCTRL_TACPQE		BIT(23)
#define XGMAC_RXQCTRL_TACPQE_SHIFT	23
#define XGMAC_RXQCTRL_TPQC_MASK	GENMASK(23, 21)
#define XGMAC_RXQCTRL_TPQC_SHIFT	21
#define XGMAC_RXQCTRL_OMCBCQ		BIT(20)
#define XGMAC_RXQCTRL_OMCBCQ_SHIFT	20
#define XGMAC_RXQCTRL_DCBCPQ_MASK	GENMASK(19, 16)
#define XGMAC_RXQCTRL_DCBCPQ_SHIFT	16
#define XGMAC_RXQCTRL_MCBCQEN		BIT(15)
#define XGMAC_RXQCTRL_MCBCQEN_SHIFT	15
#define XGMAC_RXQCTRL_MCBCQ_MASK	GENMASK(11, 8)
#define XGMAC_RXQCTRL_MCBCQ_SHIFT	8
#define XGMAC_RXQCTRL_FPRQ_MASK	GENMASK(7, 4)
#define XGMAC_RXQCTRL_FPRQ_SHIFT	4
#define XGMAC_RXQCTRL_UPQ_MASK		GENMASK(3, 0)
#define XGMAC_RXQCTRL_UPQ_SHIFT	0

/* DMA Registers */
#define XGMAC_DMA_MODE			(MAC_OFFSET + 0x00003000)
#define XGMAC_DSPW			BIT(8)
#define XGMAC_DSPW_SHIFT		8
#define XGMAC_SWR			BIT(0)
#define XGMAC_DMA_MODE_INTM_MASK	GENMASK(13, 12)
//#define XGMAC_DMA_MODE_INTM_SHIFT	12
#define XGMAC_DMA_MODE_INTM			BIT(12)

#define XGMAC_DMA_SYSBUS_MODE		(MAC_OFFSET + 0x00003004)
#define XGMAC_WR_OSR_LMT		GENMASK(29, 24)
#define XGMAC_WR_OSR_LMT_SHIFT		24
#define XGMAC_RD_OSR_LMT		GENMASK(21, 16)
#define XGMAC_RD_OSR_LMT_SHIFT		16
#define XGMAC_EN_LPI			BIT(15)
#define XGMAC_LPI_XIT_PKT		BIT(14)
#define XGMAC_AAL			BIT(12)
#define XGMAC_EAME			BIT(11)
#define XGMAC_BLEN			GENMASK(7, 1)
#define XGMAC_BLEN256			BIT(7)
#define XGMAC_BLEN128			BIT(6)
#define XGMAC_BLEN64			BIT(5)
#define XGMAC_BLEN32			BIT(4)
#define XGMAC_BLEN16			BIT(3)
#define XGMAC_BLEN8			BIT(2)
#define XGMAC_BLEN4			BIT(1)
#define XGMAC_UNDEF			BIT(0)
#define XGMAC_TX_EDMA_CTRL		(MAC_OFFSET + 0x00003040)
#define XGMAC_TDPS			BIT(30)
#define XGMAC_RX_EDMA_CTRL		(MAC_OFFSET + 0x00003044)
#define XGMAC_RDPS			GENMASK(29, 0)
#define XGMAC_DMA_TBS_CTRL0		(MAC_OFFSET + 0x00003054)
#define XGMAC_DMA_TBS_CTRL1		(MAC_OFFSET + 0x00003058)
#define XGMAC_DMA_TBS_CTRL2		(MAC_OFFSET + 0x0000305c)
#define XGMAC_DMA_TBS_CTRL3		(MAC_OFFSET + 0x00003060)
#define XGMAC_FTOS			GENMASK(31, 8)
#define XGMAC_FTOS_SHIFT		8
#define XGMAC_FGOS			GENMASK(6, 4)
#define XGMAC_FGOS_SHIFT		4
#define XGMAC_FTOV			BIT(0)
#define XGMAC_DEF_FTOS			(XGMAC_FTOS | XGMAC_FTOV)
#define XGMAC_DMA_SAFETY_INT_STATUS	(MAC_OFFSET + 0x00003064)
#define XGMAC_MCSIS			BIT(31)
#define XGMAC_MSUIS			BIT(29)
#define XGMAC_MSCIS			BIT(28)
#define XGMAC_DEUIS			BIT(1)
#define XGMAC_DECIS			BIT(0)
#define XGMAC_DMA_ECC_INT_ENABLE	(MAC_OFFSET + 0x00003068)
#define XGMAC_DCEIE			BIT(1)
#define XGMAC_TCEIE			BIT(0)
#define XGMAC_DMA_ECC_INT_STATUS	(MAC_OFFSET + 0x0000306c)
#define XGMAC_DMA_CH_CONTROL(x)	(MAC_OFFSET + (0x00003100 + (0x80 * (x))))
#define XGMAC_SPH			BIT(24)
#define XGMAC_PBLx8			BIT(16)
#define XGMAC_DMA_CH_TX_CONTROL(x)	(MAC_OFFSET + (0x00003104 + (0x80 * (x))))
#define XGMAC_EDSE			BIT(28)
#define XGMAC_TFSEL			GENMASK(30, 29)
#define XGMAC_TFSEL_SHIFT		29
#define XGMAC_TxPBL			GENMASK(21, 16)
#define XGMAC_TxPBL_SHIFT		16
#define XGMAC_TSE			BIT(12)
#define XGMAC_OSP			BIT(4)
#define XGMAC_TXST			BIT(0)
#define XGMAC_DMA_CH_RX_CONTROL(x)	(MAC_OFFSET + (0x00003108 + (0x80 * (x))))
#define XGMAC_RxPBL			GENMASK(21, 16)
#define XGMAC_RxPBL_SHIFT		16
#define XGMAC_RBSZ			GENMASK(14, 1)
#define XGMAC_RBSZ_SHIFT		1
#define XGMAC_RXST			BIT(0)
#define XGMAC_RPF			BIT(31)
#define XGMAC_DMA_CH_TxDESC_HADDR(x)	(MAC_OFFSET + (0x00003110 + (0x80 * (x))))
#define XGMAC_DMA_CH_TxDESC_LADDR(x)	(MAC_OFFSET + (0x00003114 + (0x80 * (x))))
#define XGMAC_DMA_CH_RxDESC_HADDR(x)	(MAC_OFFSET + (0x00003118 + (0x80 * (x))))
#define XGMAC_DMA_CH_RxDESC_LADDR(x)	(MAC_OFFSET + (0x0000311c + (0x80 * (x))))
#define XGMAC_DMA_CH_TxDESC_TAIL_LPTR(x)	(MAC_OFFSET + (0x00003124 + (0x80 * (x))))
#define XGMAC_DMA_CH_RxDESC_TAIL_LPTR(x)	(MAC_OFFSET + (0x0000312c + (0x80 * (x))))
#define XGMAC_DMA_CH_TX_CONTROL2(x)	(MAC_OFFSET + (0x00003130 + (0x80 * (x))))
#define XGMAC_TDRL			GENMASK(12, 0)
#define XGMAC_TDRL_SHIFT		0
#define XGMAC_DMA_CH_RX_CONTROL2(x)	(MAC_OFFSET + (0x00003134 + (0x80 * (x))))
#define XGMAC_OWRQ			GENMASK(25, 24)
#define XGMAC_OWRQ_SHIFT		24
#define XGMAC_RDRL			GENMASK(12, 0)
#define XGMAC_RDRL_SHIFT		0
#define XGMAC_DMA_CH_INT_EN(x)		(MAC_OFFSET + (0x00003138 + (0x80 * (x))))
#define XGMAC_NIE			BIT(15)
#define XGMAC_AIE			BIT(14)
#define XGMAC_RBUE			BIT(7)
#define XGMAC_RIE			BIT(6)
#define XGMAC_TBUE			BIT(2)
#define XGMAC_TIE			BIT(0)
#define XGMAC_DMA_INT_DEFAULT_EN	(XGMAC_NIE | XGMAC_AIE | XGMAC_RBUE | \
					XGMAC_RIE | XGMAC_TIE)
#define XGMAC_DMA_INT_DEFAULT_RX	(XGMAC_RBUE | XGMAC_RIE)
#define XGMAC_DMA_INT_DEFAULT_TX	(XGMAC_TIE)
#define XGMAC_DMA_CH_Rx_WATCHDOG(x)	(MAC_OFFSET + (0x0000313c + (0x80 * (x))))
#define XGMAC_RWT			GENMASK(7, 0)
#define XGMAC_DMA_CH_STATUS(x)		(MAC_OFFSET + (0x00003160 + (0x80 * (x))))

#define XGMAC_DMA_CH_DBG_STATUS(x)	(MAC_OFFSET + (0x00003164 + (0x80 * (x))))

#define XGMAC_NIS			BIT(15)
#define XGMAC_AIS			BIT(14)
#define XGMAC_FBE			BIT(12)
#define XGMAC_RBU			BIT(7)
#define XGMAC_RI			BIT(6)
#define XGMAC_TBU			BIT(2)
#define XGMAC_TPS			BIT(1)
#define XGMAC_TI			BIT(0)
#define XGMAC_RPS			BIT(8)

#define XGMAC_DMA_CH_Cur_TxDESC_HADDR(x)	(MAC_OFFSET + (0x00003140 + (0x80 * (x))))
#define XGMAC_DMA_CH_Cur_TxDESC_LADDR(x)	(MAC_OFFSET + (0x00003144 + (0x80 * (x))))
#define XGMAC_DMA_CH_Cur_RxDESC_HADDR(x)	(MAC_OFFSET + (0x00003148 + (0x80 * (x))))
#define XGMAC_DMA_CH_Cur_RxDESC_LADDR(x)	(MAC_OFFSET + (0x0000314C + (0x80 * (x))))
#define XGMAC_DMA_CH_Cur_TxBuff_HADDR(x)	(MAC_OFFSET + (0x00003150 + (0x80 * (x))))
#define XGMAC_DMA_CH_Cur_TxBuff_LADDR(x)	(MAC_OFFSET + (0x00003154 + (0x80 * (x))))
#define XGMAC_DMA_CH_Cur_RxBuff_HADDR(x)	(MAC_OFFSET + (0x00003158 + (0x80 * (x))))
#define XGMAC_DMA_CH_Cur_RxBuff_LADDR(x)	(MAC_OFFSET + (0x0000315c + (0x80 * (x))))

#define XGMAC_DMA_DEBUG_STATUS0			(MAC_OFFSET + 0x3020)

#ifdef TC956X
#define XGMAC_REGSIZE			(0x000034FC / 4)
#else
#define XGMAC_REGSIZE			(((0x0000317c + (0x80 * 15)) / 4))
#endif
#define XGMAC_DMA_REG_SIZE		((0x00003084) / 4)
/* CRC & Pad Values */
#ifdef TC956X
#define TC956X_TX_CRC_PAD_INSERT	0
#define TC956X_TX_CRC_INSERT		1
#define TC956X_TX_CRC_PAD_DISABLE	2
#define TC956X_TX_CRC_REPLACE		3

#define TC956X_RX_CRC_DISABLE_CHECK	XGMAC_CONFIG_DCRCC
#define TC956X_RX_CRC_TYPE_STRIP	XGMAC_CONFIG_CST
#define TC956X_RX_CRC_PAD_STRIP	XGMAC_CONFIG_ACS
#define TC956X_RX_CRC_DEFAULT		(XGMAC_CONFIG_ACS | XGMAC_CONFIG_CST)
#endif
/* Descriptors */
#define XGMAC_TDES0_LTV		BIT(31)
#define XGMAC_TDES0_LT			GENMASK(7, 0)
#define XGMAC_TDES1_LT			GENMASK(31, 8)
#define XGMAC_TDES2_IVT		GENMASK(31, 16)
#define XGMAC_TDES2_IVT_SHIFT		16
#define XGMAC_TDES2_IOC		BIT(31)
#define XGMAC_TDES2_TTSE		BIT(30)
#define XGMAC_TDES2_B2L		GENMASK(29, 16)
#define XGMAC_TDES2_B2L_SHIFT		16
#define XGMAC_TDES2_VTIR		GENMASK(15, 14)
#define XGMAC_TDES2_VTIR_SHIFT		14
#define XGMAC_TDES2_B1L		GENMASK(13, 0)
#define XGMAC_TDES3_OWN		BIT(31)
#define XGMAC_TDES3_CTXT		BIT(30)
#define XGMAC_TDES3_FD			BIT(29)
#define XGMAC_TDES3_LD			BIT(28)
#define XGMAC_TDES3_OSTC		BIT(27)
#define XGMAC_TDES3_CPC		GENMASK(27, 26)
#define XGMAC_TDES3_CPC_SHIFT		26
#define XGMAC_TDES3_TCMSSV		BIT(26)
#define XGMAC_TDES3_SAIC		GENMASK(25, 23)
#define XGMAC_TDES3_SAIC_SHIFT		23
#define XGMAC_TDES3_TBSV		BIT(24)
#define XGMAC_TDES3_THL		GENMASK(22, 19)
#define XGMAC_TDES3_THL_SHIFT		19
#define XGMAC_TDES3_IVTIR		GENMASK(19, 18)
#define XGMAC_TDES3_IVTIR_SHIFT	18
#define XGMAC_TDES3_TSE		BIT(18)
#define XGMAC_TDES3_IVLTV		BIT(17)
#define XGMAC_TDES3_CIC		GENMASK(17, 16)
#define XGMAC_TDES3_CIC_SHIFT		16
#define XGMAC_TDES3_TPL		GENMASK(17, 0)
#define XGMAC_TDES3_VLTV		BIT(16)
#define XGMAC_TDES3_VT			GENMASK(15, 0)
#define XGMAC_TDES3_FL			GENMASK(14, 0)
#define XGMAC_RDES2_HL			GENMASK(9, 0)
#ifdef TC956X_SRIOV_VF
#define XGMAC_RDES2_TNP			BIT(11)
#define XGMAC_RDES2_TNP_SHIFT		11
#endif
#define XGMAC_RDES3_OWN		BIT(31)
#define XGMAC_RDES3_CTXT		BIT(30)
#define XGMAC_RDES3_IOC		BIT(30)
#define XGMAC_RDES3_LD			BIT(28)
#define XGMAC_RDES3_CDA		BIT(27)
#define XGMAC_RDES3_RSV		BIT(26)
#define XGMAC_RDES3_L34T		GENMASK(23, 20)
#define XGMAC_RDES3_L34T_SHIFT		20
#ifdef TC956X_SRIOV_VF
#define XGMAC_RDES3_ETLT		GENMASK(19, 16)
#define XGMAC_RDES3_ETLT_SHIFT		16
#endif
#define XGMAC_L34T_IP4TCP		0x1
#define XGMAC_L34T_IP4UDP		0x2
#define XGMAC_L34T_IP6TCP		0x9
#define XGMAC_L34T_IP6UDP		0xA
#define XGMAC_RDES3_ES			BIT(15)
#ifdef TC956X_SRIOV_VF
#define XGMAC_RDES3_ES_SHIFT		15
#endif
#define XGMAC_RDES3_PL			GENMASK(13, 0)
#define XGMAC_RDES3_TSD		BIT(6)
#define XGMAC_RDES3_TSA		BIT(4)

#ifdef TC956X
#define XGMAC_RDES0_OVT_INDEX		0
#define XGMAC_RDES0_OVT_WIDTH		16
#define XGMAC_RDES2_VF_INDEX		15
#define XGMAC_RDES2_VF_WIDTH		1
#define XGMAC_RDES3_ES_INDEX		15
#define XGMAC_RDES3_ES_WIDTH		1
#define XGMAC_RDES3_ETLT_INDEX		16
#define XGMAC_RDES3_ETLT_WIDTH		4
#define PKT_TYPE_SINGLE_CVLAN		0x09

#define GET_BITS_LE(_var, _index, _width)				\
	((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))

#define XGMAC_GET_BITS_LE(_var, _prefix, _field)			\
	GET_BITS_LE((_var),						\
		 _prefix##_##_field##_INDEX,				\
		 _prefix##_##_field##_WIDTH)
#endif

#ifdef TC956X_SRIOV_VF
#define XGMAC_RDES3_PMT		GENMASK(3, 0)

#define XGMAC_RDES2_AVTDP		BIT(1)
#define XGMAC_RDES2_AVTCP		BIT(0)

#define XGMAC_L34T_NON_IP	0
#define XGMAC_L34T_IPV4_TCP	1
#define XGMAC_L34T_IPV4_UDP	2
#define XGMAC_L34T_IPV4_ICMP	3
#define XGMAC_L34T_IPV4_IGMP	4
#define XGMAC_L34T_IPV4_UNKNOWN	7
#define XGMAC_L34T_IPV6_TCP	9
#define XGMAC_L34T_IPV6_UDP	10
#define XGMAC_L34T_IPV6_ICMP	11
#define XGMAC_L34T_IPV6_UNKNOWN	15


#define XGMAC_ET_WD_TIMEOUT	1
#define XGMAC_ET_INV_GMII	2
#define XGMAC_ET_CRC		3
#define XGMAC_ET_GIANT_PKT	4
#define XGMAC_ET_IP_HEADER	5
#define XGMAC_ET_L4_CSUM	6
#define XGMAC_ET_OVERFLOW	7
#define XGMAC_ET_BUS		8
#define XGMAC_ET_LENGTH		9
#define XGMAC_ET_GOOD_RUNT	10
#define XGMAC_ET_DRIBBLE	12

#define XGMAC_ET_T_OUTER_IP_HEADER		5
#define XGMAC_ET_T_OUTER_HEADER_PAYLOAD_L4_CSUM	6
#define XGMAC_ET_T_INNER_IP_HEADER		9
#define XGMAC_ET_T_INNER_L4_PAYLOAD		10
#define XGMAC_ET_T_INV_VXLAN_HEADER		11

#define XGMAC_LT_LENGTH			0
#define XGMAC_LT_MAC_CONTROL		1
#define XGMAC_LT_DCB_CONTROL		2
#define XGMAC_LT_ARP_REQ		3
#define XGMAC_LT_OAM			4
#define XGMAC_LT_MAC_RX_ETH_TYPE_MATCH	5
#define XGMAC_LT_OTH_TYPE		7
#define XGMAC_LT_SVLAN			8
#define XGMAC_LT_CVLAN			9
#define XGMAC_LT_D_CVLAN_CVLAN		10
#define XGMAC_LT_D_SVLAN_SVLAN		11
#define XGMAC_LT_D_SVLAN_CVLAN		12
#define XGMAC_LT_D_CVLAN_SVLAN		13
#define XGMAC_LT_UNTAG_AV_CONTROL	6
#endif /* #ifdef TC956X_SRIOV_VF */
#endif /* __TC956XMAC_DWXGMAC2_H__ */