tx.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /****************************************************************************
  3. * Driver for Solarflare network controllers and boards
  4. * Copyright 2005-2006 Fen Systems Ltd.
  5. * Copyright 2005-2013 Solarflare Communications Inc.
  6. */
  7. #include <linux/pci.h>
  8. #include <linux/tcp.h>
  9. #include <linux/ip.h>
  10. #include <linux/in.h>
  11. #include <linux/ipv6.h>
  12. #include <linux/slab.h>
  13. #include <net/ipv6.h>
  14. #include <linux/if_ether.h>
  15. #include <linux/highmem.h>
  16. #include <linux/cache.h>
  17. #include "net_driver.h"
  18. #include "efx.h"
  19. #include "io.h"
  20. #include "nic.h"
  21. #include "tx.h"
  22. #include "tx_common.h"
  23. #include "workarounds.h"
  24. static inline u8 *efx_tx_get_copy_buffer(struct efx_tx_queue *tx_queue,
  25. struct efx_tx_buffer *buffer)
  26. {
  27. unsigned int index = efx_tx_queue_get_insert_index(tx_queue);
  28. struct efx_buffer *page_buf =
  29. &tx_queue->cb_page[index >> (PAGE_SHIFT - EFX_TX_CB_ORDER)];
  30. unsigned int offset =
  31. ((index << EFX_TX_CB_ORDER) + NET_IP_ALIGN) & (PAGE_SIZE - 1);
  32. if (unlikely(!page_buf->addr) &&
  33. efx_siena_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE,
  34. GFP_ATOMIC))
  35. return NULL;
  36. buffer->dma_addr = page_buf->dma_addr + offset;
  37. buffer->unmap_len = 0;
  38. return (u8 *)page_buf->addr + offset;
  39. }
  40. static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1)
  41. {
  42. /* We need to consider all queues that the net core sees as one */
  43. struct efx_nic *efx = txq1->efx;
  44. struct efx_tx_queue *txq2;
  45. unsigned int fill_level;
  46. fill_level = efx_channel_tx_old_fill_level(txq1->channel);
  47. if (likely(fill_level < efx->txq_stop_thresh))
  48. return;
  49. /* We used the stale old_read_count above, which gives us a
  50. * pessimistic estimate of the fill level (which may even
  51. * validly be >= efx->txq_entries). Now try again using
  52. * read_count (more likely to be a cache miss).
  53. *
  54. * If we read read_count and then conditionally stop the
  55. * queue, it is possible for the completion path to race with
  56. * us and complete all outstanding descriptors in the middle,
  57. * after which there will be no more completions to wake it.
  58. * Therefore we stop the queue first, then read read_count
  59. * (with a memory barrier to ensure the ordering), then
  60. * restart the queue if the fill level turns out to be low
  61. * enough.
  62. */
  63. netif_tx_stop_queue(txq1->core_txq);
  64. smp_mb();
  65. efx_for_each_channel_tx_queue(txq2, txq1->channel)
  66. txq2->old_read_count = READ_ONCE(txq2->read_count);
  67. fill_level = efx_channel_tx_old_fill_level(txq1->channel);
  68. EFX_WARN_ON_ONCE_PARANOID(fill_level >= efx->txq_entries);
  69. if (likely(fill_level < efx->txq_stop_thresh)) {
  70. smp_mb();
  71. if (likely(!efx->loopback_selftest))
  72. netif_tx_start_queue(txq1->core_txq);
  73. }
  74. }
  75. static int efx_enqueue_skb_copy(struct efx_tx_queue *tx_queue,
  76. struct sk_buff *skb)
  77. {
  78. unsigned int copy_len = skb->len;
  79. struct efx_tx_buffer *buffer;
  80. u8 *copy_buffer;
  81. int rc;
  82. EFX_WARN_ON_ONCE_PARANOID(copy_len > EFX_TX_CB_SIZE);
  83. buffer = efx_tx_queue_get_insert_buffer(tx_queue);
  84. copy_buffer = efx_tx_get_copy_buffer(tx_queue, buffer);
  85. if (unlikely(!copy_buffer))
  86. return -ENOMEM;
  87. rc = skb_copy_bits(skb, 0, copy_buffer, copy_len);
  88. EFX_WARN_ON_PARANOID(rc);
  89. buffer->len = copy_len;
  90. buffer->skb = skb;
  91. buffer->flags = EFX_TX_BUF_SKB;
  92. ++tx_queue->insert_count;
  93. return rc;
  94. }
  95. /* Send any pending traffic for a channel. xmit_more is shared across all
  96. * queues for a channel, so we must check all of them.
  97. */
  98. static void efx_tx_send_pending(struct efx_channel *channel)
  99. {
  100. struct efx_tx_queue *q;
  101. efx_for_each_channel_tx_queue(q, channel) {
  102. if (q->xmit_pending)
  103. efx_nic_push_buffers(q);
  104. }
  105. }
  106. /*
  107. * Add a socket buffer to a TX queue
  108. *
  109. * This maps all fragments of a socket buffer for DMA and adds them to
  110. * the TX queue. The queue's insert pointer will be incremented by
  111. * the number of fragments in the socket buffer.
  112. *
  113. * If any DMA mapping fails, any mapped fragments will be unmapped,
  114. * the queue's insert pointer will be restored to its original value.
  115. *
  116. * This function is split out from efx_siena_hard_start_xmit to allow the
  117. * loopback test to direct packets via specific TX queues.
  118. *
  119. * Returns NETDEV_TX_OK.
  120. * You must hold netif_tx_lock() to call this function.
  121. */
  122. netdev_tx_t __efx_siena_enqueue_skb(struct efx_tx_queue *tx_queue,
  123. struct sk_buff *skb)
  124. {
  125. unsigned int old_insert_count = tx_queue->insert_count;
  126. bool xmit_more = netdev_xmit_more();
  127. bool data_mapped = false;
  128. unsigned int segments;
  129. unsigned int skb_len;
  130. int rc;
  131. skb_len = skb->len;
  132. segments = skb_is_gso(skb) ? skb_shinfo(skb)->gso_segs : 0;
  133. if (segments == 1)
  134. segments = 0; /* Don't use TSO for a single segment. */
  135. /* Handle TSO first - it's *possible* (although unlikely) that we might
  136. * be passed a packet to segment that's smaller than the copybreak/PIO
  137. * size limit.
  138. */
  139. if (segments) {
  140. rc = efx_siena_tx_tso_fallback(tx_queue, skb);
  141. tx_queue->tso_fallbacks++;
  142. if (rc == 0)
  143. return 0;
  144. goto err;
  145. } else if (skb->data_len && skb_len <= EFX_TX_CB_SIZE) {
  146. /* Pad short packets or coalesce short fragmented packets. */
  147. if (efx_enqueue_skb_copy(tx_queue, skb))
  148. goto err;
  149. tx_queue->cb_packets++;
  150. data_mapped = true;
  151. }
  152. /* Map for DMA and create descriptors if we haven't done so already. */
  153. if (!data_mapped && (efx_siena_tx_map_data(tx_queue, skb, segments)))
  154. goto err;
  155. efx_tx_maybe_stop_queue(tx_queue);
  156. tx_queue->xmit_pending = true;
  157. /* Pass off to hardware */
  158. if (__netdev_tx_sent_queue(tx_queue->core_txq, skb_len, xmit_more))
  159. efx_tx_send_pending(tx_queue->channel);
  160. tx_queue->tx_packets++;
  161. return NETDEV_TX_OK;
  162. err:
  163. efx_siena_enqueue_unwind(tx_queue, old_insert_count);
  164. dev_kfree_skb_any(skb);
  165. /* If we're not expecting another transmit and we had something to push
  166. * on this queue or a partner queue then we need to push here to get the
  167. * previous packets out.
  168. */
  169. if (!xmit_more)
  170. efx_tx_send_pending(tx_queue->channel);
  171. return NETDEV_TX_OK;
  172. }
  173. /* Transmit a packet from an XDP buffer
  174. *
  175. * Returns number of packets sent on success, error code otherwise.
  176. * Runs in NAPI context, either in our poll (for XDP TX) or a different NIC
  177. * (for XDP redirect).
  178. */
  179. int efx_siena_xdp_tx_buffers(struct efx_nic *efx, int n, struct xdp_frame **xdpfs,
  180. bool flush)
  181. {
  182. struct efx_tx_buffer *tx_buffer;
  183. struct efx_tx_queue *tx_queue;
  184. struct xdp_frame *xdpf;
  185. dma_addr_t dma_addr;
  186. unsigned int len;
  187. int space;
  188. int cpu;
  189. int i = 0;
  190. if (unlikely(n && !xdpfs))
  191. return -EINVAL;
  192. if (unlikely(!n))
  193. return 0;
  194. cpu = raw_smp_processor_id();
  195. if (unlikely(cpu >= efx->xdp_tx_queue_count))
  196. return -EINVAL;
  197. tx_queue = efx->xdp_tx_queues[cpu];
  198. if (unlikely(!tx_queue))
  199. return -EINVAL;
  200. if (!tx_queue->initialised)
  201. return -EINVAL;
  202. if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED)
  203. HARD_TX_LOCK(efx->net_dev, tx_queue->core_txq, cpu);
  204. /* If we're borrowing net stack queues we have to handle stop-restart
  205. * or we might block the queue and it will be considered as frozen
  206. */
  207. if (efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_BORROWED) {
  208. if (netif_tx_queue_stopped(tx_queue->core_txq))
  209. goto unlock;
  210. efx_tx_maybe_stop_queue(tx_queue);
  211. }
  212. /* Check for available space. We should never need multiple
  213. * descriptors per frame.
  214. */
  215. space = efx->txq_entries +
  216. tx_queue->read_count - tx_queue->insert_count;
  217. for (i = 0; i < n; i++) {
  218. xdpf = xdpfs[i];
  219. if (i >= space)
  220. break;
  221. /* We'll want a descriptor for this tx. */
  222. prefetchw(__efx_tx_queue_get_insert_buffer(tx_queue));
  223. len = xdpf->len;
  224. /* Map for DMA. */
  225. dma_addr = dma_map_single(&efx->pci_dev->dev,
  226. xdpf->data, len,
  227. DMA_TO_DEVICE);
  228. if (dma_mapping_error(&efx->pci_dev->dev, dma_addr))
  229. break;
  230. /* Create descriptor and set up for unmapping DMA. */
  231. tx_buffer = efx_siena_tx_map_chunk(tx_queue, dma_addr, len);
  232. tx_buffer->xdpf = xdpf;
  233. tx_buffer->flags = EFX_TX_BUF_XDP |
  234. EFX_TX_BUF_MAP_SINGLE;
  235. tx_buffer->dma_offset = 0;
  236. tx_buffer->unmap_len = len;
  237. tx_queue->tx_packets++;
  238. }
  239. /* Pass mapped frames to hardware. */
  240. if (flush && i > 0)
  241. efx_nic_push_buffers(tx_queue);
  242. unlock:
  243. if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED)
  244. HARD_TX_UNLOCK(efx->net_dev, tx_queue->core_txq);
  245. return i == 0 ? -EIO : i;
  246. }
  247. /* Initiate a packet transmission. We use one channel per CPU
  248. * (sharing when we have more CPUs than channels).
  249. *
  250. * Context: non-blocking.
  251. * Should always return NETDEV_TX_OK and consume the skb.
  252. */
  253. netdev_tx_t efx_siena_hard_start_xmit(struct sk_buff *skb,
  254. struct net_device *net_dev)
  255. {
  256. struct efx_nic *efx = netdev_priv(net_dev);
  257. struct efx_tx_queue *tx_queue;
  258. unsigned index, type;
  259. EFX_WARN_ON_PARANOID(!netif_device_present(net_dev));
  260. index = skb_get_queue_mapping(skb);
  261. type = efx_tx_csum_type_skb(skb);
  262. if (index >= efx->n_tx_channels) {
  263. index -= efx->n_tx_channels;
  264. type |= EFX_TXQ_TYPE_HIGHPRI;
  265. }
  266. /* PTP "event" packet */
  267. if (unlikely(efx_xmit_with_hwtstamp(skb)) &&
  268. ((efx_siena_ptp_use_mac_tx_timestamps(efx) && efx->ptp_data) ||
  269. unlikely(efx_siena_ptp_is_ptp_tx(efx, skb)))) {
  270. /* There may be existing transmits on the channel that are
  271. * waiting for this packet to trigger the doorbell write.
  272. * We need to send the packets at this point.
  273. */
  274. efx_tx_send_pending(efx_get_tx_channel(efx, index));
  275. return efx_siena_ptp_tx(efx, skb);
  276. }
  277. tx_queue = efx_get_tx_queue(efx, index, type);
  278. if (WARN_ON_ONCE(!tx_queue)) {
  279. /* We don't have a TXQ of the right type.
  280. * This should never happen, as we don't advertise offload
  281. * features unless we can support them.
  282. */
  283. dev_kfree_skb_any(skb);
  284. /* If we're not expecting another transmit and we had something to push
  285. * on this queue or a partner queue then we need to push here to get the
  286. * previous packets out.
  287. */
  288. if (!netdev_xmit_more())
  289. efx_tx_send_pending(efx_get_tx_channel(efx, index));
  290. return NETDEV_TX_OK;
  291. }
  292. return __efx_siena_enqueue_skb(tx_queue, skb);
  293. }
  294. void efx_siena_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
  295. {
  296. struct efx_nic *efx = tx_queue->efx;
  297. /* Must be inverse of queue lookup in efx_siena_hard_start_xmit() */
  298. tx_queue->core_txq =
  299. netdev_get_tx_queue(efx->net_dev,
  300. tx_queue->channel->channel +
  301. ((tx_queue->type & EFX_TXQ_TYPE_HIGHPRI) ?
  302. efx->n_tx_channels : 0));
  303. }
  304. int efx_siena_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
  305. void *type_data)
  306. {
  307. struct efx_nic *efx = netdev_priv(net_dev);
  308. struct tc_mqprio_qopt *mqprio = type_data;
  309. unsigned tc, num_tc;
  310. if (type != TC_SETUP_QDISC_MQPRIO)
  311. return -EOPNOTSUPP;
  312. /* Only Siena supported highpri queues */
  313. if (efx_nic_rev(efx) > EFX_REV_SIENA_A0)
  314. return -EOPNOTSUPP;
  315. num_tc = mqprio->num_tc;
  316. if (num_tc > EFX_MAX_TX_TC)
  317. return -EINVAL;
  318. mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
  319. if (num_tc == net_dev->num_tc)
  320. return 0;
  321. for (tc = 0; tc < num_tc; tc++) {
  322. net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
  323. net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
  324. }
  325. net_dev->num_tc = num_tc;
  326. return netif_set_real_num_tx_queues(net_dev,
  327. max_t(int, num_tc, 1) *
  328. efx->n_tx_channels);
  329. }