io.h 10.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /****************************************************************************
  3. * Driver for Solarflare network controllers and boards
  4. * Copyright 2005-2006 Fen Systems Ltd.
  5. * Copyright 2006-2013 Solarflare Communications Inc.
  6. */
  7. #ifndef EFX_IO_H
  8. #define EFX_IO_H
  9. #include <linux/io.h>
  10. #include <linux/spinlock.h>
  11. /**************************************************************************
  12. *
  13. * NIC register I/O
  14. *
  15. **************************************************************************
  16. *
  17. * Notes on locking strategy for the Falcon architecture:
  18. *
  19. * Many CSRs are very wide and cannot be read or written atomically.
  20. * Writes from the host are buffered by the Bus Interface Unit (BIU)
  21. * up to 128 bits. Whenever the host writes part of such a register,
  22. * the BIU collects the written value and does not write to the
  23. * underlying register until all 4 dwords have been written. A
  24. * similar buffering scheme applies to host access to the NIC's 64-bit
  25. * SRAM.
  26. *
  27. * Writes to different CSRs and 64-bit SRAM words must be serialised,
  28. * since interleaved access can result in lost writes. We use
  29. * efx_nic::biu_lock for this.
  30. *
  31. * We also serialise reads from 128-bit CSRs and SRAM with the same
  32. * spinlock. This may not be necessary, but it doesn't really matter
  33. * as there are no such reads on the fast path.
  34. *
  35. * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
  36. * 128-bit but are special-cased in the BIU to avoid the need for
  37. * locking in the host:
  38. *
  39. * - They are write-only.
  40. * - The semantics of writing to these registers are such that
  41. * replacing the low 96 bits with zero does not affect functionality.
  42. * - If the host writes to the last dword address of such a register
  43. * (i.e. the high 32 bits) the underlying register will always be
  44. * written. If the collector and the current write together do not
  45. * provide values for all 128 bits of the register, the low 96 bits
  46. * will be written as zero.
  47. * - If the host writes to the address of any other part of such a
  48. * register while the collector already holds values for some other
  49. * register, the write is discarded and the collector maintains its
  50. * current state.
  51. *
  52. * The EF10 architecture exposes very few registers to the host and
  53. * most of them are only 32 bits wide. The only exceptions are the MC
  54. * doorbell register pair, which has its own latching, and
  55. * TX_DESC_UPD, which works in a similar way to the Falcon
  56. * architecture.
  57. */
  58. #if BITS_PER_LONG == 64
  59. #define EFX_USE_QWORD_IO 1
  60. #endif
  61. /* Hardware issue requires that only 64-bit naturally aligned writes
  62. * are seen by hardware. Its not strictly necessary to restrict to
  63. * x86_64 arch, but done for safety since unusual write combining behaviour
  64. * can break PIO.
  65. */
  66. #ifdef CONFIG_X86_64
  67. /* PIO is a win only if write-combining is possible */
  68. #ifdef ARCH_HAS_IOREMAP_WC
  69. #define EFX_USE_PIO 1
  70. #endif
  71. #endif
  72. static inline u32 efx_reg(struct efx_nic *efx, unsigned int reg)
  73. {
  74. return efx->reg_base + reg;
  75. }
  76. #ifdef EFX_USE_QWORD_IO
  77. static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
  78. unsigned int reg)
  79. {
  80. __raw_writeq((__force u64)value, efx->membase + reg);
  81. }
  82. static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
  83. {
  84. return (__force __le64)__raw_readq(efx->membase + reg);
  85. }
  86. #endif
  87. static inline void _efx_writed(struct efx_nic *efx, __le32 value,
  88. unsigned int reg)
  89. {
  90. __raw_writel((__force u32)value, efx->membase + reg);
  91. }
  92. static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
  93. {
  94. return (__force __le32)__raw_readl(efx->membase + reg);
  95. }
  96. /* Write a normal 128-bit CSR, locking as appropriate. */
  97. static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value,
  98. unsigned int reg)
  99. {
  100. unsigned long flags __attribute__ ((unused));
  101. netif_vdbg(efx, hw, efx->net_dev,
  102. "writing register %x with " EFX_OWORD_FMT "\n", reg,
  103. EFX_OWORD_VAL(*value));
  104. spin_lock_irqsave(&efx->biu_lock, flags);
  105. #ifdef EFX_USE_QWORD_IO
  106. _efx_writeq(efx, value->u64[0], reg + 0);
  107. _efx_writeq(efx, value->u64[1], reg + 8);
  108. #else
  109. _efx_writed(efx, value->u32[0], reg + 0);
  110. _efx_writed(efx, value->u32[1], reg + 4);
  111. _efx_writed(efx, value->u32[2], reg + 8);
  112. _efx_writed(efx, value->u32[3], reg + 12);
  113. #endif
  114. spin_unlock_irqrestore(&efx->biu_lock, flags);
  115. }
  116. /* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
  117. static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
  118. const efx_qword_t *value, unsigned int index)
  119. {
  120. unsigned int addr = index * sizeof(*value);
  121. unsigned long flags __attribute__ ((unused));
  122. netif_vdbg(efx, hw, efx->net_dev,
  123. "writing SRAM address %x with " EFX_QWORD_FMT "\n",
  124. addr, EFX_QWORD_VAL(*value));
  125. spin_lock_irqsave(&efx->biu_lock, flags);
  126. #ifdef EFX_USE_QWORD_IO
  127. __raw_writeq((__force u64)value->u64[0], membase + addr);
  128. #else
  129. __raw_writel((__force u32)value->u32[0], membase + addr);
  130. __raw_writel((__force u32)value->u32[1], membase + addr + 4);
  131. #endif
  132. spin_unlock_irqrestore(&efx->biu_lock, flags);
  133. }
  134. /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
  135. static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value,
  136. unsigned int reg)
  137. {
  138. netif_vdbg(efx, hw, efx->net_dev,
  139. "writing register %x with "EFX_DWORD_FMT"\n",
  140. reg, EFX_DWORD_VAL(*value));
  141. /* No lock required */
  142. _efx_writed(efx, value->u32[0], reg);
  143. }
  144. /* Read a 128-bit CSR, locking as appropriate. */
  145. static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
  146. unsigned int reg)
  147. {
  148. unsigned long flags __attribute__ ((unused));
  149. spin_lock_irqsave(&efx->biu_lock, flags);
  150. value->u32[0] = _efx_readd(efx, reg + 0);
  151. value->u32[1] = _efx_readd(efx, reg + 4);
  152. value->u32[2] = _efx_readd(efx, reg + 8);
  153. value->u32[3] = _efx_readd(efx, reg + 12);
  154. spin_unlock_irqrestore(&efx->biu_lock, flags);
  155. netif_vdbg(efx, hw, efx->net_dev,
  156. "read from register %x, got " EFX_OWORD_FMT "\n", reg,
  157. EFX_OWORD_VAL(*value));
  158. }
  159. /* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
  160. static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
  161. efx_qword_t *value, unsigned int index)
  162. {
  163. unsigned int addr = index * sizeof(*value);
  164. unsigned long flags __attribute__ ((unused));
  165. spin_lock_irqsave(&efx->biu_lock, flags);
  166. #ifdef EFX_USE_QWORD_IO
  167. value->u64[0] = (__force __le64)__raw_readq(membase + addr);
  168. #else
  169. value->u32[0] = (__force __le32)__raw_readl(membase + addr);
  170. value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
  171. #endif
  172. spin_unlock_irqrestore(&efx->biu_lock, flags);
  173. netif_vdbg(efx, hw, efx->net_dev,
  174. "read from SRAM address %x, got "EFX_QWORD_FMT"\n",
  175. addr, EFX_QWORD_VAL(*value));
  176. }
  177. /* Read a 32-bit CSR or SRAM */
  178. static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
  179. unsigned int reg)
  180. {
  181. value->u32[0] = _efx_readd(efx, reg);
  182. netif_vdbg(efx, hw, efx->net_dev,
  183. "read from register %x, got "EFX_DWORD_FMT"\n",
  184. reg, EFX_DWORD_VAL(*value));
  185. }
  186. /* Write a 128-bit CSR forming part of a table */
  187. static inline void
  188. efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value,
  189. unsigned int reg, unsigned int index)
  190. {
  191. efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
  192. }
  193. /* Read a 128-bit CSR forming part of a table */
  194. static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
  195. unsigned int reg, unsigned int index)
  196. {
  197. efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
  198. }
  199. /* default VI stride (step between per-VI registers) is 8K on EF10 and
  200. * 64K on EF100
  201. */
  202. #define EFX_DEFAULT_VI_STRIDE 0x2000
  203. #define EF100_DEFAULT_VI_STRIDE 0x10000
  204. /* Calculate offset to page-mapped register */
  205. static inline unsigned int efx_paged_reg(struct efx_nic *efx, unsigned int page,
  206. unsigned int reg)
  207. {
  208. return page * efx->vi_stride + reg;
  209. }
  210. /* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
  211. static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
  212. unsigned int reg, unsigned int page)
  213. {
  214. reg = efx_paged_reg(efx, page, reg);
  215. netif_vdbg(efx, hw, efx->net_dev,
  216. "writing register %x with " EFX_OWORD_FMT "\n", reg,
  217. EFX_OWORD_VAL(*value));
  218. #ifdef EFX_USE_QWORD_IO
  219. _efx_writeq(efx, value->u64[0], reg + 0);
  220. _efx_writeq(efx, value->u64[1], reg + 8);
  221. #else
  222. _efx_writed(efx, value->u32[0], reg + 0);
  223. _efx_writed(efx, value->u32[1], reg + 4);
  224. _efx_writed(efx, value->u32[2], reg + 8);
  225. _efx_writed(efx, value->u32[3], reg + 12);
  226. #endif
  227. }
  228. #define efx_writeo_page(efx, value, reg, page) \
  229. _efx_writeo_page(efx, value, \
  230. reg + \
  231. BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
  232. page)
  233. /* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
  234. * high bits of RX_DESC_UPD or TX_DESC_UPD)
  235. */
  236. static inline void
  237. _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value,
  238. unsigned int reg, unsigned int page)
  239. {
  240. efx_writed(efx, value, efx_paged_reg(efx, page, reg));
  241. }
  242. #define efx_writed_page(efx, value, reg, page) \
  243. _efx_writed_page(efx, value, \
  244. reg + \
  245. BUILD_BUG_ON_ZERO((reg) != 0x180 && \
  246. (reg) != 0x200 && \
  247. (reg) != 0x400 && \
  248. (reg) != 0x420 && \
  249. (reg) != 0x830 && \
  250. (reg) != 0x83c && \
  251. (reg) != 0xa18 && \
  252. (reg) != 0xa1c), \
  253. page)
  254. /* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
  255. * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
  256. * collector register.
  257. */
  258. static inline void _efx_writed_page_locked(struct efx_nic *efx,
  259. const efx_dword_t *value,
  260. unsigned int reg,
  261. unsigned int page)
  262. {
  263. unsigned long flags __attribute__ ((unused));
  264. if (page == 0) {
  265. spin_lock_irqsave(&efx->biu_lock, flags);
  266. efx_writed(efx, value, efx_paged_reg(efx, page, reg));
  267. spin_unlock_irqrestore(&efx->biu_lock, flags);
  268. } else {
  269. efx_writed(efx, value, efx_paged_reg(efx, page, reg));
  270. }
  271. }
  272. #define efx_writed_page_locked(efx, value, reg, page) \
  273. _efx_writed_page_locked(efx, value, \
  274. reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
  275. page)
  276. #endif /* EFX_IO_H */