rx.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /****************************************************************************
  3. * Driver for Solarflare network controllers and boards
  4. * Copyright 2005-2006 Fen Systems Ltd.
  5. * Copyright 2005-2013 Solarflare Communications Inc.
  6. */
  7. #include <linux/socket.h>
  8. #include <linux/in.h>
  9. #include <linux/slab.h>
  10. #include <linux/ip.h>
  11. #include <linux/ipv6.h>
  12. #include <linux/tcp.h>
  13. #include <linux/udp.h>
  14. #include <linux/prefetch.h>
  15. #include <linux/moduleparam.h>
  16. #include <linux/iommu.h>
  17. #include <net/ip.h>
  18. #include <net/checksum.h>
  19. #include "net_driver.h"
  20. #include "efx.h"
  21. #include "filter.h"
  22. #include "nic.h"
  23. #include "selftest.h"
  24. #include "workarounds.h"
  25. /* Preferred number of descriptors to fill at once */
  26. #define EF4_RX_PREFERRED_BATCH 8U
  27. /* Number of RX buffers to recycle pages for. When creating the RX page recycle
  28. * ring, this number is divided by the number of buffers per page to calculate
  29. * the number of pages to store in the RX page recycle ring.
  30. */
  31. #define EF4_RECYCLE_RING_SIZE_IOMMU 4096
  32. #define EF4_RECYCLE_RING_SIZE_NOIOMMU (2 * EF4_RX_PREFERRED_BATCH)
  33. /* Size of buffer allocated for skb header area. */
  34. #define EF4_SKB_HEADERS 128u
  35. /* This is the percentage fill level below which new RX descriptors
  36. * will be added to the RX descriptor ring.
  37. */
  38. static unsigned int rx_refill_threshold;
  39. /* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */
  40. #define EF4_RX_MAX_FRAGS DIV_ROUND_UP(EF4_MAX_FRAME_LEN(EF4_MAX_MTU), \
  41. EF4_RX_USR_BUF_SIZE)
  42. /*
  43. * RX maximum head room required.
  44. *
  45. * This must be at least 1 to prevent overflow, plus one packet-worth
  46. * to allow pipelined receives.
  47. */
  48. #define EF4_RXD_HEAD_ROOM (1 + EF4_RX_MAX_FRAGS)
  49. static inline u8 *ef4_rx_buf_va(struct ef4_rx_buffer *buf)
  50. {
  51. return page_address(buf->page) + buf->page_offset;
  52. }
  53. static inline u32 ef4_rx_buf_hash(struct ef4_nic *efx, const u8 *eh)
  54. {
  55. #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
  56. return __le32_to_cpup((const __le32 *)(eh + efx->rx_packet_hash_offset));
  57. #else
  58. const u8 *data = eh + efx->rx_packet_hash_offset;
  59. return (u32)data[0] |
  60. (u32)data[1] << 8 |
  61. (u32)data[2] << 16 |
  62. (u32)data[3] << 24;
  63. #endif
  64. }
  65. static inline struct ef4_rx_buffer *
  66. ef4_rx_buf_next(struct ef4_rx_queue *rx_queue, struct ef4_rx_buffer *rx_buf)
  67. {
  68. if (unlikely(rx_buf == ef4_rx_buffer(rx_queue, rx_queue->ptr_mask)))
  69. return ef4_rx_buffer(rx_queue, 0);
  70. else
  71. return rx_buf + 1;
  72. }
  73. static inline void ef4_sync_rx_buffer(struct ef4_nic *efx,
  74. struct ef4_rx_buffer *rx_buf,
  75. unsigned int len)
  76. {
  77. dma_sync_single_for_cpu(&efx->pci_dev->dev, rx_buf->dma_addr, len,
  78. DMA_FROM_DEVICE);
  79. }
  80. void ef4_rx_config_page_split(struct ef4_nic *efx)
  81. {
  82. efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + efx->rx_ip_align,
  83. EF4_RX_BUF_ALIGNMENT);
  84. efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 :
  85. ((PAGE_SIZE - sizeof(struct ef4_rx_page_state)) /
  86. efx->rx_page_buf_step);
  87. efx->rx_buffer_truesize = (PAGE_SIZE << efx->rx_buffer_order) /
  88. efx->rx_bufs_per_page;
  89. efx->rx_pages_per_batch = DIV_ROUND_UP(EF4_RX_PREFERRED_BATCH,
  90. efx->rx_bufs_per_page);
  91. }
  92. /* Check the RX page recycle ring for a page that can be reused. */
  93. static struct page *ef4_reuse_page(struct ef4_rx_queue *rx_queue)
  94. {
  95. struct ef4_nic *efx = rx_queue->efx;
  96. struct page *page;
  97. struct ef4_rx_page_state *state;
  98. unsigned index;
  99. if (unlikely(!rx_queue->page_ring))
  100. return NULL;
  101. index = rx_queue->page_remove & rx_queue->page_ptr_mask;
  102. page = rx_queue->page_ring[index];
  103. if (page == NULL)
  104. return NULL;
  105. rx_queue->page_ring[index] = NULL;
  106. /* page_remove cannot exceed page_add. */
  107. if (rx_queue->page_remove != rx_queue->page_add)
  108. ++rx_queue->page_remove;
  109. /* If page_count is 1 then we hold the only reference to this page. */
  110. if (page_count(page) == 1) {
  111. ++rx_queue->page_recycle_count;
  112. return page;
  113. } else {
  114. state = page_address(page);
  115. dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
  116. PAGE_SIZE << efx->rx_buffer_order,
  117. DMA_FROM_DEVICE);
  118. put_page(page);
  119. ++rx_queue->page_recycle_failed;
  120. }
  121. return NULL;
  122. }
  123. /**
  124. * ef4_init_rx_buffers - create EF4_RX_BATCH page-based RX buffers
  125. *
  126. * @rx_queue: Efx RX queue
  127. * @atomic: control memory allocation flags
  128. *
  129. * This allocates a batch of pages, maps them for DMA, and populates
  130. * struct ef4_rx_buffers for each one. Return a negative error code or
  131. * 0 on success. If a single page can be used for multiple buffers,
  132. * then the page will either be inserted fully, or not at all.
  133. */
  134. static int ef4_init_rx_buffers(struct ef4_rx_queue *rx_queue, bool atomic)
  135. {
  136. struct ef4_nic *efx = rx_queue->efx;
  137. struct ef4_rx_buffer *rx_buf;
  138. struct page *page;
  139. unsigned int page_offset;
  140. struct ef4_rx_page_state *state;
  141. dma_addr_t dma_addr;
  142. unsigned index, count;
  143. count = 0;
  144. do {
  145. page = ef4_reuse_page(rx_queue);
  146. if (page == NULL) {
  147. page = alloc_pages(__GFP_COMP |
  148. (atomic ? GFP_ATOMIC : GFP_KERNEL),
  149. efx->rx_buffer_order);
  150. if (unlikely(page == NULL))
  151. return -ENOMEM;
  152. dma_addr =
  153. dma_map_page(&efx->pci_dev->dev, page, 0,
  154. PAGE_SIZE << efx->rx_buffer_order,
  155. DMA_FROM_DEVICE);
  156. if (unlikely(dma_mapping_error(&efx->pci_dev->dev,
  157. dma_addr))) {
  158. __free_pages(page, efx->rx_buffer_order);
  159. return -EIO;
  160. }
  161. state = page_address(page);
  162. state->dma_addr = dma_addr;
  163. } else {
  164. state = page_address(page);
  165. dma_addr = state->dma_addr;
  166. }
  167. dma_addr += sizeof(struct ef4_rx_page_state);
  168. page_offset = sizeof(struct ef4_rx_page_state);
  169. do {
  170. index = rx_queue->added_count & rx_queue->ptr_mask;
  171. rx_buf = ef4_rx_buffer(rx_queue, index);
  172. rx_buf->dma_addr = dma_addr + efx->rx_ip_align;
  173. rx_buf->page = page;
  174. rx_buf->page_offset = page_offset + efx->rx_ip_align;
  175. rx_buf->len = efx->rx_dma_len;
  176. rx_buf->flags = 0;
  177. ++rx_queue->added_count;
  178. get_page(page);
  179. dma_addr += efx->rx_page_buf_step;
  180. page_offset += efx->rx_page_buf_step;
  181. } while (page_offset + efx->rx_page_buf_step <= PAGE_SIZE);
  182. rx_buf->flags = EF4_RX_BUF_LAST_IN_PAGE;
  183. } while (++count < efx->rx_pages_per_batch);
  184. return 0;
  185. }
  186. /* Unmap a DMA-mapped page. This function is only called for the final RX
  187. * buffer in a page.
  188. */
  189. static void ef4_unmap_rx_buffer(struct ef4_nic *efx,
  190. struct ef4_rx_buffer *rx_buf)
  191. {
  192. struct page *page = rx_buf->page;
  193. if (page) {
  194. struct ef4_rx_page_state *state = page_address(page);
  195. dma_unmap_page(&efx->pci_dev->dev,
  196. state->dma_addr,
  197. PAGE_SIZE << efx->rx_buffer_order,
  198. DMA_FROM_DEVICE);
  199. }
  200. }
  201. static void ef4_free_rx_buffers(struct ef4_rx_queue *rx_queue,
  202. struct ef4_rx_buffer *rx_buf,
  203. unsigned int num_bufs)
  204. {
  205. do {
  206. if (rx_buf->page) {
  207. put_page(rx_buf->page);
  208. rx_buf->page = NULL;
  209. }
  210. rx_buf = ef4_rx_buf_next(rx_queue, rx_buf);
  211. } while (--num_bufs);
  212. }
  213. /* Attempt to recycle the page if there is an RX recycle ring; the page can
  214. * only be added if this is the final RX buffer, to prevent pages being used in
  215. * the descriptor ring and appearing in the recycle ring simultaneously.
  216. */
  217. static void ef4_recycle_rx_page(struct ef4_channel *channel,
  218. struct ef4_rx_buffer *rx_buf)
  219. {
  220. struct page *page = rx_buf->page;
  221. struct ef4_rx_queue *rx_queue = ef4_channel_get_rx_queue(channel);
  222. struct ef4_nic *efx = rx_queue->efx;
  223. unsigned index;
  224. /* Only recycle the page after processing the final buffer. */
  225. if (!(rx_buf->flags & EF4_RX_BUF_LAST_IN_PAGE))
  226. return;
  227. index = rx_queue->page_add & rx_queue->page_ptr_mask;
  228. if (rx_queue->page_ring[index] == NULL) {
  229. unsigned read_index = rx_queue->page_remove &
  230. rx_queue->page_ptr_mask;
  231. /* The next slot in the recycle ring is available, but
  232. * increment page_remove if the read pointer currently
  233. * points here.
  234. */
  235. if (read_index == index)
  236. ++rx_queue->page_remove;
  237. rx_queue->page_ring[index] = page;
  238. ++rx_queue->page_add;
  239. return;
  240. }
  241. ++rx_queue->page_recycle_full;
  242. ef4_unmap_rx_buffer(efx, rx_buf);
  243. put_page(rx_buf->page);
  244. }
  245. static void ef4_fini_rx_buffer(struct ef4_rx_queue *rx_queue,
  246. struct ef4_rx_buffer *rx_buf)
  247. {
  248. /* Release the page reference we hold for the buffer. */
  249. if (rx_buf->page)
  250. put_page(rx_buf->page);
  251. /* If this is the last buffer in a page, unmap and free it. */
  252. if (rx_buf->flags & EF4_RX_BUF_LAST_IN_PAGE) {
  253. ef4_unmap_rx_buffer(rx_queue->efx, rx_buf);
  254. ef4_free_rx_buffers(rx_queue, rx_buf, 1);
  255. }
  256. rx_buf->page = NULL;
  257. }
  258. /* Recycle the pages that are used by buffers that have just been received. */
  259. static void ef4_recycle_rx_pages(struct ef4_channel *channel,
  260. struct ef4_rx_buffer *rx_buf,
  261. unsigned int n_frags)
  262. {
  263. struct ef4_rx_queue *rx_queue = ef4_channel_get_rx_queue(channel);
  264. if (unlikely(!rx_queue->page_ring))
  265. return;
  266. do {
  267. ef4_recycle_rx_page(channel, rx_buf);
  268. rx_buf = ef4_rx_buf_next(rx_queue, rx_buf);
  269. } while (--n_frags);
  270. }
  271. static void ef4_discard_rx_packet(struct ef4_channel *channel,
  272. struct ef4_rx_buffer *rx_buf,
  273. unsigned int n_frags)
  274. {
  275. struct ef4_rx_queue *rx_queue = ef4_channel_get_rx_queue(channel);
  276. ef4_recycle_rx_pages(channel, rx_buf, n_frags);
  277. ef4_free_rx_buffers(rx_queue, rx_buf, n_frags);
  278. }
  279. /**
  280. * ef4_fast_push_rx_descriptors - push new RX descriptors quickly
  281. * @rx_queue: RX descriptor queue
  282. *
  283. * This will aim to fill the RX descriptor queue up to
  284. * @rx_queue->@max_fill. If there is insufficient atomic
  285. * memory to do so, a slow fill will be scheduled.
  286. * @atomic: control memory allocation flags
  287. *
  288. * The caller must provide serialisation (none is used here). In practise,
  289. * this means this function must run from the NAPI handler, or be called
  290. * when NAPI is disabled.
  291. */
  292. void ef4_fast_push_rx_descriptors(struct ef4_rx_queue *rx_queue, bool atomic)
  293. {
  294. struct ef4_nic *efx = rx_queue->efx;
  295. unsigned int fill_level, batch_size;
  296. int space, rc = 0;
  297. if (!rx_queue->refill_enabled)
  298. return;
  299. /* Calculate current fill level, and exit if we don't need to fill */
  300. fill_level = (rx_queue->added_count - rx_queue->removed_count);
  301. EF4_BUG_ON_PARANOID(fill_level > rx_queue->efx->rxq_entries);
  302. if (fill_level >= rx_queue->fast_fill_trigger)
  303. goto out;
  304. /* Record minimum fill level */
  305. if (unlikely(fill_level < rx_queue->min_fill)) {
  306. if (fill_level)
  307. rx_queue->min_fill = fill_level;
  308. }
  309. batch_size = efx->rx_pages_per_batch * efx->rx_bufs_per_page;
  310. space = rx_queue->max_fill - fill_level;
  311. EF4_BUG_ON_PARANOID(space < batch_size);
  312. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  313. "RX queue %d fast-filling descriptor ring from"
  314. " level %d to level %d\n",
  315. ef4_rx_queue_index(rx_queue), fill_level,
  316. rx_queue->max_fill);
  317. do {
  318. rc = ef4_init_rx_buffers(rx_queue, atomic);
  319. if (unlikely(rc)) {
  320. /* Ensure that we don't leave the rx queue empty */
  321. if (rx_queue->added_count == rx_queue->removed_count)
  322. ef4_schedule_slow_fill(rx_queue);
  323. goto out;
  324. }
  325. } while ((space -= batch_size) >= batch_size);
  326. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  327. "RX queue %d fast-filled descriptor ring "
  328. "to level %d\n", ef4_rx_queue_index(rx_queue),
  329. rx_queue->added_count - rx_queue->removed_count);
  330. out:
  331. if (rx_queue->notified_count != rx_queue->added_count)
  332. ef4_nic_notify_rx_desc(rx_queue);
  333. }
  334. void ef4_rx_slow_fill(struct timer_list *t)
  335. {
  336. struct ef4_rx_queue *rx_queue = from_timer(rx_queue, t, slow_fill);
  337. /* Post an event to cause NAPI to run and refill the queue */
  338. ef4_nic_generate_fill_event(rx_queue);
  339. ++rx_queue->slow_fill_count;
  340. }
  341. static void ef4_rx_packet__check_len(struct ef4_rx_queue *rx_queue,
  342. struct ef4_rx_buffer *rx_buf,
  343. int len)
  344. {
  345. struct ef4_nic *efx = rx_queue->efx;
  346. unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding;
  347. if (likely(len <= max_len))
  348. return;
  349. /* The packet must be discarded, but this is only a fatal error
  350. * if the caller indicated it was
  351. */
  352. rx_buf->flags |= EF4_RX_PKT_DISCARD;
  353. if ((len > rx_buf->len) && EF4_WORKAROUND_8071(efx)) {
  354. if (net_ratelimit())
  355. netif_err(efx, rx_err, efx->net_dev,
  356. " RX queue %d seriously overlength "
  357. "RX event (0x%x > 0x%x+0x%x). Leaking\n",
  358. ef4_rx_queue_index(rx_queue), len, max_len,
  359. efx->type->rx_buffer_padding);
  360. ef4_schedule_reset(efx, RESET_TYPE_RX_RECOVERY);
  361. } else {
  362. if (net_ratelimit())
  363. netif_err(efx, rx_err, efx->net_dev,
  364. " RX queue %d overlength RX event "
  365. "(0x%x > 0x%x)\n",
  366. ef4_rx_queue_index(rx_queue), len, max_len);
  367. }
  368. ef4_rx_queue_channel(rx_queue)->n_rx_overlength++;
  369. }
  370. /* Pass a received packet up through GRO. GRO can handle pages
  371. * regardless of checksum state and skbs with a good checksum.
  372. */
  373. static void
  374. ef4_rx_packet_gro(struct ef4_channel *channel, struct ef4_rx_buffer *rx_buf,
  375. unsigned int n_frags, u8 *eh)
  376. {
  377. struct napi_struct *napi = &channel->napi_str;
  378. struct ef4_nic *efx = channel->efx;
  379. struct sk_buff *skb;
  380. skb = napi_get_frags(napi);
  381. if (unlikely(!skb)) {
  382. struct ef4_rx_queue *rx_queue;
  383. rx_queue = ef4_channel_get_rx_queue(channel);
  384. ef4_free_rx_buffers(rx_queue, rx_buf, n_frags);
  385. return;
  386. }
  387. if (efx->net_dev->features & NETIF_F_RXHASH)
  388. skb_set_hash(skb, ef4_rx_buf_hash(efx, eh),
  389. PKT_HASH_TYPE_L3);
  390. skb->ip_summed = ((rx_buf->flags & EF4_RX_PKT_CSUMMED) ?
  391. CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
  392. for (;;) {
  393. skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
  394. rx_buf->page, rx_buf->page_offset,
  395. rx_buf->len);
  396. rx_buf->page = NULL;
  397. skb->len += rx_buf->len;
  398. if (skb_shinfo(skb)->nr_frags == n_frags)
  399. break;
  400. rx_buf = ef4_rx_buf_next(&channel->rx_queue, rx_buf);
  401. }
  402. skb->data_len = skb->len;
  403. skb->truesize += n_frags * efx->rx_buffer_truesize;
  404. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  405. napi_gro_frags(napi);
  406. }
  407. /* Allocate and construct an SKB around page fragments */
  408. static struct sk_buff *ef4_rx_mk_skb(struct ef4_channel *channel,
  409. struct ef4_rx_buffer *rx_buf,
  410. unsigned int n_frags,
  411. u8 *eh, int hdr_len)
  412. {
  413. struct ef4_nic *efx = channel->efx;
  414. struct sk_buff *skb;
  415. /* Allocate an SKB to store the headers */
  416. skb = netdev_alloc_skb(efx->net_dev,
  417. efx->rx_ip_align + efx->rx_prefix_size +
  418. hdr_len);
  419. if (unlikely(skb == NULL)) {
  420. atomic_inc(&efx->n_rx_noskb_drops);
  421. return NULL;
  422. }
  423. EF4_BUG_ON_PARANOID(rx_buf->len < hdr_len);
  424. memcpy(skb->data + efx->rx_ip_align, eh - efx->rx_prefix_size,
  425. efx->rx_prefix_size + hdr_len);
  426. skb_reserve(skb, efx->rx_ip_align + efx->rx_prefix_size);
  427. __skb_put(skb, hdr_len);
  428. /* Append the remaining page(s) onto the frag list */
  429. if (rx_buf->len > hdr_len) {
  430. rx_buf->page_offset += hdr_len;
  431. rx_buf->len -= hdr_len;
  432. for (;;) {
  433. skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
  434. rx_buf->page, rx_buf->page_offset,
  435. rx_buf->len);
  436. rx_buf->page = NULL;
  437. skb->len += rx_buf->len;
  438. skb->data_len += rx_buf->len;
  439. if (skb_shinfo(skb)->nr_frags == n_frags)
  440. break;
  441. rx_buf = ef4_rx_buf_next(&channel->rx_queue, rx_buf);
  442. }
  443. } else {
  444. __free_pages(rx_buf->page, efx->rx_buffer_order);
  445. rx_buf->page = NULL;
  446. n_frags = 0;
  447. }
  448. skb->truesize += n_frags * efx->rx_buffer_truesize;
  449. /* Move past the ethernet header */
  450. skb->protocol = eth_type_trans(skb, efx->net_dev);
  451. skb_mark_napi_id(skb, &channel->napi_str);
  452. return skb;
  453. }
  454. void ef4_rx_packet(struct ef4_rx_queue *rx_queue, unsigned int index,
  455. unsigned int n_frags, unsigned int len, u16 flags)
  456. {
  457. struct ef4_nic *efx = rx_queue->efx;
  458. struct ef4_channel *channel = ef4_rx_queue_channel(rx_queue);
  459. struct ef4_rx_buffer *rx_buf;
  460. rx_queue->rx_packets++;
  461. rx_buf = ef4_rx_buffer(rx_queue, index);
  462. rx_buf->flags |= flags;
  463. /* Validate the number of fragments and completed length */
  464. if (n_frags == 1) {
  465. if (!(flags & EF4_RX_PKT_PREFIX_LEN))
  466. ef4_rx_packet__check_len(rx_queue, rx_buf, len);
  467. } else if (unlikely(n_frags > EF4_RX_MAX_FRAGS) ||
  468. unlikely(len <= (n_frags - 1) * efx->rx_dma_len) ||
  469. unlikely(len > n_frags * efx->rx_dma_len) ||
  470. unlikely(!efx->rx_scatter)) {
  471. /* If this isn't an explicit discard request, either
  472. * the hardware or the driver is broken.
  473. */
  474. WARN_ON(!(len == 0 && rx_buf->flags & EF4_RX_PKT_DISCARD));
  475. rx_buf->flags |= EF4_RX_PKT_DISCARD;
  476. }
  477. netif_vdbg(efx, rx_status, efx->net_dev,
  478. "RX queue %d received ids %x-%x len %d %s%s\n",
  479. ef4_rx_queue_index(rx_queue), index,
  480. (index + n_frags - 1) & rx_queue->ptr_mask, len,
  481. (rx_buf->flags & EF4_RX_PKT_CSUMMED) ? " [SUMMED]" : "",
  482. (rx_buf->flags & EF4_RX_PKT_DISCARD) ? " [DISCARD]" : "");
  483. /* Discard packet, if instructed to do so. Process the
  484. * previous receive first.
  485. */
  486. if (unlikely(rx_buf->flags & EF4_RX_PKT_DISCARD)) {
  487. ef4_rx_flush_packet(channel);
  488. ef4_discard_rx_packet(channel, rx_buf, n_frags);
  489. return;
  490. }
  491. if (n_frags == 1 && !(flags & EF4_RX_PKT_PREFIX_LEN))
  492. rx_buf->len = len;
  493. /* Release and/or sync the DMA mapping - assumes all RX buffers
  494. * consumed in-order per RX queue.
  495. */
  496. ef4_sync_rx_buffer(efx, rx_buf, rx_buf->len);
  497. /* Prefetch nice and early so data will (hopefully) be in cache by
  498. * the time we look at it.
  499. */
  500. prefetch(ef4_rx_buf_va(rx_buf));
  501. rx_buf->page_offset += efx->rx_prefix_size;
  502. rx_buf->len -= efx->rx_prefix_size;
  503. if (n_frags > 1) {
  504. /* Release/sync DMA mapping for additional fragments.
  505. * Fix length for last fragment.
  506. */
  507. unsigned int tail_frags = n_frags - 1;
  508. for (;;) {
  509. rx_buf = ef4_rx_buf_next(rx_queue, rx_buf);
  510. if (--tail_frags == 0)
  511. break;
  512. ef4_sync_rx_buffer(efx, rx_buf, efx->rx_dma_len);
  513. }
  514. rx_buf->len = len - (n_frags - 1) * efx->rx_dma_len;
  515. ef4_sync_rx_buffer(efx, rx_buf, rx_buf->len);
  516. }
  517. /* All fragments have been DMA-synced, so recycle pages. */
  518. rx_buf = ef4_rx_buffer(rx_queue, index);
  519. ef4_recycle_rx_pages(channel, rx_buf, n_frags);
  520. /* Pipeline receives so that we give time for packet headers to be
  521. * prefetched into cache.
  522. */
  523. ef4_rx_flush_packet(channel);
  524. channel->rx_pkt_n_frags = n_frags;
  525. channel->rx_pkt_index = index;
  526. }
  527. static void ef4_rx_deliver(struct ef4_channel *channel, u8 *eh,
  528. struct ef4_rx_buffer *rx_buf,
  529. unsigned int n_frags)
  530. {
  531. struct sk_buff *skb;
  532. u16 hdr_len = min_t(u16, rx_buf->len, EF4_SKB_HEADERS);
  533. skb = ef4_rx_mk_skb(channel, rx_buf, n_frags, eh, hdr_len);
  534. if (unlikely(skb == NULL)) {
  535. struct ef4_rx_queue *rx_queue;
  536. rx_queue = ef4_channel_get_rx_queue(channel);
  537. ef4_free_rx_buffers(rx_queue, rx_buf, n_frags);
  538. return;
  539. }
  540. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  541. /* Set the SKB flags */
  542. skb_checksum_none_assert(skb);
  543. if (likely(rx_buf->flags & EF4_RX_PKT_CSUMMED))
  544. skb->ip_summed = CHECKSUM_UNNECESSARY;
  545. if (channel->type->receive_skb)
  546. if (channel->type->receive_skb(channel, skb))
  547. return;
  548. /* Pass the packet up */
  549. netif_receive_skb(skb);
  550. }
  551. /* Handle a received packet. Second half: Touches packet payload. */
  552. void __ef4_rx_packet(struct ef4_channel *channel)
  553. {
  554. struct ef4_nic *efx = channel->efx;
  555. struct ef4_rx_buffer *rx_buf =
  556. ef4_rx_buffer(&channel->rx_queue, channel->rx_pkt_index);
  557. u8 *eh = ef4_rx_buf_va(rx_buf);
  558. /* Read length from the prefix if necessary. This already
  559. * excludes the length of the prefix itself.
  560. */
  561. if (rx_buf->flags & EF4_RX_PKT_PREFIX_LEN)
  562. rx_buf->len = le16_to_cpup((__le16 *)
  563. (eh + efx->rx_packet_len_offset));
  564. /* If we're in loopback test, then pass the packet directly to the
  565. * loopback layer, and free the rx_buf here
  566. */
  567. if (unlikely(efx->loopback_selftest)) {
  568. struct ef4_rx_queue *rx_queue;
  569. ef4_loopback_rx_packet(efx, eh, rx_buf->len);
  570. rx_queue = ef4_channel_get_rx_queue(channel);
  571. ef4_free_rx_buffers(rx_queue, rx_buf,
  572. channel->rx_pkt_n_frags);
  573. goto out;
  574. }
  575. if (unlikely(!(efx->net_dev->features & NETIF_F_RXCSUM)))
  576. rx_buf->flags &= ~EF4_RX_PKT_CSUMMED;
  577. if ((rx_buf->flags & EF4_RX_PKT_TCP) && !channel->type->receive_skb)
  578. ef4_rx_packet_gro(channel, rx_buf, channel->rx_pkt_n_frags, eh);
  579. else
  580. ef4_rx_deliver(channel, eh, rx_buf, channel->rx_pkt_n_frags);
  581. out:
  582. channel->rx_pkt_n_frags = 0;
  583. }
  584. int ef4_probe_rx_queue(struct ef4_rx_queue *rx_queue)
  585. {
  586. struct ef4_nic *efx = rx_queue->efx;
  587. unsigned int entries;
  588. int rc;
  589. /* Create the smallest power-of-two aligned ring */
  590. entries = max(roundup_pow_of_two(efx->rxq_entries), EF4_MIN_DMAQ_SIZE);
  591. EF4_BUG_ON_PARANOID(entries > EF4_MAX_DMAQ_SIZE);
  592. rx_queue->ptr_mask = entries - 1;
  593. netif_dbg(efx, probe, efx->net_dev,
  594. "creating RX queue %d size %#x mask %#x\n",
  595. ef4_rx_queue_index(rx_queue), efx->rxq_entries,
  596. rx_queue->ptr_mask);
  597. /* Allocate RX buffers */
  598. rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer),
  599. GFP_KERNEL);
  600. if (!rx_queue->buffer)
  601. return -ENOMEM;
  602. rc = ef4_nic_probe_rx(rx_queue);
  603. if (rc) {
  604. kfree(rx_queue->buffer);
  605. rx_queue->buffer = NULL;
  606. }
  607. return rc;
  608. }
  609. static void ef4_init_rx_recycle_ring(struct ef4_nic *efx,
  610. struct ef4_rx_queue *rx_queue)
  611. {
  612. unsigned int bufs_in_recycle_ring, page_ring_size;
  613. struct iommu_domain __maybe_unused *domain;
  614. /* Set the RX recycle ring size */
  615. #ifdef CONFIG_PPC64
  616. bufs_in_recycle_ring = EF4_RECYCLE_RING_SIZE_IOMMU;
  617. #else
  618. domain = iommu_get_domain_for_dev(&efx->pci_dev->dev);
  619. if (domain && domain->type != IOMMU_DOMAIN_IDENTITY)
  620. bufs_in_recycle_ring = EF4_RECYCLE_RING_SIZE_IOMMU;
  621. else
  622. bufs_in_recycle_ring = EF4_RECYCLE_RING_SIZE_NOIOMMU;
  623. #endif /* CONFIG_PPC64 */
  624. page_ring_size = roundup_pow_of_two(bufs_in_recycle_ring /
  625. efx->rx_bufs_per_page);
  626. rx_queue->page_ring = kcalloc(page_ring_size,
  627. sizeof(*rx_queue->page_ring), GFP_KERNEL);
  628. if (!rx_queue->page_ring)
  629. rx_queue->page_ptr_mask = 0;
  630. else
  631. rx_queue->page_ptr_mask = page_ring_size - 1;
  632. }
  633. void ef4_init_rx_queue(struct ef4_rx_queue *rx_queue)
  634. {
  635. struct ef4_nic *efx = rx_queue->efx;
  636. unsigned int max_fill, trigger, max_trigger;
  637. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  638. "initialising RX queue %d\n", ef4_rx_queue_index(rx_queue));
  639. /* Initialise ptr fields */
  640. rx_queue->added_count = 0;
  641. rx_queue->notified_count = 0;
  642. rx_queue->removed_count = 0;
  643. rx_queue->min_fill = -1U;
  644. ef4_init_rx_recycle_ring(efx, rx_queue);
  645. rx_queue->page_remove = 0;
  646. rx_queue->page_add = rx_queue->page_ptr_mask + 1;
  647. rx_queue->page_recycle_count = 0;
  648. rx_queue->page_recycle_failed = 0;
  649. rx_queue->page_recycle_full = 0;
  650. /* Initialise limit fields */
  651. max_fill = efx->rxq_entries - EF4_RXD_HEAD_ROOM;
  652. max_trigger =
  653. max_fill - efx->rx_pages_per_batch * efx->rx_bufs_per_page;
  654. if (rx_refill_threshold != 0) {
  655. trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
  656. if (trigger > max_trigger)
  657. trigger = max_trigger;
  658. } else {
  659. trigger = max_trigger;
  660. }
  661. rx_queue->max_fill = max_fill;
  662. rx_queue->fast_fill_trigger = trigger;
  663. rx_queue->refill_enabled = true;
  664. /* Set up RX descriptor ring */
  665. ef4_nic_init_rx(rx_queue);
  666. }
  667. void ef4_fini_rx_queue(struct ef4_rx_queue *rx_queue)
  668. {
  669. int i;
  670. struct ef4_nic *efx = rx_queue->efx;
  671. struct ef4_rx_buffer *rx_buf;
  672. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  673. "shutting down RX queue %d\n", ef4_rx_queue_index(rx_queue));
  674. del_timer_sync(&rx_queue->slow_fill);
  675. /* Release RX buffers from the current read ptr to the write ptr */
  676. if (rx_queue->buffer) {
  677. for (i = rx_queue->removed_count; i < rx_queue->added_count;
  678. i++) {
  679. unsigned index = i & rx_queue->ptr_mask;
  680. rx_buf = ef4_rx_buffer(rx_queue, index);
  681. ef4_fini_rx_buffer(rx_queue, rx_buf);
  682. }
  683. }
  684. /* Unmap and release the pages in the recycle ring. Remove the ring. */
  685. for (i = 0; i <= rx_queue->page_ptr_mask; i++) {
  686. struct page *page = rx_queue->page_ring[i];
  687. struct ef4_rx_page_state *state;
  688. if (page == NULL)
  689. continue;
  690. state = page_address(page);
  691. dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
  692. PAGE_SIZE << efx->rx_buffer_order,
  693. DMA_FROM_DEVICE);
  694. put_page(page);
  695. }
  696. kfree(rx_queue->page_ring);
  697. rx_queue->page_ring = NULL;
  698. }
  699. void ef4_remove_rx_queue(struct ef4_rx_queue *rx_queue)
  700. {
  701. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  702. "destroying RX queue %d\n", ef4_rx_queue_index(rx_queue));
  703. ef4_nic_remove_rx(rx_queue);
  704. kfree(rx_queue->buffer);
  705. rx_queue->buffer = NULL;
  706. }
  707. module_param(rx_refill_threshold, uint, 0444);
  708. MODULE_PARM_DESC(rx_refill_threshold,
  709. "RX descriptor ring refill threshold (%)");
  710. #ifdef CONFIG_RFS_ACCEL
  711. int ef4_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
  712. u16 rxq_index, u32 flow_id)
  713. {
  714. struct ef4_nic *efx = netdev_priv(net_dev);
  715. struct ef4_channel *channel;
  716. struct ef4_filter_spec spec;
  717. struct flow_keys fk;
  718. int rc;
  719. if (flow_id == RPS_FLOW_ID_INVALID)
  720. return -EINVAL;
  721. if (!skb_flow_dissect_flow_keys(skb, &fk, 0))
  722. return -EPROTONOSUPPORT;
  723. if (fk.basic.n_proto != htons(ETH_P_IP) && fk.basic.n_proto != htons(ETH_P_IPV6))
  724. return -EPROTONOSUPPORT;
  725. if (fk.control.flags & FLOW_DIS_IS_FRAGMENT)
  726. return -EPROTONOSUPPORT;
  727. ef4_filter_init_rx(&spec, EF4_FILTER_PRI_HINT,
  728. efx->rx_scatter ? EF4_FILTER_FLAG_RX_SCATTER : 0,
  729. rxq_index);
  730. spec.match_flags =
  731. EF4_FILTER_MATCH_ETHER_TYPE | EF4_FILTER_MATCH_IP_PROTO |
  732. EF4_FILTER_MATCH_LOC_HOST | EF4_FILTER_MATCH_LOC_PORT |
  733. EF4_FILTER_MATCH_REM_HOST | EF4_FILTER_MATCH_REM_PORT;
  734. spec.ether_type = fk.basic.n_proto;
  735. spec.ip_proto = fk.basic.ip_proto;
  736. if (fk.basic.n_proto == htons(ETH_P_IP)) {
  737. spec.rem_host[0] = fk.addrs.v4addrs.src;
  738. spec.loc_host[0] = fk.addrs.v4addrs.dst;
  739. } else {
  740. memcpy(spec.rem_host, &fk.addrs.v6addrs.src, sizeof(struct in6_addr));
  741. memcpy(spec.loc_host, &fk.addrs.v6addrs.dst, sizeof(struct in6_addr));
  742. }
  743. spec.rem_port = fk.ports.src;
  744. spec.loc_port = fk.ports.dst;
  745. rc = efx->type->filter_rfs_insert(efx, &spec);
  746. if (rc < 0)
  747. return rc;
  748. /* Remember this so we can check whether to expire the filter later */
  749. channel = ef4_get_channel(efx, rxq_index);
  750. channel->rps_flow_id[rc] = flow_id;
  751. ++channel->rfs_filters_added;
  752. if (spec.ether_type == htons(ETH_P_IP))
  753. netif_info(efx, rx_status, efx->net_dev,
  754. "steering %s %pI4:%u:%pI4:%u to queue %u [flow %u filter %d]\n",
  755. (spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  756. spec.rem_host, ntohs(spec.rem_port), spec.loc_host,
  757. ntohs(spec.loc_port), rxq_index, flow_id, rc);
  758. else
  759. netif_info(efx, rx_status, efx->net_dev,
  760. "steering %s [%pI6]:%u:[%pI6]:%u to queue %u [flow %u filter %d]\n",
  761. (spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  762. spec.rem_host, ntohs(spec.rem_port), spec.loc_host,
  763. ntohs(spec.loc_port), rxq_index, flow_id, rc);
  764. return rc;
  765. }
  766. bool __ef4_filter_rfs_expire(struct ef4_nic *efx, unsigned int quota)
  767. {
  768. bool (*expire_one)(struct ef4_nic *efx, u32 flow_id, unsigned int index);
  769. unsigned int channel_idx, index, size;
  770. u32 flow_id;
  771. if (!spin_trylock_bh(&efx->filter_lock))
  772. return false;
  773. expire_one = efx->type->filter_rfs_expire_one;
  774. channel_idx = efx->rps_expire_channel;
  775. index = efx->rps_expire_index;
  776. size = efx->type->max_rx_ip_filters;
  777. while (quota--) {
  778. struct ef4_channel *channel = ef4_get_channel(efx, channel_idx);
  779. flow_id = channel->rps_flow_id[index];
  780. if (flow_id != RPS_FLOW_ID_INVALID &&
  781. expire_one(efx, flow_id, index)) {
  782. netif_info(efx, rx_status, efx->net_dev,
  783. "expired filter %d [queue %u flow %u]\n",
  784. index, channel_idx, flow_id);
  785. channel->rps_flow_id[index] = RPS_FLOW_ID_INVALID;
  786. }
  787. if (++index == size) {
  788. if (++channel_idx == efx->n_channels)
  789. channel_idx = 0;
  790. index = 0;
  791. }
  792. }
  793. efx->rps_expire_channel = channel_idx;
  794. efx->rps_expire_index = index;
  795. spin_unlock_bh(&efx->filter_lock);
  796. return true;
  797. }
  798. #endif /* CONFIG_RFS_ACCEL */
  799. /**
  800. * ef4_filter_is_mc_recipient - test whether spec is a multicast recipient
  801. * @spec: Specification to test
  802. *
  803. * Return: %true if the specification is a non-drop RX filter that
  804. * matches a local MAC address I/G bit value of 1 or matches a local
  805. * IPv4 or IPv6 address value in the respective multicast address
  806. * range. Otherwise %false.
  807. */
  808. bool ef4_filter_is_mc_recipient(const struct ef4_filter_spec *spec)
  809. {
  810. if (!(spec->flags & EF4_FILTER_FLAG_RX) ||
  811. spec->dmaq_id == EF4_FILTER_RX_DMAQ_ID_DROP)
  812. return false;
  813. if (spec->match_flags &
  814. (EF4_FILTER_MATCH_LOC_MAC | EF4_FILTER_MATCH_LOC_MAC_IG) &&
  815. is_multicast_ether_addr(spec->loc_mac))
  816. return true;
  817. if ((spec->match_flags &
  818. (EF4_FILTER_MATCH_ETHER_TYPE | EF4_FILTER_MATCH_LOC_HOST)) ==
  819. (EF4_FILTER_MATCH_ETHER_TYPE | EF4_FILTER_MATCH_LOC_HOST)) {
  820. if (spec->ether_type == htons(ETH_P_IP) &&
  821. ipv4_is_multicast(spec->loc_host[0]))
  822. return true;
  823. if (spec->ether_type == htons(ETH_P_IPV6) &&
  824. ((const u8 *)spec->loc_host)[0] == 0xff)
  825. return true;
  826. }
  827. return false;
  828. }