cnic.c 149 KB

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  1. /* cnic.c: QLogic CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2014 Broadcom Corporation
  4. * Copyright (c) 2014-2015 QLogic Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. *
  10. * Original skeleton written by: John(Zongxi) Chen ([email protected])
  11. * Previously modified and maintained by: Michael Chan <[email protected]>
  12. * Maintained By: [email protected]
  13. */
  14. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/errno.h>
  18. #include <linux/list.h>
  19. #include <linux/slab.h>
  20. #include <linux/pci.h>
  21. #include <linux/init.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/uio_driver.h>
  24. #include <linux/in.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/delay.h>
  27. #include <linux/ethtool.h>
  28. #include <linux/if_vlan.h>
  29. #include <linux/prefetch.h>
  30. #include <linux/random.h>
  31. #if IS_ENABLED(CONFIG_VLAN_8021Q)
  32. #define BCM_VLAN 1
  33. #endif
  34. #include <net/ip.h>
  35. #include <net/tcp.h>
  36. #include <net/route.h>
  37. #include <net/ipv6.h>
  38. #include <net/ip6_route.h>
  39. #include <net/ip6_checksum.h>
  40. #include <scsi/iscsi_if.h>
  41. #define BCM_CNIC 1
  42. #include "cnic_if.h"
  43. #include "bnx2.h"
  44. #include "bnx2x/bnx2x.h"
  45. #include "bnx2x/bnx2x_reg.h"
  46. #include "bnx2x/bnx2x_fw_defs.h"
  47. #include "bnx2x/bnx2x_hsi.h"
  48. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  49. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  50. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  51. #include "cnic.h"
  52. #include "cnic_defs.h"
  53. #define CNIC_MODULE_NAME "cnic"
  54. static char version[] =
  55. "QLogic " CNIC_MODULE_NAME "Driver v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  56. MODULE_AUTHOR("Michael Chan <[email protected]> and John(Zongxi) "
  57. "Chen ([email protected]");
  58. MODULE_DESCRIPTION("QLogic cnic Driver");
  59. MODULE_LICENSE("GPL");
  60. MODULE_VERSION(CNIC_MODULE_VERSION);
  61. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  62. static LIST_HEAD(cnic_dev_list);
  63. static LIST_HEAD(cnic_udev_list);
  64. static DEFINE_RWLOCK(cnic_dev_lock);
  65. static DEFINE_MUTEX(cnic_lock);
  66. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  67. /* helper function, assuming cnic_lock is held */
  68. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  69. {
  70. return rcu_dereference_protected(cnic_ulp_tbl[type],
  71. lockdep_is_held(&cnic_lock));
  72. }
  73. static int cnic_service_bnx2(void *, void *);
  74. static int cnic_service_bnx2x(void *, void *);
  75. static int cnic_ctl(void *, struct cnic_ctl_info *);
  76. static struct cnic_ops cnic_bnx2_ops = {
  77. .cnic_owner = THIS_MODULE,
  78. .cnic_handler = cnic_service_bnx2,
  79. .cnic_ctl = cnic_ctl,
  80. };
  81. static struct cnic_ops cnic_bnx2x_ops = {
  82. .cnic_owner = THIS_MODULE,
  83. .cnic_handler = cnic_service_bnx2x,
  84. .cnic_ctl = cnic_ctl,
  85. };
  86. static struct workqueue_struct *cnic_wq;
  87. static void cnic_shutdown_rings(struct cnic_dev *);
  88. static void cnic_init_rings(struct cnic_dev *);
  89. static int cnic_cm_set_pg(struct cnic_sock *);
  90. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  91. {
  92. struct cnic_uio_dev *udev = uinfo->priv;
  93. struct cnic_dev *dev;
  94. if (!capable(CAP_NET_ADMIN))
  95. return -EPERM;
  96. if (udev->uio_dev != -1)
  97. return -EBUSY;
  98. rtnl_lock();
  99. dev = udev->dev;
  100. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  101. rtnl_unlock();
  102. return -ENODEV;
  103. }
  104. udev->uio_dev = iminor(inode);
  105. cnic_shutdown_rings(dev);
  106. cnic_init_rings(dev);
  107. rtnl_unlock();
  108. return 0;
  109. }
  110. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  111. {
  112. struct cnic_uio_dev *udev = uinfo->priv;
  113. udev->uio_dev = -1;
  114. return 0;
  115. }
  116. static inline void cnic_hold(struct cnic_dev *dev)
  117. {
  118. atomic_inc(&dev->ref_count);
  119. }
  120. static inline void cnic_put(struct cnic_dev *dev)
  121. {
  122. atomic_dec(&dev->ref_count);
  123. }
  124. static inline void csk_hold(struct cnic_sock *csk)
  125. {
  126. atomic_inc(&csk->ref_count);
  127. }
  128. static inline void csk_put(struct cnic_sock *csk)
  129. {
  130. atomic_dec(&csk->ref_count);
  131. }
  132. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  133. {
  134. struct cnic_dev *cdev;
  135. read_lock(&cnic_dev_lock);
  136. list_for_each_entry(cdev, &cnic_dev_list, list) {
  137. if (netdev == cdev->netdev) {
  138. cnic_hold(cdev);
  139. read_unlock(&cnic_dev_lock);
  140. return cdev;
  141. }
  142. }
  143. read_unlock(&cnic_dev_lock);
  144. return NULL;
  145. }
  146. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  147. {
  148. atomic_inc(&ulp_ops->ref_count);
  149. }
  150. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  151. {
  152. atomic_dec(&ulp_ops->ref_count);
  153. }
  154. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  155. {
  156. struct cnic_local *cp = dev->cnic_priv;
  157. struct cnic_eth_dev *ethdev = cp->ethdev;
  158. struct drv_ctl_info info;
  159. struct drv_ctl_io *io = &info.data.io;
  160. memset(&info, 0, sizeof(struct drv_ctl_info));
  161. info.cmd = DRV_CTL_CTX_WR_CMD;
  162. io->cid_addr = cid_addr;
  163. io->offset = off;
  164. io->data = val;
  165. ethdev->drv_ctl(dev->netdev, &info);
  166. }
  167. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  168. {
  169. struct cnic_local *cp = dev->cnic_priv;
  170. struct cnic_eth_dev *ethdev = cp->ethdev;
  171. struct drv_ctl_info info;
  172. struct drv_ctl_io *io = &info.data.io;
  173. memset(&info, 0, sizeof(struct drv_ctl_info));
  174. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  175. io->offset = off;
  176. io->dma_addr = addr;
  177. ethdev->drv_ctl(dev->netdev, &info);
  178. }
  179. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  180. {
  181. struct cnic_local *cp = dev->cnic_priv;
  182. struct cnic_eth_dev *ethdev = cp->ethdev;
  183. struct drv_ctl_info info;
  184. struct drv_ctl_l2_ring *ring = &info.data.ring;
  185. memset(&info, 0, sizeof(struct drv_ctl_info));
  186. if (start)
  187. info.cmd = DRV_CTL_START_L2_CMD;
  188. else
  189. info.cmd = DRV_CTL_STOP_L2_CMD;
  190. ring->cid = cid;
  191. ring->client_id = cl_id;
  192. ethdev->drv_ctl(dev->netdev, &info);
  193. }
  194. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  195. {
  196. struct cnic_local *cp = dev->cnic_priv;
  197. struct cnic_eth_dev *ethdev = cp->ethdev;
  198. struct drv_ctl_info info;
  199. struct drv_ctl_io *io = &info.data.io;
  200. memset(&info, 0, sizeof(struct drv_ctl_info));
  201. info.cmd = DRV_CTL_IO_WR_CMD;
  202. io->offset = off;
  203. io->data = val;
  204. ethdev->drv_ctl(dev->netdev, &info);
  205. }
  206. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  207. {
  208. struct cnic_local *cp = dev->cnic_priv;
  209. struct cnic_eth_dev *ethdev = cp->ethdev;
  210. struct drv_ctl_info info;
  211. struct drv_ctl_io *io = &info.data.io;
  212. memset(&info, 0, sizeof(struct drv_ctl_info));
  213. info.cmd = DRV_CTL_IO_RD_CMD;
  214. io->offset = off;
  215. ethdev->drv_ctl(dev->netdev, &info);
  216. return io->data;
  217. }
  218. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg, int state)
  219. {
  220. struct cnic_local *cp = dev->cnic_priv;
  221. struct cnic_eth_dev *ethdev = cp->ethdev;
  222. struct drv_ctl_info info;
  223. struct fcoe_capabilities *fcoe_cap =
  224. &info.data.register_data.fcoe_features;
  225. memset(&info, 0, sizeof(struct drv_ctl_info));
  226. if (reg) {
  227. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  228. if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
  229. memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
  230. } else {
  231. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  232. }
  233. info.data.ulp_type = ulp_type;
  234. info.drv_state = state;
  235. ethdev->drv_ctl(dev->netdev, &info);
  236. }
  237. static int cnic_in_use(struct cnic_sock *csk)
  238. {
  239. return test_bit(SK_F_INUSE, &csk->flags);
  240. }
  241. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  242. {
  243. struct cnic_local *cp = dev->cnic_priv;
  244. struct cnic_eth_dev *ethdev = cp->ethdev;
  245. struct drv_ctl_info info;
  246. memset(&info, 0, sizeof(struct drv_ctl_info));
  247. info.cmd = cmd;
  248. info.data.credit.credit_count = count;
  249. ethdev->drv_ctl(dev->netdev, &info);
  250. }
  251. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  252. {
  253. u32 i;
  254. if (!cp->ctx_tbl)
  255. return -EINVAL;
  256. for (i = 0; i < cp->max_cid_space; i++) {
  257. if (cp->ctx_tbl[i].cid == cid) {
  258. *l5_cid = i;
  259. return 0;
  260. }
  261. }
  262. return -EINVAL;
  263. }
  264. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  265. struct cnic_sock *csk)
  266. {
  267. struct iscsi_path path_req;
  268. char *buf = NULL;
  269. u16 len = 0;
  270. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  271. struct cnic_ulp_ops *ulp_ops;
  272. struct cnic_uio_dev *udev = cp->udev;
  273. int rc = 0, retry = 0;
  274. if (!udev || udev->uio_dev == -1)
  275. return -ENODEV;
  276. if (csk) {
  277. len = sizeof(path_req);
  278. buf = (char *) &path_req;
  279. memset(&path_req, 0, len);
  280. msg_type = ISCSI_KEVENT_PATH_REQ;
  281. path_req.handle = (u64) csk->l5_cid;
  282. if (test_bit(SK_F_IPV6, &csk->flags)) {
  283. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  284. sizeof(struct in6_addr));
  285. path_req.ip_addr_len = 16;
  286. } else {
  287. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  288. sizeof(struct in_addr));
  289. path_req.ip_addr_len = 4;
  290. }
  291. path_req.vlan_id = csk->vlan_id;
  292. path_req.pmtu = csk->mtu;
  293. }
  294. while (retry < 3) {
  295. rc = 0;
  296. rcu_read_lock();
  297. ulp_ops = rcu_dereference(cp->ulp_ops[CNIC_ULP_ISCSI]);
  298. if (ulp_ops)
  299. rc = ulp_ops->iscsi_nl_send_msg(
  300. cp->ulp_handle[CNIC_ULP_ISCSI],
  301. msg_type, buf, len);
  302. rcu_read_unlock();
  303. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  304. break;
  305. msleep(100);
  306. retry++;
  307. }
  308. return rc;
  309. }
  310. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  311. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  312. char *buf, u16 len)
  313. {
  314. int rc = -EINVAL;
  315. switch (msg_type) {
  316. case ISCSI_UEVENT_PATH_UPDATE: {
  317. struct cnic_local *cp;
  318. u32 l5_cid;
  319. struct cnic_sock *csk;
  320. struct iscsi_path *path_resp;
  321. if (len < sizeof(*path_resp))
  322. break;
  323. path_resp = (struct iscsi_path *) buf;
  324. cp = dev->cnic_priv;
  325. l5_cid = (u32) path_resp->handle;
  326. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  327. break;
  328. if (!rcu_access_pointer(cp->ulp_ops[CNIC_ULP_L4])) {
  329. rc = -ENODEV;
  330. break;
  331. }
  332. csk = &cp->csk_tbl[l5_cid];
  333. csk_hold(csk);
  334. if (cnic_in_use(csk) &&
  335. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  336. csk->vlan_id = path_resp->vlan_id;
  337. memcpy(csk->ha, path_resp->mac_addr, ETH_ALEN);
  338. if (test_bit(SK_F_IPV6, &csk->flags))
  339. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  340. sizeof(struct in6_addr));
  341. else
  342. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  343. sizeof(struct in_addr));
  344. if (is_valid_ether_addr(csk->ha)) {
  345. cnic_cm_set_pg(csk);
  346. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  347. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  348. cnic_cm_upcall(cp, csk,
  349. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  350. clear_bit(SK_F_CONNECT_START, &csk->flags);
  351. }
  352. }
  353. csk_put(csk);
  354. rc = 0;
  355. }
  356. }
  357. return rc;
  358. }
  359. static int cnic_offld_prep(struct cnic_sock *csk)
  360. {
  361. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  362. return 0;
  363. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  364. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  365. return 0;
  366. }
  367. return 1;
  368. }
  369. static int cnic_close_prep(struct cnic_sock *csk)
  370. {
  371. clear_bit(SK_F_CONNECT_START, &csk->flags);
  372. smp_mb__after_atomic();
  373. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  374. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  375. msleep(1);
  376. return 1;
  377. }
  378. return 0;
  379. }
  380. static int cnic_abort_prep(struct cnic_sock *csk)
  381. {
  382. clear_bit(SK_F_CONNECT_START, &csk->flags);
  383. smp_mb__after_atomic();
  384. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  385. msleep(1);
  386. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  387. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  388. return 1;
  389. }
  390. return 0;
  391. }
  392. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  393. {
  394. struct cnic_dev *dev;
  395. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  396. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  397. return -EINVAL;
  398. }
  399. mutex_lock(&cnic_lock);
  400. if (cnic_ulp_tbl_prot(ulp_type)) {
  401. pr_err("%s: Type %d has already been registered\n",
  402. __func__, ulp_type);
  403. mutex_unlock(&cnic_lock);
  404. return -EBUSY;
  405. }
  406. read_lock(&cnic_dev_lock);
  407. list_for_each_entry(dev, &cnic_dev_list, list) {
  408. struct cnic_local *cp = dev->cnic_priv;
  409. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  410. }
  411. read_unlock(&cnic_dev_lock);
  412. atomic_set(&ulp_ops->ref_count, 0);
  413. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  414. mutex_unlock(&cnic_lock);
  415. /* Prevent race conditions with netdev_event */
  416. rtnl_lock();
  417. list_for_each_entry(dev, &cnic_dev_list, list) {
  418. struct cnic_local *cp = dev->cnic_priv;
  419. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  420. ulp_ops->cnic_init(dev);
  421. }
  422. rtnl_unlock();
  423. return 0;
  424. }
  425. int cnic_unregister_driver(int ulp_type)
  426. {
  427. struct cnic_dev *dev;
  428. struct cnic_ulp_ops *ulp_ops;
  429. int i = 0;
  430. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  431. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  432. return -EINVAL;
  433. }
  434. mutex_lock(&cnic_lock);
  435. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  436. if (!ulp_ops) {
  437. pr_err("%s: Type %d has not been registered\n",
  438. __func__, ulp_type);
  439. goto out_unlock;
  440. }
  441. read_lock(&cnic_dev_lock);
  442. list_for_each_entry(dev, &cnic_dev_list, list) {
  443. struct cnic_local *cp = dev->cnic_priv;
  444. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  445. pr_err("%s: Type %d still has devices registered\n",
  446. __func__, ulp_type);
  447. read_unlock(&cnic_dev_lock);
  448. goto out_unlock;
  449. }
  450. }
  451. read_unlock(&cnic_dev_lock);
  452. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  453. mutex_unlock(&cnic_lock);
  454. synchronize_rcu();
  455. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  456. msleep(100);
  457. i++;
  458. }
  459. if (atomic_read(&ulp_ops->ref_count) != 0)
  460. pr_warn("%s: Failed waiting for ref count to go to zero\n",
  461. __func__);
  462. return 0;
  463. out_unlock:
  464. mutex_unlock(&cnic_lock);
  465. return -EINVAL;
  466. }
  467. static int cnic_start_hw(struct cnic_dev *);
  468. static void cnic_stop_hw(struct cnic_dev *);
  469. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  470. void *ulp_ctx)
  471. {
  472. struct cnic_local *cp = dev->cnic_priv;
  473. struct cnic_ulp_ops *ulp_ops;
  474. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  475. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  476. return -EINVAL;
  477. }
  478. mutex_lock(&cnic_lock);
  479. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  480. pr_err("%s: Driver with type %d has not been registered\n",
  481. __func__, ulp_type);
  482. mutex_unlock(&cnic_lock);
  483. return -EAGAIN;
  484. }
  485. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  486. pr_err("%s: Type %d has already been registered to this device\n",
  487. __func__, ulp_type);
  488. mutex_unlock(&cnic_lock);
  489. return -EBUSY;
  490. }
  491. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  492. cp->ulp_handle[ulp_type] = ulp_ctx;
  493. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  494. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  495. cnic_hold(dev);
  496. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  497. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  498. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  499. mutex_unlock(&cnic_lock);
  500. cnic_ulp_ctl(dev, ulp_type, true, DRV_ACTIVE);
  501. return 0;
  502. }
  503. EXPORT_SYMBOL(cnic_register_driver);
  504. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  505. {
  506. struct cnic_local *cp = dev->cnic_priv;
  507. int i = 0;
  508. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  509. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  510. return -EINVAL;
  511. }
  512. if (ulp_type == CNIC_ULP_ISCSI)
  513. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  514. mutex_lock(&cnic_lock);
  515. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  516. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  517. cnic_put(dev);
  518. } else {
  519. pr_err("%s: device not registered to this ulp type %d\n",
  520. __func__, ulp_type);
  521. mutex_unlock(&cnic_lock);
  522. return -EINVAL;
  523. }
  524. mutex_unlock(&cnic_lock);
  525. if (ulp_type == CNIC_ULP_FCOE)
  526. dev->fcoe_cap = NULL;
  527. synchronize_rcu();
  528. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  529. i < 20) {
  530. msleep(100);
  531. i++;
  532. }
  533. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  534. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  535. if (test_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  536. cnic_ulp_ctl(dev, ulp_type, false, DRV_UNLOADED);
  537. else
  538. cnic_ulp_ctl(dev, ulp_type, false, DRV_INACTIVE);
  539. return 0;
  540. }
  541. EXPORT_SYMBOL(cnic_unregister_driver);
  542. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  543. u32 next)
  544. {
  545. id_tbl->start = start_id;
  546. id_tbl->max = size;
  547. id_tbl->next = next;
  548. spin_lock_init(&id_tbl->lock);
  549. id_tbl->table = bitmap_zalloc(size, GFP_KERNEL);
  550. if (!id_tbl->table)
  551. return -ENOMEM;
  552. return 0;
  553. }
  554. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  555. {
  556. bitmap_free(id_tbl->table);
  557. id_tbl->table = NULL;
  558. }
  559. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  560. {
  561. int ret = -1;
  562. id -= id_tbl->start;
  563. if (id >= id_tbl->max)
  564. return ret;
  565. spin_lock(&id_tbl->lock);
  566. if (!test_bit(id, id_tbl->table)) {
  567. set_bit(id, id_tbl->table);
  568. ret = 0;
  569. }
  570. spin_unlock(&id_tbl->lock);
  571. return ret;
  572. }
  573. /* Returns -1 if not successful */
  574. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  575. {
  576. u32 id;
  577. spin_lock(&id_tbl->lock);
  578. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  579. if (id >= id_tbl->max) {
  580. id = -1;
  581. if (id_tbl->next != 0) {
  582. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  583. if (id >= id_tbl->next)
  584. id = -1;
  585. }
  586. }
  587. if (id < id_tbl->max) {
  588. set_bit(id, id_tbl->table);
  589. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  590. id += id_tbl->start;
  591. }
  592. spin_unlock(&id_tbl->lock);
  593. return id;
  594. }
  595. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  596. {
  597. if (id == -1)
  598. return;
  599. id -= id_tbl->start;
  600. if (id >= id_tbl->max)
  601. return;
  602. clear_bit(id, id_tbl->table);
  603. }
  604. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  605. {
  606. int i;
  607. if (!dma->pg_arr)
  608. return;
  609. for (i = 0; i < dma->num_pages; i++) {
  610. if (dma->pg_arr[i]) {
  611. dma_free_coherent(&dev->pcidev->dev, CNIC_PAGE_SIZE,
  612. dma->pg_arr[i], dma->pg_map_arr[i]);
  613. dma->pg_arr[i] = NULL;
  614. }
  615. }
  616. if (dma->pgtbl) {
  617. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  618. dma->pgtbl, dma->pgtbl_map);
  619. dma->pgtbl = NULL;
  620. }
  621. kfree(dma->pg_arr);
  622. dma->pg_arr = NULL;
  623. dma->num_pages = 0;
  624. }
  625. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  626. {
  627. int i;
  628. __le32 *page_table = (__le32 *) dma->pgtbl;
  629. for (i = 0; i < dma->num_pages; i++) {
  630. /* Each entry needs to be in big endian format. */
  631. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  632. page_table++;
  633. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  634. page_table++;
  635. }
  636. }
  637. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  638. {
  639. int i;
  640. __le32 *page_table = (__le32 *) dma->pgtbl;
  641. for (i = 0; i < dma->num_pages; i++) {
  642. /* Each entry needs to be in little endian format. */
  643. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  644. page_table++;
  645. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  646. page_table++;
  647. }
  648. }
  649. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  650. int pages, int use_pg_tbl)
  651. {
  652. int i, size;
  653. struct cnic_local *cp = dev->cnic_priv;
  654. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  655. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  656. if (dma->pg_arr == NULL)
  657. return -ENOMEM;
  658. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  659. dma->num_pages = pages;
  660. for (i = 0; i < pages; i++) {
  661. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  662. CNIC_PAGE_SIZE,
  663. &dma->pg_map_arr[i],
  664. GFP_ATOMIC);
  665. if (dma->pg_arr[i] == NULL)
  666. goto error;
  667. }
  668. if (!use_pg_tbl)
  669. return 0;
  670. dma->pgtbl_size = ((pages * 8) + CNIC_PAGE_SIZE - 1) &
  671. ~(CNIC_PAGE_SIZE - 1);
  672. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  673. &dma->pgtbl_map, GFP_ATOMIC);
  674. if (dma->pgtbl == NULL)
  675. goto error;
  676. cp->setup_pgtbl(dev, dma);
  677. return 0;
  678. error:
  679. cnic_free_dma(dev, dma);
  680. return -ENOMEM;
  681. }
  682. static void cnic_free_context(struct cnic_dev *dev)
  683. {
  684. struct cnic_local *cp = dev->cnic_priv;
  685. int i;
  686. for (i = 0; i < cp->ctx_blks; i++) {
  687. if (cp->ctx_arr[i].ctx) {
  688. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  689. cp->ctx_arr[i].ctx,
  690. cp->ctx_arr[i].mapping);
  691. cp->ctx_arr[i].ctx = NULL;
  692. }
  693. }
  694. }
  695. static void __cnic_free_uio_rings(struct cnic_uio_dev *udev)
  696. {
  697. if (udev->l2_buf) {
  698. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  699. udev->l2_buf, udev->l2_buf_map);
  700. udev->l2_buf = NULL;
  701. }
  702. if (udev->l2_ring) {
  703. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  704. udev->l2_ring, udev->l2_ring_map);
  705. udev->l2_ring = NULL;
  706. }
  707. }
  708. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  709. {
  710. uio_unregister_device(&udev->cnic_uinfo);
  711. __cnic_free_uio_rings(udev);
  712. pci_dev_put(udev->pdev);
  713. kfree(udev);
  714. }
  715. static void cnic_free_uio(struct cnic_uio_dev *udev)
  716. {
  717. if (!udev)
  718. return;
  719. write_lock(&cnic_dev_lock);
  720. list_del_init(&udev->list);
  721. write_unlock(&cnic_dev_lock);
  722. __cnic_free_uio(udev);
  723. }
  724. static void cnic_free_resc(struct cnic_dev *dev)
  725. {
  726. struct cnic_local *cp = dev->cnic_priv;
  727. struct cnic_uio_dev *udev = cp->udev;
  728. if (udev) {
  729. udev->dev = NULL;
  730. cp->udev = NULL;
  731. if (udev->uio_dev == -1)
  732. __cnic_free_uio_rings(udev);
  733. }
  734. cnic_free_context(dev);
  735. kfree(cp->ctx_arr);
  736. cp->ctx_arr = NULL;
  737. cp->ctx_blks = 0;
  738. cnic_free_dma(dev, &cp->gbl_buf_info);
  739. cnic_free_dma(dev, &cp->kwq_info);
  740. cnic_free_dma(dev, &cp->kwq_16_data_info);
  741. cnic_free_dma(dev, &cp->kcq2.dma);
  742. cnic_free_dma(dev, &cp->kcq1.dma);
  743. kfree(cp->iscsi_tbl);
  744. cp->iscsi_tbl = NULL;
  745. kfree(cp->ctx_tbl);
  746. cp->ctx_tbl = NULL;
  747. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  748. cnic_free_id_tbl(&cp->cid_tbl);
  749. }
  750. static int cnic_alloc_context(struct cnic_dev *dev)
  751. {
  752. struct cnic_local *cp = dev->cnic_priv;
  753. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  754. int i, k, arr_size;
  755. cp->ctx_blk_size = CNIC_PAGE_SIZE;
  756. cp->cids_per_blk = CNIC_PAGE_SIZE / 128;
  757. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  758. sizeof(struct cnic_ctx);
  759. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  760. if (cp->ctx_arr == NULL)
  761. return -ENOMEM;
  762. k = 0;
  763. for (i = 0; i < 2; i++) {
  764. u32 j, reg, off, lo, hi;
  765. if (i == 0)
  766. off = BNX2_PG_CTX_MAP;
  767. else
  768. off = BNX2_ISCSI_CTX_MAP;
  769. reg = cnic_reg_rd_ind(dev, off);
  770. lo = reg >> 16;
  771. hi = reg & 0xffff;
  772. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  773. cp->ctx_arr[k].cid = j;
  774. }
  775. cp->ctx_blks = k;
  776. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  777. cp->ctx_blks = 0;
  778. return -ENOMEM;
  779. }
  780. for (i = 0; i < cp->ctx_blks; i++) {
  781. cp->ctx_arr[i].ctx =
  782. dma_alloc_coherent(&dev->pcidev->dev,
  783. CNIC_PAGE_SIZE,
  784. &cp->ctx_arr[i].mapping,
  785. GFP_KERNEL);
  786. if (cp->ctx_arr[i].ctx == NULL)
  787. return -ENOMEM;
  788. }
  789. }
  790. return 0;
  791. }
  792. static u16 cnic_bnx2_next_idx(u16 idx)
  793. {
  794. return idx + 1;
  795. }
  796. static u16 cnic_bnx2_hw_idx(u16 idx)
  797. {
  798. return idx;
  799. }
  800. static u16 cnic_bnx2x_next_idx(u16 idx)
  801. {
  802. idx++;
  803. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  804. idx++;
  805. return idx;
  806. }
  807. static u16 cnic_bnx2x_hw_idx(u16 idx)
  808. {
  809. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  810. idx++;
  811. return idx;
  812. }
  813. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  814. bool use_pg_tbl)
  815. {
  816. int err, i, use_page_tbl = 0;
  817. struct kcqe **kcq;
  818. if (use_pg_tbl)
  819. use_page_tbl = 1;
  820. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  821. if (err)
  822. return err;
  823. kcq = (struct kcqe **) info->dma.pg_arr;
  824. info->kcq = kcq;
  825. info->next_idx = cnic_bnx2_next_idx;
  826. info->hw_idx = cnic_bnx2_hw_idx;
  827. if (use_pg_tbl)
  828. return 0;
  829. info->next_idx = cnic_bnx2x_next_idx;
  830. info->hw_idx = cnic_bnx2x_hw_idx;
  831. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  832. struct bnx2x_bd_chain_next *next =
  833. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  834. int j = i + 1;
  835. if (j >= KCQ_PAGE_CNT)
  836. j = 0;
  837. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  838. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  839. }
  840. return 0;
  841. }
  842. static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages)
  843. {
  844. struct cnic_local *cp = udev->dev->cnic_priv;
  845. if (udev->l2_ring)
  846. return 0;
  847. udev->l2_ring_size = pages * CNIC_PAGE_SIZE;
  848. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  849. &udev->l2_ring_map,
  850. GFP_KERNEL | __GFP_COMP);
  851. if (!udev->l2_ring)
  852. return -ENOMEM;
  853. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  854. udev->l2_buf_size = CNIC_PAGE_ALIGN(udev->l2_buf_size);
  855. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  856. &udev->l2_buf_map,
  857. GFP_KERNEL | __GFP_COMP);
  858. if (!udev->l2_buf) {
  859. __cnic_free_uio_rings(udev);
  860. return -ENOMEM;
  861. }
  862. return 0;
  863. }
  864. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  865. {
  866. struct cnic_local *cp = dev->cnic_priv;
  867. struct cnic_uio_dev *udev;
  868. list_for_each_entry(udev, &cnic_udev_list, list) {
  869. if (udev->pdev == dev->pcidev) {
  870. udev->dev = dev;
  871. if (__cnic_alloc_uio_rings(udev, pages)) {
  872. udev->dev = NULL;
  873. return -ENOMEM;
  874. }
  875. cp->udev = udev;
  876. return 0;
  877. }
  878. }
  879. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  880. if (!udev)
  881. return -ENOMEM;
  882. udev->uio_dev = -1;
  883. udev->dev = dev;
  884. udev->pdev = dev->pcidev;
  885. if (__cnic_alloc_uio_rings(udev, pages))
  886. goto err_udev;
  887. list_add(&udev->list, &cnic_udev_list);
  888. pci_dev_get(udev->pdev);
  889. cp->udev = udev;
  890. return 0;
  891. err_udev:
  892. kfree(udev);
  893. return -ENOMEM;
  894. }
  895. static int cnic_init_uio(struct cnic_dev *dev)
  896. {
  897. struct cnic_local *cp = dev->cnic_priv;
  898. struct cnic_uio_dev *udev = cp->udev;
  899. struct uio_info *uinfo;
  900. int ret = 0;
  901. if (!udev)
  902. return -ENOMEM;
  903. uinfo = &udev->cnic_uinfo;
  904. uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
  905. uinfo->mem[0].internal_addr = dev->regview;
  906. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  907. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  908. uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
  909. TX_MAX_TSS_RINGS + 1);
  910. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  911. CNIC_PAGE_MASK;
  912. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  913. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  914. else
  915. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  916. uinfo->name = "bnx2_cnic";
  917. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  918. uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
  919. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  920. CNIC_PAGE_MASK;
  921. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  922. uinfo->name = "bnx2x_cnic";
  923. }
  924. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  925. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  926. uinfo->mem[2].size = udev->l2_ring_size;
  927. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  928. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  929. uinfo->mem[3].size = udev->l2_buf_size;
  930. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  931. uinfo->version = CNIC_MODULE_VERSION;
  932. uinfo->irq = UIO_IRQ_CUSTOM;
  933. uinfo->open = cnic_uio_open;
  934. uinfo->release = cnic_uio_close;
  935. if (udev->uio_dev == -1) {
  936. if (!uinfo->priv) {
  937. uinfo->priv = udev;
  938. ret = uio_register_device(&udev->pdev->dev, uinfo);
  939. }
  940. } else {
  941. cnic_init_rings(dev);
  942. }
  943. return ret;
  944. }
  945. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  946. {
  947. struct cnic_local *cp = dev->cnic_priv;
  948. int ret;
  949. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  950. if (ret)
  951. goto error;
  952. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  953. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  954. if (ret)
  955. goto error;
  956. ret = cnic_alloc_context(dev);
  957. if (ret)
  958. goto error;
  959. ret = cnic_alloc_uio_rings(dev, 2);
  960. if (ret)
  961. goto error;
  962. ret = cnic_init_uio(dev);
  963. if (ret)
  964. goto error;
  965. return 0;
  966. error:
  967. cnic_free_resc(dev);
  968. return ret;
  969. }
  970. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  971. {
  972. struct cnic_local *cp = dev->cnic_priv;
  973. struct bnx2x *bp = netdev_priv(dev->netdev);
  974. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  975. int total_mem, blks, i;
  976. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  977. blks = total_mem / ctx_blk_size;
  978. if (total_mem % ctx_blk_size)
  979. blks++;
  980. if (blks > cp->ethdev->ctx_tbl_len)
  981. return -ENOMEM;
  982. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  983. if (cp->ctx_arr == NULL)
  984. return -ENOMEM;
  985. cp->ctx_blks = blks;
  986. cp->ctx_blk_size = ctx_blk_size;
  987. if (!CHIP_IS_E1(bp))
  988. cp->ctx_align = 0;
  989. else
  990. cp->ctx_align = ctx_blk_size;
  991. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  992. for (i = 0; i < blks; i++) {
  993. cp->ctx_arr[i].ctx =
  994. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  995. &cp->ctx_arr[i].mapping,
  996. GFP_KERNEL);
  997. if (cp->ctx_arr[i].ctx == NULL)
  998. return -ENOMEM;
  999. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  1000. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  1001. cnic_free_context(dev);
  1002. cp->ctx_blk_size += cp->ctx_align;
  1003. i = -1;
  1004. continue;
  1005. }
  1006. }
  1007. }
  1008. return 0;
  1009. }
  1010. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  1011. {
  1012. struct cnic_local *cp = dev->cnic_priv;
  1013. struct bnx2x *bp = netdev_priv(dev->netdev);
  1014. struct cnic_eth_dev *ethdev = cp->ethdev;
  1015. u32 start_cid = ethdev->starting_cid;
  1016. int i, j, n, ret, pages;
  1017. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  1018. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  1019. cp->iscsi_start_cid = start_cid;
  1020. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  1021. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  1022. cp->max_cid_space += dev->max_fcoe_conn;
  1023. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  1024. if (!cp->fcoe_init_cid)
  1025. cp->fcoe_init_cid = 0x10;
  1026. }
  1027. cp->iscsi_tbl = kcalloc(MAX_ISCSI_TBL_SZ, sizeof(struct cnic_iscsi),
  1028. GFP_KERNEL);
  1029. if (!cp->iscsi_tbl)
  1030. goto error;
  1031. cp->ctx_tbl = kcalloc(cp->max_cid_space, sizeof(struct cnic_context),
  1032. GFP_KERNEL);
  1033. if (!cp->ctx_tbl)
  1034. goto error;
  1035. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1036. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1037. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1038. }
  1039. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1040. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1041. pages = CNIC_PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1042. CNIC_PAGE_SIZE;
  1043. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1044. if (ret)
  1045. goto error;
  1046. n = CNIC_PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1047. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1048. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1049. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1050. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1051. off;
  1052. if ((i % n) == (n - 1))
  1053. j++;
  1054. }
  1055. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1056. if (ret)
  1057. goto error;
  1058. if (CNIC_SUPPORTS_FCOE(bp)) {
  1059. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1060. if (ret)
  1061. goto error;
  1062. }
  1063. pages = CNIC_PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / CNIC_PAGE_SIZE;
  1064. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1065. if (ret)
  1066. goto error;
  1067. ret = cnic_alloc_bnx2x_context(dev);
  1068. if (ret)
  1069. goto error;
  1070. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  1071. return 0;
  1072. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1073. cp->l2_rx_ring_size = 15;
  1074. ret = cnic_alloc_uio_rings(dev, 4);
  1075. if (ret)
  1076. goto error;
  1077. ret = cnic_init_uio(dev);
  1078. if (ret)
  1079. goto error;
  1080. return 0;
  1081. error:
  1082. cnic_free_resc(dev);
  1083. return -ENOMEM;
  1084. }
  1085. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1086. {
  1087. return cp->max_kwq_idx -
  1088. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1089. }
  1090. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1091. u32 num_wqes)
  1092. {
  1093. struct cnic_local *cp = dev->cnic_priv;
  1094. struct kwqe *prod_qe;
  1095. u16 prod, sw_prod, i;
  1096. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1097. return -EAGAIN; /* bnx2 is down */
  1098. spin_lock_bh(&cp->cnic_ulp_lock);
  1099. if (num_wqes > cnic_kwq_avail(cp) &&
  1100. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1101. spin_unlock_bh(&cp->cnic_ulp_lock);
  1102. return -EAGAIN;
  1103. }
  1104. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1105. prod = cp->kwq_prod_idx;
  1106. sw_prod = prod & MAX_KWQ_IDX;
  1107. for (i = 0; i < num_wqes; i++) {
  1108. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1109. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1110. prod++;
  1111. sw_prod = prod & MAX_KWQ_IDX;
  1112. }
  1113. cp->kwq_prod_idx = prod;
  1114. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1115. spin_unlock_bh(&cp->cnic_ulp_lock);
  1116. return 0;
  1117. }
  1118. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1119. union l5cm_specific_data *l5_data)
  1120. {
  1121. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1122. dma_addr_t map;
  1123. map = ctx->kwqe_data_mapping;
  1124. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1125. l5_data->phy_address.hi = (u64) map >> 32;
  1126. return ctx->kwqe_data;
  1127. }
  1128. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1129. u32 type, union l5cm_specific_data *l5_data)
  1130. {
  1131. struct cnic_local *cp = dev->cnic_priv;
  1132. struct bnx2x *bp = netdev_priv(dev->netdev);
  1133. struct l5cm_spe kwqe;
  1134. struct kwqe_16 *kwq[1];
  1135. u16 type_16;
  1136. int ret;
  1137. kwqe.hdr.conn_and_cmd_data =
  1138. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1139. BNX2X_HW_CID(bp, cid)));
  1140. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1141. type_16 |= (bp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1142. SPE_HDR_FUNCTION_ID;
  1143. kwqe.hdr.type = cpu_to_le16(type_16);
  1144. kwqe.hdr.reserved1 = 0;
  1145. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1146. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1147. kwq[0] = (struct kwqe_16 *) &kwqe;
  1148. spin_lock_bh(&cp->cnic_ulp_lock);
  1149. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1150. spin_unlock_bh(&cp->cnic_ulp_lock);
  1151. if (ret == 1)
  1152. return 0;
  1153. return ret;
  1154. }
  1155. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1156. struct kcqe *cqes[], u32 num_cqes)
  1157. {
  1158. struct cnic_local *cp = dev->cnic_priv;
  1159. struct cnic_ulp_ops *ulp_ops;
  1160. rcu_read_lock();
  1161. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1162. if (likely(ulp_ops)) {
  1163. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1164. cqes, num_cqes);
  1165. }
  1166. rcu_read_unlock();
  1167. }
  1168. static void cnic_bnx2x_set_tcp_options(struct cnic_dev *dev, int time_stamps,
  1169. int en_tcp_dack)
  1170. {
  1171. struct bnx2x *bp = netdev_priv(dev->netdev);
  1172. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1173. u16 tstorm_flags = 0;
  1174. if (time_stamps) {
  1175. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1176. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1177. }
  1178. if (en_tcp_dack)
  1179. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN;
  1180. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1181. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), xstorm_flags);
  1182. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1183. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), tstorm_flags);
  1184. }
  1185. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1186. {
  1187. struct cnic_local *cp = dev->cnic_priv;
  1188. struct bnx2x *bp = netdev_priv(dev->netdev);
  1189. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1190. int hq_bds, pages;
  1191. u32 pfid = bp->pfid;
  1192. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1193. cp->num_ccells = req1->num_ccells_per_conn;
  1194. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1195. cp->num_iscsi_tasks;
  1196. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1197. BNX2X_ISCSI_R2TQE_SIZE;
  1198. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1199. pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
  1200. hq_bds = pages * (CNIC_PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1201. cp->num_cqs = req1->num_cqs;
  1202. if (!dev->max_iscsi_conn)
  1203. return 0;
  1204. /* init Tstorm RAM */
  1205. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1206. req1->rq_num_wqes);
  1207. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1208. CNIC_PAGE_SIZE);
  1209. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1210. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1211. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1212. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1213. req1->num_tasks_per_conn);
  1214. /* init Ustorm RAM */
  1215. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1216. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1217. req1->rq_buffer_size);
  1218. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1219. CNIC_PAGE_SIZE);
  1220. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1221. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1222. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1223. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1224. req1->num_tasks_per_conn);
  1225. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1226. req1->rq_num_wqes);
  1227. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1228. req1->cq_num_wqes);
  1229. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1230. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1231. /* init Xstorm RAM */
  1232. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1233. CNIC_PAGE_SIZE);
  1234. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1235. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1236. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1237. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1238. req1->num_tasks_per_conn);
  1239. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1240. hq_bds);
  1241. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1242. req1->num_tasks_per_conn);
  1243. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1244. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1245. /* init Cstorm RAM */
  1246. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1247. CNIC_PAGE_SIZE);
  1248. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1249. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1250. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1251. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1252. req1->num_tasks_per_conn);
  1253. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1254. req1->cq_num_wqes);
  1255. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1256. hq_bds);
  1257. cnic_bnx2x_set_tcp_options(dev,
  1258. req1->flags & ISCSI_KWQE_INIT1_TIME_STAMPS_ENABLE,
  1259. req1->flags & ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE);
  1260. return 0;
  1261. }
  1262. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1263. {
  1264. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1265. struct bnx2x *bp = netdev_priv(dev->netdev);
  1266. u32 pfid = bp->pfid;
  1267. struct iscsi_kcqe kcqe;
  1268. struct kcqe *cqes[1];
  1269. memset(&kcqe, 0, sizeof(kcqe));
  1270. if (!dev->max_iscsi_conn) {
  1271. kcqe.completion_status =
  1272. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1273. goto done;
  1274. }
  1275. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1276. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1277. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1278. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1279. req2->error_bit_map[1]);
  1280. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1281. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1282. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1283. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1284. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1285. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1286. req2->error_bit_map[1]);
  1287. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1288. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1289. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1290. done:
  1291. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1292. cqes[0] = (struct kcqe *) &kcqe;
  1293. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1294. return 0;
  1295. }
  1296. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1297. {
  1298. struct cnic_local *cp = dev->cnic_priv;
  1299. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1300. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1301. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1302. cnic_free_dma(dev, &iscsi->hq_info);
  1303. cnic_free_dma(dev, &iscsi->r2tq_info);
  1304. cnic_free_dma(dev, &iscsi->task_array_info);
  1305. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1306. } else {
  1307. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1308. }
  1309. ctx->cid = 0;
  1310. }
  1311. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1312. {
  1313. u32 cid;
  1314. int ret, pages;
  1315. struct cnic_local *cp = dev->cnic_priv;
  1316. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1317. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1318. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1319. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1320. if (cid == -1) {
  1321. ret = -ENOMEM;
  1322. goto error;
  1323. }
  1324. ctx->cid = cid;
  1325. return 0;
  1326. }
  1327. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1328. if (cid == -1) {
  1329. ret = -ENOMEM;
  1330. goto error;
  1331. }
  1332. ctx->cid = cid;
  1333. pages = CNIC_PAGE_ALIGN(cp->task_array_size) / CNIC_PAGE_SIZE;
  1334. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1335. if (ret)
  1336. goto error;
  1337. pages = CNIC_PAGE_ALIGN(cp->r2tq_size) / CNIC_PAGE_SIZE;
  1338. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1339. if (ret)
  1340. goto error;
  1341. pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
  1342. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1343. if (ret)
  1344. goto error;
  1345. return 0;
  1346. error:
  1347. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1348. return ret;
  1349. }
  1350. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1351. struct regpair *ctx_addr)
  1352. {
  1353. struct cnic_local *cp = dev->cnic_priv;
  1354. struct cnic_eth_dev *ethdev = cp->ethdev;
  1355. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1356. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1357. unsigned long align_off = 0;
  1358. dma_addr_t ctx_map;
  1359. void *ctx;
  1360. if (cp->ctx_align) {
  1361. unsigned long mask = cp->ctx_align - 1;
  1362. if (cp->ctx_arr[blk].mapping & mask)
  1363. align_off = cp->ctx_align -
  1364. (cp->ctx_arr[blk].mapping & mask);
  1365. }
  1366. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1367. (off * BNX2X_CONTEXT_MEM_SIZE);
  1368. ctx = cp->ctx_arr[blk].ctx + align_off +
  1369. (off * BNX2X_CONTEXT_MEM_SIZE);
  1370. if (init)
  1371. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1372. ctx_addr->lo = ctx_map & 0xffffffff;
  1373. ctx_addr->hi = (u64) ctx_map >> 32;
  1374. return ctx;
  1375. }
  1376. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1377. u32 num)
  1378. {
  1379. struct cnic_local *cp = dev->cnic_priv;
  1380. struct bnx2x *bp = netdev_priv(dev->netdev);
  1381. struct iscsi_kwqe_conn_offload1 *req1 =
  1382. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1383. struct iscsi_kwqe_conn_offload2 *req2 =
  1384. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1385. struct iscsi_kwqe_conn_offload3 *req3;
  1386. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1387. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1388. u32 cid = ctx->cid;
  1389. u32 hw_cid = BNX2X_HW_CID(bp, cid);
  1390. struct iscsi_context *ictx;
  1391. struct regpair context_addr;
  1392. int i, j, n = 2, n_max;
  1393. u8 port = BP_PORT(bp);
  1394. ctx->ctx_flags = 0;
  1395. if (!req2->num_additional_wqes)
  1396. return -EINVAL;
  1397. n_max = req2->num_additional_wqes + 2;
  1398. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1399. if (ictx == NULL)
  1400. return -ENOMEM;
  1401. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1402. ictx->xstorm_ag_context.hq_prod = 1;
  1403. ictx->xstorm_st_context.iscsi.first_burst_length =
  1404. ISCSI_DEF_FIRST_BURST_LEN;
  1405. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1406. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1407. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1408. req1->sq_page_table_addr_lo;
  1409. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1410. req1->sq_page_table_addr_hi;
  1411. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1412. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1413. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1414. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1415. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1416. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1417. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1418. iscsi->hq_info.pgtbl[0];
  1419. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1420. iscsi->hq_info.pgtbl[1];
  1421. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1422. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1423. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1424. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1425. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1426. iscsi->r2tq_info.pgtbl[0];
  1427. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1428. iscsi->r2tq_info.pgtbl[1];
  1429. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1430. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1431. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1432. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1433. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1434. BNX2X_ISCSI_PBL_NOT_CACHED;
  1435. ictx->xstorm_st_context.iscsi.flags.flags |=
  1436. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1437. ictx->xstorm_st_context.iscsi.flags.flags |=
  1438. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1439. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1440. ETH_P_8021Q;
  1441. if (BNX2X_CHIP_IS_E2_PLUS(bp) &&
  1442. bp->common.chip_port_mode == CHIP_2_PORT_MODE) {
  1443. port = 0;
  1444. }
  1445. ictx->xstorm_st_context.common.flags =
  1446. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1447. ictx->xstorm_st_context.common.flags =
  1448. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1449. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1450. /* TSTORM requires the base address of RQ DB & not PTE */
  1451. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1452. req2->rq_page_table_addr_lo & CNIC_PAGE_MASK;
  1453. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1454. req2->rq_page_table_addr_hi;
  1455. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1456. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1457. ictx->tstorm_st_context.tcp.flags2 |=
  1458. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1459. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1460. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1461. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1462. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1463. req2->rq_page_table_addr_lo;
  1464. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1465. req2->rq_page_table_addr_hi;
  1466. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1467. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1468. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1469. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1470. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1471. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1472. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1473. iscsi->r2tq_info.pgtbl[0];
  1474. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1475. iscsi->r2tq_info.pgtbl[1];
  1476. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1477. req1->cq_page_table_addr_lo;
  1478. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1479. req1->cq_page_table_addr_hi;
  1480. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1481. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1482. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1483. ictx->ustorm_st_context.task_pbe_cache_index =
  1484. BNX2X_ISCSI_PBL_NOT_CACHED;
  1485. ictx->ustorm_st_context.task_pdu_cache_index =
  1486. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1487. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1488. if (j == 3) {
  1489. if (n >= n_max)
  1490. break;
  1491. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1492. j = 0;
  1493. }
  1494. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1495. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1496. req3->qp_first_pte[j].hi;
  1497. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1498. req3->qp_first_pte[j].lo;
  1499. }
  1500. ictx->ustorm_st_context.task_pbl_base.lo =
  1501. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1502. ictx->ustorm_st_context.task_pbl_base.hi =
  1503. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1504. ictx->ustorm_st_context.tce_phy_addr.lo =
  1505. iscsi->task_array_info.pgtbl[0];
  1506. ictx->ustorm_st_context.tce_phy_addr.hi =
  1507. iscsi->task_array_info.pgtbl[1];
  1508. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1509. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1510. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1511. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1512. ISCSI_DEF_MAX_BURST_LEN;
  1513. ictx->ustorm_st_context.negotiated_rx |=
  1514. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1515. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1516. ictx->cstorm_st_context.hq_pbl_base.lo =
  1517. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1518. ictx->cstorm_st_context.hq_pbl_base.hi =
  1519. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1520. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1521. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1522. ictx->cstorm_st_context.task_pbl_base.lo =
  1523. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1524. ictx->cstorm_st_context.task_pbl_base.hi =
  1525. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1526. /* CSTORM and USTORM initialization is different, CSTORM requires
  1527. * CQ DB base & not PTE addr */
  1528. ictx->cstorm_st_context.cq_db_base.lo =
  1529. req1->cq_page_table_addr_lo & CNIC_PAGE_MASK;
  1530. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1531. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1532. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1533. for (i = 0; i < cp->num_cqs; i++) {
  1534. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1535. ISCSI_INITIAL_SN;
  1536. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1537. ISCSI_INITIAL_SN;
  1538. }
  1539. ictx->xstorm_ag_context.cdu_reserved =
  1540. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1541. ISCSI_CONNECTION_TYPE);
  1542. ictx->ustorm_ag_context.cdu_usage =
  1543. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1544. ISCSI_CONNECTION_TYPE);
  1545. return 0;
  1546. }
  1547. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1548. u32 num, int *work)
  1549. {
  1550. struct iscsi_kwqe_conn_offload1 *req1;
  1551. struct iscsi_kwqe_conn_offload2 *req2;
  1552. struct cnic_local *cp = dev->cnic_priv;
  1553. struct bnx2x *bp = netdev_priv(dev->netdev);
  1554. struct cnic_context *ctx;
  1555. struct iscsi_kcqe kcqe;
  1556. struct kcqe *cqes[1];
  1557. u32 l5_cid;
  1558. int ret = 0;
  1559. if (num < 2) {
  1560. *work = num;
  1561. return -EINVAL;
  1562. }
  1563. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1564. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1565. if ((num - 2) < req2->num_additional_wqes) {
  1566. *work = num;
  1567. return -EINVAL;
  1568. }
  1569. *work = 2 + req2->num_additional_wqes;
  1570. l5_cid = req1->iscsi_conn_id;
  1571. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1572. return -EINVAL;
  1573. memset(&kcqe, 0, sizeof(kcqe));
  1574. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1575. kcqe.iscsi_conn_id = l5_cid;
  1576. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1577. ctx = &cp->ctx_tbl[l5_cid];
  1578. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1579. kcqe.completion_status =
  1580. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1581. goto done;
  1582. }
  1583. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1584. atomic_dec(&cp->iscsi_conn);
  1585. goto done;
  1586. }
  1587. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1588. if (ret) {
  1589. atomic_dec(&cp->iscsi_conn);
  1590. goto done;
  1591. }
  1592. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1593. if (ret < 0) {
  1594. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1595. atomic_dec(&cp->iscsi_conn);
  1596. goto done;
  1597. }
  1598. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1599. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(bp, cp->ctx_tbl[l5_cid].cid);
  1600. done:
  1601. cqes[0] = (struct kcqe *) &kcqe;
  1602. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1603. return 0;
  1604. }
  1605. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1606. {
  1607. struct cnic_local *cp = dev->cnic_priv;
  1608. struct iscsi_kwqe_conn_update *req =
  1609. (struct iscsi_kwqe_conn_update *) kwqe;
  1610. void *data;
  1611. union l5cm_specific_data l5_data;
  1612. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1613. int ret;
  1614. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1615. return -EINVAL;
  1616. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1617. if (!data)
  1618. return -ENOMEM;
  1619. memcpy(data, kwqe, sizeof(struct kwqe));
  1620. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1621. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1622. return ret;
  1623. }
  1624. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1625. {
  1626. struct cnic_local *cp = dev->cnic_priv;
  1627. struct bnx2x *bp = netdev_priv(dev->netdev);
  1628. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1629. union l5cm_specific_data l5_data;
  1630. int ret;
  1631. u32 hw_cid;
  1632. init_waitqueue_head(&ctx->waitq);
  1633. ctx->wait_cond = 0;
  1634. memset(&l5_data, 0, sizeof(l5_data));
  1635. hw_cid = BNX2X_HW_CID(bp, ctx->cid);
  1636. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1637. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1638. if (ret == 0) {
  1639. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1640. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1641. return -EBUSY;
  1642. }
  1643. return 0;
  1644. }
  1645. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1646. {
  1647. struct cnic_local *cp = dev->cnic_priv;
  1648. struct iscsi_kwqe_conn_destroy *req =
  1649. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1650. u32 l5_cid = req->reserved0;
  1651. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1652. int ret = 0;
  1653. struct iscsi_kcqe kcqe;
  1654. struct kcqe *cqes[1];
  1655. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1656. goto skip_cfc_delete;
  1657. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1658. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1659. if (delta > (2 * HZ))
  1660. delta = 0;
  1661. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1662. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1663. goto destroy_reply;
  1664. }
  1665. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1666. skip_cfc_delete:
  1667. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1668. if (!ret) {
  1669. atomic_dec(&cp->iscsi_conn);
  1670. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1671. }
  1672. destroy_reply:
  1673. memset(&kcqe, 0, sizeof(kcqe));
  1674. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1675. kcqe.iscsi_conn_id = l5_cid;
  1676. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1677. kcqe.iscsi_conn_context_id = req->context_id;
  1678. cqes[0] = (struct kcqe *) &kcqe;
  1679. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1680. return 0;
  1681. }
  1682. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1683. struct l4_kwq_connect_req1 *kwqe1,
  1684. struct l4_kwq_connect_req3 *kwqe3,
  1685. struct l5cm_active_conn_buffer *conn_buf)
  1686. {
  1687. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1688. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1689. &conn_buf->xstorm_conn_buffer;
  1690. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1691. &conn_buf->tstorm_conn_buffer;
  1692. struct regpair context_addr;
  1693. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1694. struct in6_addr src_ip, dst_ip;
  1695. int i;
  1696. u32 *addrp;
  1697. addrp = (u32 *) &conn_addr->local_ip_addr;
  1698. for (i = 0; i < 4; i++, addrp++)
  1699. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1700. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1701. for (i = 0; i < 4; i++, addrp++)
  1702. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1703. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1704. xstorm_buf->context_addr.hi = context_addr.hi;
  1705. xstorm_buf->context_addr.lo = context_addr.lo;
  1706. xstorm_buf->mss = 0xffff;
  1707. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1708. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1709. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1710. xstorm_buf->pseudo_header_checksum =
  1711. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1712. if (kwqe3->ka_timeout) {
  1713. tstorm_buf->ka_enable = 1;
  1714. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1715. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1716. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1717. }
  1718. tstorm_buf->max_rt_time = 0xffffffff;
  1719. }
  1720. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1721. {
  1722. struct bnx2x *bp = netdev_priv(dev->netdev);
  1723. u32 pfid = bp->pfid;
  1724. u8 *mac = dev->mac_addr;
  1725. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1726. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1727. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1728. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1729. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1730. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1731. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1732. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1733. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1734. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1735. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1736. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1737. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1738. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1739. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1740. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1741. mac[4]);
  1742. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1743. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1744. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1745. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1746. mac[2]);
  1747. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1748. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1749. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1750. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1751. mac[0]);
  1752. }
  1753. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1754. u32 num, int *work)
  1755. {
  1756. struct cnic_local *cp = dev->cnic_priv;
  1757. struct bnx2x *bp = netdev_priv(dev->netdev);
  1758. struct l4_kwq_connect_req1 *kwqe1 =
  1759. (struct l4_kwq_connect_req1 *) wqes[0];
  1760. struct l4_kwq_connect_req3 *kwqe3;
  1761. struct l5cm_active_conn_buffer *conn_buf;
  1762. struct l5cm_conn_addr_params *conn_addr;
  1763. union l5cm_specific_data l5_data;
  1764. u32 l5_cid = kwqe1->pg_cid;
  1765. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1766. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1767. int ret;
  1768. if (num < 2) {
  1769. *work = num;
  1770. return -EINVAL;
  1771. }
  1772. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1773. *work = 3;
  1774. else
  1775. *work = 2;
  1776. if (num < *work) {
  1777. *work = num;
  1778. return -EINVAL;
  1779. }
  1780. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1781. netdev_err(dev->netdev, "conn_buf size too big\n");
  1782. return -ENOMEM;
  1783. }
  1784. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1785. if (!conn_buf)
  1786. return -ENOMEM;
  1787. memset(conn_buf, 0, sizeof(*conn_buf));
  1788. conn_addr = &conn_buf->conn_addr_buf;
  1789. conn_addr->remote_addr_0 = csk->ha[0];
  1790. conn_addr->remote_addr_1 = csk->ha[1];
  1791. conn_addr->remote_addr_2 = csk->ha[2];
  1792. conn_addr->remote_addr_3 = csk->ha[3];
  1793. conn_addr->remote_addr_4 = csk->ha[4];
  1794. conn_addr->remote_addr_5 = csk->ha[5];
  1795. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1796. struct l4_kwq_connect_req2 *kwqe2 =
  1797. (struct l4_kwq_connect_req2 *) wqes[1];
  1798. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1799. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1800. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1801. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1802. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1803. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1804. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1805. }
  1806. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1807. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1808. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1809. conn_addr->local_tcp_port = kwqe1->src_port;
  1810. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1811. conn_addr->pmtu = kwqe3->pmtu;
  1812. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1813. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1814. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(bp->pfid), csk->vlan_id);
  1815. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1816. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1817. if (!ret)
  1818. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1819. return ret;
  1820. }
  1821. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1822. {
  1823. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1824. union l5cm_specific_data l5_data;
  1825. int ret;
  1826. memset(&l5_data, 0, sizeof(l5_data));
  1827. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1828. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1829. return ret;
  1830. }
  1831. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1832. {
  1833. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1834. union l5cm_specific_data l5_data;
  1835. int ret;
  1836. memset(&l5_data, 0, sizeof(l5_data));
  1837. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1838. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1839. return ret;
  1840. }
  1841. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1842. {
  1843. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1844. struct l4_kcq kcqe;
  1845. struct kcqe *cqes[1];
  1846. memset(&kcqe, 0, sizeof(kcqe));
  1847. kcqe.pg_host_opaque = req->host_opaque;
  1848. kcqe.pg_cid = req->host_opaque;
  1849. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1850. cqes[0] = (struct kcqe *) &kcqe;
  1851. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1852. return 0;
  1853. }
  1854. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1855. {
  1856. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1857. struct l4_kcq kcqe;
  1858. struct kcqe *cqes[1];
  1859. memset(&kcqe, 0, sizeof(kcqe));
  1860. kcqe.pg_host_opaque = req->pg_host_opaque;
  1861. kcqe.pg_cid = req->pg_cid;
  1862. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1863. cqes[0] = (struct kcqe *) &kcqe;
  1864. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1865. return 0;
  1866. }
  1867. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1868. {
  1869. struct fcoe_kwqe_stat *req;
  1870. struct fcoe_stat_ramrod_params *fcoe_stat;
  1871. union l5cm_specific_data l5_data;
  1872. struct cnic_local *cp = dev->cnic_priv;
  1873. struct bnx2x *bp = netdev_priv(dev->netdev);
  1874. int ret;
  1875. u32 cid;
  1876. req = (struct fcoe_kwqe_stat *) kwqe;
  1877. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  1878. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1879. if (!fcoe_stat)
  1880. return -ENOMEM;
  1881. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1882. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1883. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1884. FCOE_CONNECTION_TYPE, &l5_data);
  1885. return ret;
  1886. }
  1887. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1888. u32 num, int *work)
  1889. {
  1890. int ret;
  1891. struct cnic_local *cp = dev->cnic_priv;
  1892. struct bnx2x *bp = netdev_priv(dev->netdev);
  1893. u32 cid;
  1894. struct fcoe_init_ramrod_params *fcoe_init;
  1895. struct fcoe_kwqe_init1 *req1;
  1896. struct fcoe_kwqe_init2 *req2;
  1897. struct fcoe_kwqe_init3 *req3;
  1898. union l5cm_specific_data l5_data;
  1899. if (num < 3) {
  1900. *work = num;
  1901. return -EINVAL;
  1902. }
  1903. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1904. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1905. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1906. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1907. *work = 1;
  1908. return -EINVAL;
  1909. }
  1910. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1911. *work = 2;
  1912. return -EINVAL;
  1913. }
  1914. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1915. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1916. return -ENOMEM;
  1917. }
  1918. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1919. if (!fcoe_init)
  1920. return -ENOMEM;
  1921. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1922. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1923. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1924. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1925. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1926. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1927. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1928. fcoe_init->sb_num = cp->status_blk_num;
  1929. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1930. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1931. cp->kcq2.sw_prod_idx = 0;
  1932. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  1933. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1934. FCOE_CONNECTION_TYPE, &l5_data);
  1935. *work = 3;
  1936. return ret;
  1937. }
  1938. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1939. u32 num, int *work)
  1940. {
  1941. int ret = 0;
  1942. u32 cid = -1, l5_cid;
  1943. struct cnic_local *cp = dev->cnic_priv;
  1944. struct bnx2x *bp = netdev_priv(dev->netdev);
  1945. struct fcoe_kwqe_conn_offload1 *req1;
  1946. struct fcoe_kwqe_conn_offload2 *req2;
  1947. struct fcoe_kwqe_conn_offload3 *req3;
  1948. struct fcoe_kwqe_conn_offload4 *req4;
  1949. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1950. struct cnic_context *ctx;
  1951. struct fcoe_context *fctx;
  1952. struct regpair ctx_addr;
  1953. union l5cm_specific_data l5_data;
  1954. struct fcoe_kcqe kcqe;
  1955. struct kcqe *cqes[1];
  1956. if (num < 4) {
  1957. *work = num;
  1958. return -EINVAL;
  1959. }
  1960. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1961. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1962. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1963. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1964. *work = 4;
  1965. l5_cid = req1->fcoe_conn_id;
  1966. if (l5_cid >= dev->max_fcoe_conn)
  1967. goto err_reply;
  1968. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1969. ctx = &cp->ctx_tbl[l5_cid];
  1970. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1971. goto err_reply;
  1972. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1973. if (ret) {
  1974. ret = 0;
  1975. goto err_reply;
  1976. }
  1977. cid = ctx->cid;
  1978. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1979. if (fctx) {
  1980. u32 hw_cid = BNX2X_HW_CID(bp, cid);
  1981. u32 val;
  1982. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1983. FCOE_CONNECTION_TYPE);
  1984. fctx->xstorm_ag_context.cdu_reserved = val;
  1985. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1986. FCOE_CONNECTION_TYPE);
  1987. fctx->ustorm_ag_context.cdu_usage = val;
  1988. }
  1989. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1990. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1991. goto err_reply;
  1992. }
  1993. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1994. if (!fcoe_offload)
  1995. goto err_reply;
  1996. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1997. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1998. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1999. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  2000. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  2001. cid = BNX2X_HW_CID(bp, cid);
  2002. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  2003. FCOE_CONNECTION_TYPE, &l5_data);
  2004. if (!ret)
  2005. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  2006. return ret;
  2007. err_reply:
  2008. if (cid != -1)
  2009. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  2010. memset(&kcqe, 0, sizeof(kcqe));
  2011. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  2012. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  2013. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  2014. cqes[0] = (struct kcqe *) &kcqe;
  2015. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2016. return ret;
  2017. }
  2018. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  2019. {
  2020. struct fcoe_kwqe_conn_enable_disable *req;
  2021. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  2022. union l5cm_specific_data l5_data;
  2023. int ret;
  2024. u32 cid, l5_cid;
  2025. struct cnic_local *cp = dev->cnic_priv;
  2026. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2027. cid = req->context_id;
  2028. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  2029. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  2030. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  2031. return -ENOMEM;
  2032. }
  2033. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2034. if (!fcoe_enable)
  2035. return -ENOMEM;
  2036. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  2037. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  2038. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  2039. FCOE_CONNECTION_TYPE, &l5_data);
  2040. return ret;
  2041. }
  2042. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  2043. {
  2044. struct fcoe_kwqe_conn_enable_disable *req;
  2045. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  2046. union l5cm_specific_data l5_data;
  2047. int ret;
  2048. u32 cid, l5_cid;
  2049. struct cnic_local *cp = dev->cnic_priv;
  2050. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2051. cid = req->context_id;
  2052. l5_cid = req->conn_id;
  2053. if (l5_cid >= dev->max_fcoe_conn)
  2054. return -EINVAL;
  2055. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2056. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2057. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2058. return -ENOMEM;
  2059. }
  2060. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2061. if (!fcoe_disable)
  2062. return -ENOMEM;
  2063. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2064. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2065. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2066. FCOE_CONNECTION_TYPE, &l5_data);
  2067. return ret;
  2068. }
  2069. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2070. {
  2071. struct fcoe_kwqe_conn_destroy *req;
  2072. union l5cm_specific_data l5_data;
  2073. int ret;
  2074. u32 cid, l5_cid;
  2075. struct cnic_local *cp = dev->cnic_priv;
  2076. struct cnic_context *ctx;
  2077. struct fcoe_kcqe kcqe;
  2078. struct kcqe *cqes[1];
  2079. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2080. cid = req->context_id;
  2081. l5_cid = req->conn_id;
  2082. if (l5_cid >= dev->max_fcoe_conn)
  2083. return -EINVAL;
  2084. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2085. ctx = &cp->ctx_tbl[l5_cid];
  2086. init_waitqueue_head(&ctx->waitq);
  2087. ctx->wait_cond = 0;
  2088. memset(&kcqe, 0, sizeof(kcqe));
  2089. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2090. memset(&l5_data, 0, sizeof(l5_data));
  2091. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2092. FCOE_CONNECTION_TYPE, &l5_data);
  2093. if (ret == 0) {
  2094. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2095. if (ctx->wait_cond)
  2096. kcqe.completion_status = 0;
  2097. }
  2098. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2099. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2100. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2101. kcqe.fcoe_conn_id = req->conn_id;
  2102. kcqe.fcoe_conn_context_id = cid;
  2103. cqes[0] = (struct kcqe *) &kcqe;
  2104. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2105. return ret;
  2106. }
  2107. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2108. {
  2109. struct cnic_local *cp = dev->cnic_priv;
  2110. u32 i;
  2111. for (i = start_cid; i < cp->max_cid_space; i++) {
  2112. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2113. int j;
  2114. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2115. msleep(10);
  2116. for (j = 0; j < 5; j++) {
  2117. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2118. break;
  2119. msleep(20);
  2120. }
  2121. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2122. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2123. ctx->cid);
  2124. }
  2125. }
  2126. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2127. {
  2128. union l5cm_specific_data l5_data;
  2129. struct cnic_local *cp = dev->cnic_priv;
  2130. struct bnx2x *bp = netdev_priv(dev->netdev);
  2131. int ret;
  2132. u32 cid;
  2133. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2134. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  2135. memset(&l5_data, 0, sizeof(l5_data));
  2136. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2137. FCOE_CONNECTION_TYPE, &l5_data);
  2138. return ret;
  2139. }
  2140. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2141. {
  2142. struct cnic_local *cp = dev->cnic_priv;
  2143. struct kcqe kcqe;
  2144. struct kcqe *cqes[1];
  2145. u32 cid;
  2146. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2147. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2148. u32 kcqe_op;
  2149. int ulp_type;
  2150. cid = kwqe->kwqe_info0;
  2151. memset(&kcqe, 0, sizeof(kcqe));
  2152. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2153. u32 l5_cid = 0;
  2154. ulp_type = CNIC_ULP_FCOE;
  2155. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2156. struct fcoe_kwqe_conn_enable_disable *req;
  2157. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2158. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2159. cid = req->context_id;
  2160. l5_cid = req->conn_id;
  2161. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2162. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2163. } else {
  2164. return;
  2165. }
  2166. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2167. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2168. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2169. kcqe.kcqe_info2 = cid;
  2170. kcqe.kcqe_info0 = l5_cid;
  2171. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2172. ulp_type = CNIC_ULP_ISCSI;
  2173. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2174. cid = kwqe->kwqe_info1;
  2175. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2176. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2177. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2178. kcqe.kcqe_info2 = cid;
  2179. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2180. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2181. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2182. ulp_type = CNIC_ULP_L4;
  2183. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2184. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2185. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2186. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2187. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2188. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2189. else
  2190. return;
  2191. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2192. KCQE_FLAGS_LAYER_MASK_L4;
  2193. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2194. l4kcqe->cid = cid;
  2195. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2196. } else {
  2197. return;
  2198. }
  2199. cqes[0] = &kcqe;
  2200. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2201. }
  2202. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2203. struct kwqe *wqes[], u32 num_wqes)
  2204. {
  2205. int i, work, ret;
  2206. u32 opcode;
  2207. struct kwqe *kwqe;
  2208. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2209. return -EAGAIN; /* bnx2 is down */
  2210. for (i = 0; i < num_wqes; ) {
  2211. kwqe = wqes[i];
  2212. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2213. work = 1;
  2214. switch (opcode) {
  2215. case ISCSI_KWQE_OPCODE_INIT1:
  2216. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2217. break;
  2218. case ISCSI_KWQE_OPCODE_INIT2:
  2219. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2220. break;
  2221. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2222. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2223. num_wqes - i, &work);
  2224. break;
  2225. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2226. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2227. break;
  2228. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2229. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2230. break;
  2231. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2232. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2233. &work);
  2234. break;
  2235. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2236. ret = cnic_bnx2x_close(dev, kwqe);
  2237. break;
  2238. case L4_KWQE_OPCODE_VALUE_RESET:
  2239. ret = cnic_bnx2x_reset(dev, kwqe);
  2240. break;
  2241. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2242. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2243. break;
  2244. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2245. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2246. break;
  2247. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2248. ret = 0;
  2249. break;
  2250. default:
  2251. ret = 0;
  2252. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2253. opcode);
  2254. break;
  2255. }
  2256. if (ret < 0) {
  2257. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2258. opcode);
  2259. /* Possibly bnx2x parity error, send completion
  2260. * to ulp drivers with error code to speed up
  2261. * cleanup and reset recovery.
  2262. */
  2263. if (ret == -EIO || ret == -EAGAIN)
  2264. cnic_bnx2x_kwqe_err(dev, kwqe);
  2265. }
  2266. i += work;
  2267. }
  2268. return 0;
  2269. }
  2270. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2271. struct kwqe *wqes[], u32 num_wqes)
  2272. {
  2273. struct bnx2x *bp = netdev_priv(dev->netdev);
  2274. int i, work, ret;
  2275. u32 opcode;
  2276. struct kwqe *kwqe;
  2277. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2278. return -EAGAIN; /* bnx2 is down */
  2279. if (!BNX2X_CHIP_IS_E2_PLUS(bp))
  2280. return -EINVAL;
  2281. for (i = 0; i < num_wqes; ) {
  2282. kwqe = wqes[i];
  2283. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2284. work = 1;
  2285. switch (opcode) {
  2286. case FCOE_KWQE_OPCODE_INIT1:
  2287. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2288. num_wqes - i, &work);
  2289. break;
  2290. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2291. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2292. num_wqes - i, &work);
  2293. break;
  2294. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2295. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2296. break;
  2297. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2298. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2299. break;
  2300. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2301. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2302. break;
  2303. case FCOE_KWQE_OPCODE_DESTROY:
  2304. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2305. break;
  2306. case FCOE_KWQE_OPCODE_STAT:
  2307. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2308. break;
  2309. default:
  2310. ret = 0;
  2311. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2312. opcode);
  2313. break;
  2314. }
  2315. if (ret < 0) {
  2316. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2317. opcode);
  2318. /* Possibly bnx2x parity error, send completion
  2319. * to ulp drivers with error code to speed up
  2320. * cleanup and reset recovery.
  2321. */
  2322. if (ret == -EIO || ret == -EAGAIN)
  2323. cnic_bnx2x_kwqe_err(dev, kwqe);
  2324. }
  2325. i += work;
  2326. }
  2327. return 0;
  2328. }
  2329. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2330. u32 num_wqes)
  2331. {
  2332. int ret = -EINVAL;
  2333. u32 layer_code;
  2334. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2335. return -EAGAIN; /* bnx2x is down */
  2336. if (!num_wqes)
  2337. return 0;
  2338. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2339. switch (layer_code) {
  2340. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2341. case KWQE_FLAGS_LAYER_MASK_L4:
  2342. case KWQE_FLAGS_LAYER_MASK_L2:
  2343. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2344. break;
  2345. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2346. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2347. break;
  2348. }
  2349. return ret;
  2350. }
  2351. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2352. {
  2353. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2354. return KCQE_FLAGS_LAYER_MASK_L4;
  2355. return opflag & KCQE_FLAGS_LAYER_MASK;
  2356. }
  2357. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2358. {
  2359. struct cnic_local *cp = dev->cnic_priv;
  2360. int i, j, comp = 0;
  2361. i = 0;
  2362. j = 1;
  2363. while (num_cqes) {
  2364. struct cnic_ulp_ops *ulp_ops;
  2365. int ulp_type;
  2366. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2367. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2368. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2369. comp++;
  2370. while (j < num_cqes) {
  2371. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2372. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2373. break;
  2374. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2375. comp++;
  2376. j++;
  2377. }
  2378. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2379. ulp_type = CNIC_ULP_RDMA;
  2380. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2381. ulp_type = CNIC_ULP_ISCSI;
  2382. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2383. ulp_type = CNIC_ULP_FCOE;
  2384. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2385. ulp_type = CNIC_ULP_L4;
  2386. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2387. goto end;
  2388. else {
  2389. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2390. kcqe_op_flag);
  2391. goto end;
  2392. }
  2393. rcu_read_lock();
  2394. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2395. if (likely(ulp_ops)) {
  2396. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2397. cp->completed_kcq + i, j);
  2398. }
  2399. rcu_read_unlock();
  2400. end:
  2401. num_cqes -= j;
  2402. i += j;
  2403. j = 1;
  2404. }
  2405. if (unlikely(comp))
  2406. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2407. }
  2408. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2409. {
  2410. struct cnic_local *cp = dev->cnic_priv;
  2411. u16 i, ri, hw_prod, last;
  2412. struct kcqe *kcqe;
  2413. int kcqe_cnt = 0, last_cnt = 0;
  2414. i = ri = last = info->sw_prod_idx;
  2415. ri &= MAX_KCQ_IDX;
  2416. hw_prod = *info->hw_prod_idx_ptr;
  2417. hw_prod = info->hw_idx(hw_prod);
  2418. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2419. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2420. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2421. i = info->next_idx(i);
  2422. ri = i & MAX_KCQ_IDX;
  2423. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2424. last_cnt = kcqe_cnt;
  2425. last = i;
  2426. }
  2427. }
  2428. info->sw_prod_idx = last;
  2429. return last_cnt;
  2430. }
  2431. static int cnic_l2_completion(struct cnic_local *cp)
  2432. {
  2433. u16 hw_cons, sw_cons;
  2434. struct cnic_uio_dev *udev = cp->udev;
  2435. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2436. (udev->l2_ring + (2 * CNIC_PAGE_SIZE));
  2437. u32 cmd;
  2438. int comp = 0;
  2439. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2440. return 0;
  2441. hw_cons = *cp->rx_cons_ptr;
  2442. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2443. hw_cons++;
  2444. sw_cons = cp->rx_cons;
  2445. while (sw_cons != hw_cons) {
  2446. u8 cqe_fp_flags;
  2447. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2448. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2449. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2450. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2451. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2452. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2453. cmd == RAMROD_CMD_ID_ETH_HALT)
  2454. comp++;
  2455. }
  2456. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2457. }
  2458. return comp;
  2459. }
  2460. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2461. {
  2462. u16 rx_cons, tx_cons;
  2463. int comp = 0;
  2464. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2465. return;
  2466. rx_cons = *cp->rx_cons_ptr;
  2467. tx_cons = *cp->tx_cons_ptr;
  2468. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2469. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2470. comp = cnic_l2_completion(cp);
  2471. cp->tx_cons = tx_cons;
  2472. cp->rx_cons = rx_cons;
  2473. if (cp->udev)
  2474. uio_event_notify(&cp->udev->cnic_uinfo);
  2475. }
  2476. if (comp)
  2477. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2478. }
  2479. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2480. {
  2481. struct cnic_local *cp = dev->cnic_priv;
  2482. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2483. int kcqe_cnt;
  2484. /* status block index must be read before reading other fields */
  2485. rmb();
  2486. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2487. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2488. service_kcqes(dev, kcqe_cnt);
  2489. /* Tell compiler that status_blk fields can change. */
  2490. barrier();
  2491. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2492. /* status block index must be read first */
  2493. rmb();
  2494. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2495. }
  2496. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2497. cnic_chk_pkt_rings(cp);
  2498. return status_idx;
  2499. }
  2500. static int cnic_service_bnx2(void *data, void *status_blk)
  2501. {
  2502. struct cnic_dev *dev = data;
  2503. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2504. struct status_block *sblk = status_blk;
  2505. return sblk->status_idx;
  2506. }
  2507. return cnic_service_bnx2_queues(dev);
  2508. }
  2509. static void cnic_service_bnx2_msix(struct tasklet_struct *t)
  2510. {
  2511. struct cnic_local *cp = from_tasklet(cp, t, cnic_irq_task);
  2512. struct cnic_dev *dev = cp->dev;
  2513. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2514. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2515. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2516. }
  2517. static void cnic_doirq(struct cnic_dev *dev)
  2518. {
  2519. struct cnic_local *cp = dev->cnic_priv;
  2520. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2521. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2522. prefetch(cp->status_blk.gen);
  2523. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2524. tasklet_schedule(&cp->cnic_irq_task);
  2525. }
  2526. }
  2527. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2528. {
  2529. struct cnic_dev *dev = dev_instance;
  2530. struct cnic_local *cp = dev->cnic_priv;
  2531. if (cp->ack_int)
  2532. cp->ack_int(dev);
  2533. cnic_doirq(dev);
  2534. return IRQ_HANDLED;
  2535. }
  2536. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2537. u16 index, u8 op, u8 update)
  2538. {
  2539. struct bnx2x *bp = netdev_priv(dev->netdev);
  2540. u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp) * 32 +
  2541. COMMAND_REG_INT_ACK);
  2542. struct igu_ack_register igu_ack;
  2543. igu_ack.status_block_index = index;
  2544. igu_ack.sb_id_and_flags =
  2545. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2546. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2547. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2548. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2549. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2550. }
  2551. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2552. u16 index, u8 op, u8 update)
  2553. {
  2554. struct igu_regular cmd_data;
  2555. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2556. cmd_data.sb_id_and_flags =
  2557. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2558. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2559. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2560. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2561. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2562. }
  2563. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2564. {
  2565. struct cnic_local *cp = dev->cnic_priv;
  2566. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2567. IGU_INT_DISABLE, 0);
  2568. }
  2569. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2570. {
  2571. struct cnic_local *cp = dev->cnic_priv;
  2572. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2573. IGU_INT_DISABLE, 0);
  2574. }
  2575. static void cnic_arm_bnx2x_msix(struct cnic_dev *dev, u32 idx)
  2576. {
  2577. struct cnic_local *cp = dev->cnic_priv;
  2578. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, idx,
  2579. IGU_INT_ENABLE, 1);
  2580. }
  2581. static void cnic_arm_bnx2x_e2_msix(struct cnic_dev *dev, u32 idx)
  2582. {
  2583. struct cnic_local *cp = dev->cnic_priv;
  2584. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, idx,
  2585. IGU_INT_ENABLE, 1);
  2586. }
  2587. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2588. {
  2589. u32 last_status = *info->status_idx_ptr;
  2590. int kcqe_cnt;
  2591. /* status block index must be read before reading the KCQ */
  2592. rmb();
  2593. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2594. service_kcqes(dev, kcqe_cnt);
  2595. /* Tell compiler that sblk fields can change. */
  2596. barrier();
  2597. last_status = *info->status_idx_ptr;
  2598. /* status block index must be read before reading the KCQ */
  2599. rmb();
  2600. }
  2601. return last_status;
  2602. }
  2603. static void cnic_service_bnx2x_bh(struct tasklet_struct *t)
  2604. {
  2605. struct cnic_local *cp = from_tasklet(cp, t, cnic_irq_task);
  2606. struct cnic_dev *dev = cp->dev;
  2607. struct bnx2x *bp = netdev_priv(dev->netdev);
  2608. u32 status_idx, new_status_idx;
  2609. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2610. return;
  2611. while (1) {
  2612. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2613. CNIC_WR16(dev, cp->kcq1.io_addr,
  2614. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2615. if (!CNIC_SUPPORTS_FCOE(bp)) {
  2616. cp->arm_int(dev, status_idx);
  2617. break;
  2618. }
  2619. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2620. if (new_status_idx != status_idx)
  2621. continue;
  2622. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2623. MAX_KCQ_IDX);
  2624. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2625. status_idx, IGU_INT_ENABLE, 1);
  2626. break;
  2627. }
  2628. }
  2629. static int cnic_service_bnx2x(void *data, void *status_blk)
  2630. {
  2631. struct cnic_dev *dev = data;
  2632. struct cnic_local *cp = dev->cnic_priv;
  2633. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2634. cnic_doirq(dev);
  2635. cnic_chk_pkt_rings(cp);
  2636. return 0;
  2637. }
  2638. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2639. {
  2640. struct cnic_ulp_ops *ulp_ops;
  2641. if (if_type == CNIC_ULP_ISCSI)
  2642. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2643. mutex_lock(&cnic_lock);
  2644. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2645. lockdep_is_held(&cnic_lock));
  2646. if (!ulp_ops) {
  2647. mutex_unlock(&cnic_lock);
  2648. return;
  2649. }
  2650. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2651. mutex_unlock(&cnic_lock);
  2652. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2653. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2654. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2655. }
  2656. static void cnic_ulp_stop(struct cnic_dev *dev)
  2657. {
  2658. struct cnic_local *cp = dev->cnic_priv;
  2659. int if_type;
  2660. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2661. cnic_ulp_stop_one(cp, if_type);
  2662. }
  2663. static void cnic_ulp_start(struct cnic_dev *dev)
  2664. {
  2665. struct cnic_local *cp = dev->cnic_priv;
  2666. int if_type;
  2667. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2668. struct cnic_ulp_ops *ulp_ops;
  2669. mutex_lock(&cnic_lock);
  2670. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2671. lockdep_is_held(&cnic_lock));
  2672. if (!ulp_ops || !ulp_ops->cnic_start) {
  2673. mutex_unlock(&cnic_lock);
  2674. continue;
  2675. }
  2676. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2677. mutex_unlock(&cnic_lock);
  2678. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2679. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2680. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2681. }
  2682. }
  2683. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2684. {
  2685. struct cnic_local *cp = dev->cnic_priv;
  2686. struct cnic_ulp_ops *ulp_ops;
  2687. int rc;
  2688. mutex_lock(&cnic_lock);
  2689. ulp_ops = rcu_dereference_protected(cp->ulp_ops[ulp_type],
  2690. lockdep_is_held(&cnic_lock));
  2691. if (ulp_ops && ulp_ops->cnic_get_stats)
  2692. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2693. else
  2694. rc = -ENODEV;
  2695. mutex_unlock(&cnic_lock);
  2696. return rc;
  2697. }
  2698. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2699. {
  2700. struct cnic_dev *dev = data;
  2701. int ulp_type = CNIC_ULP_ISCSI;
  2702. switch (info->cmd) {
  2703. case CNIC_CTL_STOP_CMD:
  2704. cnic_hold(dev);
  2705. cnic_ulp_stop(dev);
  2706. cnic_stop_hw(dev);
  2707. cnic_put(dev);
  2708. break;
  2709. case CNIC_CTL_START_CMD:
  2710. cnic_hold(dev);
  2711. if (!cnic_start_hw(dev))
  2712. cnic_ulp_start(dev);
  2713. cnic_put(dev);
  2714. break;
  2715. case CNIC_CTL_STOP_ISCSI_CMD: {
  2716. struct cnic_local *cp = dev->cnic_priv;
  2717. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2718. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2719. break;
  2720. }
  2721. case CNIC_CTL_COMPLETION_CMD: {
  2722. struct cnic_ctl_completion *comp = &info->data.comp;
  2723. u32 cid = BNX2X_SW_CID(comp->cid);
  2724. u32 l5_cid;
  2725. struct cnic_local *cp = dev->cnic_priv;
  2726. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2727. break;
  2728. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2729. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2730. if (unlikely(comp->error)) {
  2731. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2732. netdev_err(dev->netdev,
  2733. "CID %x CFC delete comp error %x\n",
  2734. cid, comp->error);
  2735. }
  2736. ctx->wait_cond = 1;
  2737. wake_up(&ctx->waitq);
  2738. }
  2739. break;
  2740. }
  2741. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2742. ulp_type = CNIC_ULP_FCOE;
  2743. fallthrough;
  2744. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2745. cnic_hold(dev);
  2746. cnic_copy_ulp_stats(dev, ulp_type);
  2747. cnic_put(dev);
  2748. break;
  2749. default:
  2750. return -EINVAL;
  2751. }
  2752. return 0;
  2753. }
  2754. static void cnic_ulp_init(struct cnic_dev *dev)
  2755. {
  2756. int i;
  2757. struct cnic_local *cp = dev->cnic_priv;
  2758. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2759. struct cnic_ulp_ops *ulp_ops;
  2760. mutex_lock(&cnic_lock);
  2761. ulp_ops = cnic_ulp_tbl_prot(i);
  2762. if (!ulp_ops || !ulp_ops->cnic_init) {
  2763. mutex_unlock(&cnic_lock);
  2764. continue;
  2765. }
  2766. ulp_get(ulp_ops);
  2767. mutex_unlock(&cnic_lock);
  2768. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2769. ulp_ops->cnic_init(dev);
  2770. ulp_put(ulp_ops);
  2771. }
  2772. }
  2773. static void cnic_ulp_exit(struct cnic_dev *dev)
  2774. {
  2775. int i;
  2776. struct cnic_local *cp = dev->cnic_priv;
  2777. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2778. struct cnic_ulp_ops *ulp_ops;
  2779. mutex_lock(&cnic_lock);
  2780. ulp_ops = cnic_ulp_tbl_prot(i);
  2781. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2782. mutex_unlock(&cnic_lock);
  2783. continue;
  2784. }
  2785. ulp_get(ulp_ops);
  2786. mutex_unlock(&cnic_lock);
  2787. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2788. ulp_ops->cnic_exit(dev);
  2789. ulp_put(ulp_ops);
  2790. }
  2791. }
  2792. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2793. {
  2794. struct cnic_dev *dev = csk->dev;
  2795. struct l4_kwq_offload_pg *l4kwqe;
  2796. struct kwqe *wqes[1];
  2797. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2798. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2799. wqes[0] = (struct kwqe *) l4kwqe;
  2800. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2801. l4kwqe->flags =
  2802. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2803. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2804. l4kwqe->da0 = csk->ha[0];
  2805. l4kwqe->da1 = csk->ha[1];
  2806. l4kwqe->da2 = csk->ha[2];
  2807. l4kwqe->da3 = csk->ha[3];
  2808. l4kwqe->da4 = csk->ha[4];
  2809. l4kwqe->da5 = csk->ha[5];
  2810. l4kwqe->sa0 = dev->mac_addr[0];
  2811. l4kwqe->sa1 = dev->mac_addr[1];
  2812. l4kwqe->sa2 = dev->mac_addr[2];
  2813. l4kwqe->sa3 = dev->mac_addr[3];
  2814. l4kwqe->sa4 = dev->mac_addr[4];
  2815. l4kwqe->sa5 = dev->mac_addr[5];
  2816. l4kwqe->etype = ETH_P_IP;
  2817. l4kwqe->ipid_start = DEF_IPID_START;
  2818. l4kwqe->host_opaque = csk->l5_cid;
  2819. if (csk->vlan_id) {
  2820. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2821. l4kwqe->vlan_tag = csk->vlan_id;
  2822. l4kwqe->l2hdr_nbytes += 4;
  2823. }
  2824. return dev->submit_kwqes(dev, wqes, 1);
  2825. }
  2826. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2827. {
  2828. struct cnic_dev *dev = csk->dev;
  2829. struct l4_kwq_update_pg *l4kwqe;
  2830. struct kwqe *wqes[1];
  2831. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2832. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2833. wqes[0] = (struct kwqe *) l4kwqe;
  2834. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2835. l4kwqe->flags =
  2836. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2837. l4kwqe->pg_cid = csk->pg_cid;
  2838. l4kwqe->da0 = csk->ha[0];
  2839. l4kwqe->da1 = csk->ha[1];
  2840. l4kwqe->da2 = csk->ha[2];
  2841. l4kwqe->da3 = csk->ha[3];
  2842. l4kwqe->da4 = csk->ha[4];
  2843. l4kwqe->da5 = csk->ha[5];
  2844. l4kwqe->pg_host_opaque = csk->l5_cid;
  2845. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2846. return dev->submit_kwqes(dev, wqes, 1);
  2847. }
  2848. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2849. {
  2850. struct cnic_dev *dev = csk->dev;
  2851. struct l4_kwq_upload *l4kwqe;
  2852. struct kwqe *wqes[1];
  2853. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2854. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2855. wqes[0] = (struct kwqe *) l4kwqe;
  2856. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2857. l4kwqe->flags =
  2858. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2859. l4kwqe->cid = csk->pg_cid;
  2860. return dev->submit_kwqes(dev, wqes, 1);
  2861. }
  2862. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2863. {
  2864. struct cnic_dev *dev = csk->dev;
  2865. struct l4_kwq_connect_req1 *l4kwqe1;
  2866. struct l4_kwq_connect_req2 *l4kwqe2;
  2867. struct l4_kwq_connect_req3 *l4kwqe3;
  2868. struct kwqe *wqes[3];
  2869. u8 tcp_flags = 0;
  2870. int num_wqes = 2;
  2871. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2872. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2873. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2874. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2875. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2876. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2877. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2878. l4kwqe3->flags =
  2879. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2880. l4kwqe3->ka_timeout = csk->ka_timeout;
  2881. l4kwqe3->ka_interval = csk->ka_interval;
  2882. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2883. l4kwqe3->tos = csk->tos;
  2884. l4kwqe3->ttl = csk->ttl;
  2885. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2886. l4kwqe3->pmtu = csk->mtu;
  2887. l4kwqe3->rcv_buf = csk->rcv_buf;
  2888. l4kwqe3->snd_buf = csk->snd_buf;
  2889. l4kwqe3->seed = csk->seed;
  2890. wqes[0] = (struct kwqe *) l4kwqe1;
  2891. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2892. wqes[1] = (struct kwqe *) l4kwqe2;
  2893. wqes[2] = (struct kwqe *) l4kwqe3;
  2894. num_wqes = 3;
  2895. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2896. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2897. l4kwqe2->flags =
  2898. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2899. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2900. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2901. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2902. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2903. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2904. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2905. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2906. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2907. sizeof(struct tcphdr);
  2908. } else {
  2909. wqes[1] = (struct kwqe *) l4kwqe3;
  2910. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2911. sizeof(struct tcphdr);
  2912. }
  2913. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2914. l4kwqe1->flags =
  2915. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2916. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2917. l4kwqe1->cid = csk->cid;
  2918. l4kwqe1->pg_cid = csk->pg_cid;
  2919. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2920. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2921. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2922. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2923. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2924. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2925. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2926. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2927. if (csk->tcp_flags & SK_TCP_NAGLE)
  2928. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2929. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2930. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2931. if (csk->tcp_flags & SK_TCP_SACK)
  2932. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2933. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2934. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2935. l4kwqe1->tcp_flags = tcp_flags;
  2936. return dev->submit_kwqes(dev, wqes, num_wqes);
  2937. }
  2938. static int cnic_cm_close_req(struct cnic_sock *csk)
  2939. {
  2940. struct cnic_dev *dev = csk->dev;
  2941. struct l4_kwq_close_req *l4kwqe;
  2942. struct kwqe *wqes[1];
  2943. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2944. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2945. wqes[0] = (struct kwqe *) l4kwqe;
  2946. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2947. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2948. l4kwqe->cid = csk->cid;
  2949. return dev->submit_kwqes(dev, wqes, 1);
  2950. }
  2951. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2952. {
  2953. struct cnic_dev *dev = csk->dev;
  2954. struct l4_kwq_reset_req *l4kwqe;
  2955. struct kwqe *wqes[1];
  2956. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2957. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2958. wqes[0] = (struct kwqe *) l4kwqe;
  2959. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2960. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2961. l4kwqe->cid = csk->cid;
  2962. return dev->submit_kwqes(dev, wqes, 1);
  2963. }
  2964. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2965. u32 l5_cid, struct cnic_sock **csk, void *context)
  2966. {
  2967. struct cnic_local *cp = dev->cnic_priv;
  2968. struct cnic_sock *csk1;
  2969. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2970. return -EINVAL;
  2971. if (cp->ctx_tbl) {
  2972. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2973. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2974. return -EAGAIN;
  2975. }
  2976. csk1 = &cp->csk_tbl[l5_cid];
  2977. if (atomic_read(&csk1->ref_count))
  2978. return -EAGAIN;
  2979. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2980. return -EBUSY;
  2981. csk1->dev = dev;
  2982. csk1->cid = cid;
  2983. csk1->l5_cid = l5_cid;
  2984. csk1->ulp_type = ulp_type;
  2985. csk1->context = context;
  2986. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2987. csk1->ka_interval = DEF_KA_INTERVAL;
  2988. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2989. csk1->tos = DEF_TOS;
  2990. csk1->ttl = DEF_TTL;
  2991. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2992. csk1->rcv_buf = DEF_RCV_BUF;
  2993. csk1->snd_buf = DEF_SND_BUF;
  2994. csk1->seed = DEF_SEED;
  2995. csk1->tcp_flags = 0;
  2996. *csk = csk1;
  2997. return 0;
  2998. }
  2999. static void cnic_cm_cleanup(struct cnic_sock *csk)
  3000. {
  3001. if (csk->src_port) {
  3002. struct cnic_dev *dev = csk->dev;
  3003. struct cnic_local *cp = dev->cnic_priv;
  3004. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  3005. csk->src_port = 0;
  3006. }
  3007. }
  3008. static void cnic_close_conn(struct cnic_sock *csk)
  3009. {
  3010. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  3011. cnic_cm_upload_pg(csk);
  3012. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3013. }
  3014. cnic_cm_cleanup(csk);
  3015. }
  3016. static int cnic_cm_destroy(struct cnic_sock *csk)
  3017. {
  3018. if (!cnic_in_use(csk))
  3019. return -EINVAL;
  3020. csk_hold(csk);
  3021. clear_bit(SK_F_INUSE, &csk->flags);
  3022. smp_mb__after_atomic();
  3023. while (atomic_read(&csk->ref_count) != 1)
  3024. msleep(1);
  3025. cnic_cm_cleanup(csk);
  3026. csk->flags = 0;
  3027. csk_put(csk);
  3028. return 0;
  3029. }
  3030. static inline u16 cnic_get_vlan(struct net_device *dev,
  3031. struct net_device **vlan_dev)
  3032. {
  3033. if (is_vlan_dev(dev)) {
  3034. *vlan_dev = vlan_dev_real_dev(dev);
  3035. return vlan_dev_vlan_id(dev);
  3036. }
  3037. *vlan_dev = dev;
  3038. return 0;
  3039. }
  3040. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  3041. struct dst_entry **dst)
  3042. {
  3043. #if defined(CONFIG_INET)
  3044. struct rtable *rt;
  3045. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  3046. if (!IS_ERR(rt)) {
  3047. *dst = &rt->dst;
  3048. return 0;
  3049. }
  3050. return PTR_ERR(rt);
  3051. #else
  3052. return -ENETUNREACH;
  3053. #endif
  3054. }
  3055. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  3056. struct dst_entry **dst)
  3057. {
  3058. #if IS_ENABLED(CONFIG_IPV6)
  3059. struct flowi6 fl6;
  3060. memset(&fl6, 0, sizeof(fl6));
  3061. fl6.daddr = dst_addr->sin6_addr;
  3062. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3063. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3064. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3065. if ((*dst)->error) {
  3066. dst_release(*dst);
  3067. *dst = NULL;
  3068. return -ENETUNREACH;
  3069. } else
  3070. return 0;
  3071. #endif
  3072. return -ENETUNREACH;
  3073. }
  3074. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3075. int ulp_type)
  3076. {
  3077. struct cnic_dev *dev = NULL;
  3078. struct dst_entry *dst;
  3079. struct net_device *netdev = NULL;
  3080. int err = -ENETUNREACH;
  3081. if (dst_addr->sin_family == AF_INET)
  3082. err = cnic_get_v4_route(dst_addr, &dst);
  3083. else if (dst_addr->sin_family == AF_INET6) {
  3084. struct sockaddr_in6 *dst_addr6 =
  3085. (struct sockaddr_in6 *) dst_addr;
  3086. err = cnic_get_v6_route(dst_addr6, &dst);
  3087. } else
  3088. return NULL;
  3089. if (err)
  3090. return NULL;
  3091. if (!dst->dev)
  3092. goto done;
  3093. cnic_get_vlan(dst->dev, &netdev);
  3094. dev = cnic_from_netdev(netdev);
  3095. done:
  3096. dst_release(dst);
  3097. if (dev)
  3098. cnic_put(dev);
  3099. return dev;
  3100. }
  3101. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3102. {
  3103. struct cnic_dev *dev = csk->dev;
  3104. struct cnic_local *cp = dev->cnic_priv;
  3105. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3106. }
  3107. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3108. {
  3109. struct cnic_dev *dev = csk->dev;
  3110. struct cnic_local *cp = dev->cnic_priv;
  3111. int is_v6, rc = 0;
  3112. struct dst_entry *dst = NULL;
  3113. struct net_device *realdev;
  3114. __be16 local_port;
  3115. u32 port_id;
  3116. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3117. saddr->remote.v6.sin6_family == AF_INET6)
  3118. is_v6 = 1;
  3119. else if (saddr->local.v4.sin_family == AF_INET &&
  3120. saddr->remote.v4.sin_family == AF_INET)
  3121. is_v6 = 0;
  3122. else
  3123. return -EINVAL;
  3124. clear_bit(SK_F_IPV6, &csk->flags);
  3125. if (is_v6) {
  3126. set_bit(SK_F_IPV6, &csk->flags);
  3127. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3128. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3129. sizeof(struct in6_addr));
  3130. csk->dst_port = saddr->remote.v6.sin6_port;
  3131. local_port = saddr->local.v6.sin6_port;
  3132. } else {
  3133. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3134. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3135. csk->dst_port = saddr->remote.v4.sin_port;
  3136. local_port = saddr->local.v4.sin_port;
  3137. }
  3138. csk->vlan_id = 0;
  3139. csk->mtu = dev->netdev->mtu;
  3140. if (dst && dst->dev) {
  3141. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3142. if (realdev == dev->netdev) {
  3143. csk->vlan_id = vlan;
  3144. csk->mtu = dst_mtu(dst);
  3145. }
  3146. }
  3147. port_id = be16_to_cpu(local_port);
  3148. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3149. port_id < CNIC_LOCAL_PORT_MAX) {
  3150. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3151. port_id = 0;
  3152. } else
  3153. port_id = 0;
  3154. if (!port_id) {
  3155. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3156. if (port_id == -1) {
  3157. rc = -ENOMEM;
  3158. goto err_out;
  3159. }
  3160. local_port = cpu_to_be16(port_id);
  3161. }
  3162. csk->src_port = local_port;
  3163. err_out:
  3164. dst_release(dst);
  3165. return rc;
  3166. }
  3167. static void cnic_init_csk_state(struct cnic_sock *csk)
  3168. {
  3169. csk->state = 0;
  3170. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3171. clear_bit(SK_F_CLOSING, &csk->flags);
  3172. }
  3173. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3174. {
  3175. struct cnic_local *cp = csk->dev->cnic_priv;
  3176. int err = 0;
  3177. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3178. return -EOPNOTSUPP;
  3179. if (!cnic_in_use(csk))
  3180. return -EINVAL;
  3181. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3182. return -EINVAL;
  3183. cnic_init_csk_state(csk);
  3184. err = cnic_get_route(csk, saddr);
  3185. if (err)
  3186. goto err_out;
  3187. err = cnic_resolve_addr(csk, saddr);
  3188. if (!err)
  3189. return 0;
  3190. err_out:
  3191. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3192. return err;
  3193. }
  3194. static int cnic_cm_abort(struct cnic_sock *csk)
  3195. {
  3196. struct cnic_local *cp = csk->dev->cnic_priv;
  3197. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3198. if (!cnic_in_use(csk))
  3199. return -EINVAL;
  3200. if (cnic_abort_prep(csk))
  3201. return cnic_cm_abort_req(csk);
  3202. /* Getting here means that we haven't started connect, or
  3203. * connect was not successful, or it has been reset by the target.
  3204. */
  3205. cp->close_conn(csk, opcode);
  3206. if (csk->state != opcode) {
  3207. /* Wait for remote reset sequence to complete */
  3208. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3209. msleep(1);
  3210. return -EALREADY;
  3211. }
  3212. return 0;
  3213. }
  3214. static int cnic_cm_close(struct cnic_sock *csk)
  3215. {
  3216. if (!cnic_in_use(csk))
  3217. return -EINVAL;
  3218. if (cnic_close_prep(csk)) {
  3219. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3220. return cnic_cm_close_req(csk);
  3221. } else {
  3222. /* Wait for remote reset sequence to complete */
  3223. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3224. msleep(1);
  3225. return -EALREADY;
  3226. }
  3227. return 0;
  3228. }
  3229. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3230. u8 opcode)
  3231. {
  3232. struct cnic_ulp_ops *ulp_ops;
  3233. int ulp_type = csk->ulp_type;
  3234. rcu_read_lock();
  3235. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3236. if (ulp_ops) {
  3237. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3238. ulp_ops->cm_connect_complete(csk);
  3239. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3240. ulp_ops->cm_close_complete(csk);
  3241. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3242. ulp_ops->cm_remote_abort(csk);
  3243. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3244. ulp_ops->cm_abort_complete(csk);
  3245. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3246. ulp_ops->cm_remote_close(csk);
  3247. }
  3248. rcu_read_unlock();
  3249. }
  3250. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3251. {
  3252. if (cnic_offld_prep(csk)) {
  3253. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3254. cnic_cm_update_pg(csk);
  3255. else
  3256. cnic_cm_offload_pg(csk);
  3257. }
  3258. return 0;
  3259. }
  3260. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3261. {
  3262. struct cnic_local *cp = dev->cnic_priv;
  3263. u32 l5_cid = kcqe->pg_host_opaque;
  3264. u8 opcode = kcqe->op_code;
  3265. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3266. csk_hold(csk);
  3267. if (!cnic_in_use(csk))
  3268. goto done;
  3269. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3270. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3271. goto done;
  3272. }
  3273. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3274. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3275. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3276. cnic_cm_upcall(cp, csk,
  3277. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3278. goto done;
  3279. }
  3280. csk->pg_cid = kcqe->pg_cid;
  3281. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3282. cnic_cm_conn_req(csk);
  3283. done:
  3284. csk_put(csk);
  3285. }
  3286. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3287. {
  3288. struct cnic_local *cp = dev->cnic_priv;
  3289. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3290. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3291. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3292. ctx->timestamp = jiffies;
  3293. ctx->wait_cond = 1;
  3294. wake_up(&ctx->waitq);
  3295. }
  3296. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3297. {
  3298. struct cnic_local *cp = dev->cnic_priv;
  3299. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3300. u8 opcode = l4kcqe->op_code;
  3301. u32 l5_cid;
  3302. struct cnic_sock *csk;
  3303. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3304. cnic_process_fcoe_term_conn(dev, kcqe);
  3305. return;
  3306. }
  3307. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3308. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3309. cnic_cm_process_offld_pg(dev, l4kcqe);
  3310. return;
  3311. }
  3312. l5_cid = l4kcqe->conn_id;
  3313. if (opcode & 0x80)
  3314. l5_cid = l4kcqe->cid;
  3315. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3316. return;
  3317. csk = &cp->csk_tbl[l5_cid];
  3318. csk_hold(csk);
  3319. if (!cnic_in_use(csk)) {
  3320. csk_put(csk);
  3321. return;
  3322. }
  3323. switch (opcode) {
  3324. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3325. if (l4kcqe->status != 0) {
  3326. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3327. cnic_cm_upcall(cp, csk,
  3328. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3329. }
  3330. break;
  3331. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3332. if (l4kcqe->status == 0)
  3333. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3334. else if (l4kcqe->status ==
  3335. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3336. set_bit(SK_F_HW_ERR, &csk->flags);
  3337. smp_mb__before_atomic();
  3338. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3339. cnic_cm_upcall(cp, csk, opcode);
  3340. break;
  3341. case L5CM_RAMROD_CMD_ID_CLOSE: {
  3342. struct iscsi_kcqe *l5kcqe = (struct iscsi_kcqe *) kcqe;
  3343. if (l4kcqe->status == 0 && l5kcqe->completion_status == 0)
  3344. break;
  3345. netdev_warn(dev->netdev, "RAMROD CLOSE compl with status 0x%x completion status 0x%x\n",
  3346. l4kcqe->status, l5kcqe->completion_status);
  3347. opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3348. }
  3349. fallthrough;
  3350. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3351. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3352. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3353. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3354. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3355. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3356. set_bit(SK_F_HW_ERR, &csk->flags);
  3357. cp->close_conn(csk, opcode);
  3358. break;
  3359. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3360. /* after we already sent CLOSE_REQ */
  3361. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3362. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3363. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3364. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3365. else
  3366. cnic_cm_upcall(cp, csk, opcode);
  3367. break;
  3368. }
  3369. csk_put(csk);
  3370. }
  3371. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3372. {
  3373. struct cnic_dev *dev = data;
  3374. int i;
  3375. for (i = 0; i < num; i++)
  3376. cnic_cm_process_kcqe(dev, kcqe[i]);
  3377. }
  3378. static struct cnic_ulp_ops cm_ulp_ops = {
  3379. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3380. };
  3381. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3382. {
  3383. struct cnic_local *cp = dev->cnic_priv;
  3384. kvfree(cp->csk_tbl);
  3385. cp->csk_tbl = NULL;
  3386. cnic_free_id_tbl(&cp->csk_port_tbl);
  3387. }
  3388. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3389. {
  3390. struct cnic_local *cp = dev->cnic_priv;
  3391. u32 port_id;
  3392. int i;
  3393. cp->csk_tbl = kvcalloc(MAX_CM_SK_TBL_SZ, sizeof(struct cnic_sock),
  3394. GFP_KERNEL);
  3395. if (!cp->csk_tbl)
  3396. return -ENOMEM;
  3397. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++)
  3398. atomic_set(&cp->csk_tbl[i].ref_count, 0);
  3399. port_id = prandom_u32_max(CNIC_LOCAL_PORT_RANGE);
  3400. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3401. CNIC_LOCAL_PORT_MIN, port_id)) {
  3402. cnic_cm_free_mem(dev);
  3403. return -ENOMEM;
  3404. }
  3405. return 0;
  3406. }
  3407. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3408. {
  3409. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3410. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3411. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3412. csk->state = opcode;
  3413. }
  3414. /* 1. If event opcode matches the expected event in csk->state
  3415. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3416. * event
  3417. * 3. If the expected event is 0, meaning the connection was never
  3418. * never established, we accept the opcode from cm_abort.
  3419. */
  3420. if (opcode == csk->state || csk->state == 0 ||
  3421. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3422. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3423. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3424. if (csk->state == 0)
  3425. csk->state = opcode;
  3426. return 1;
  3427. }
  3428. }
  3429. return 0;
  3430. }
  3431. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3432. {
  3433. struct cnic_dev *dev = csk->dev;
  3434. struct cnic_local *cp = dev->cnic_priv;
  3435. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3436. cnic_cm_upcall(cp, csk, opcode);
  3437. return;
  3438. }
  3439. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3440. cnic_close_conn(csk);
  3441. csk->state = opcode;
  3442. cnic_cm_upcall(cp, csk, opcode);
  3443. }
  3444. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3445. {
  3446. }
  3447. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3448. {
  3449. u32 seed;
  3450. seed = get_random_u32();
  3451. cnic_ctx_wr(dev, 45, 0, seed);
  3452. return 0;
  3453. }
  3454. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3455. {
  3456. struct cnic_dev *dev = csk->dev;
  3457. struct cnic_local *cp = dev->cnic_priv;
  3458. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3459. union l5cm_specific_data l5_data;
  3460. u32 cmd = 0;
  3461. int close_complete = 0;
  3462. switch (opcode) {
  3463. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3464. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3465. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3466. if (cnic_ready_to_close(csk, opcode)) {
  3467. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3468. close_complete = 1;
  3469. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3470. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3471. else
  3472. close_complete = 1;
  3473. }
  3474. break;
  3475. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3476. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3477. break;
  3478. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3479. close_complete = 1;
  3480. break;
  3481. }
  3482. if (cmd) {
  3483. memset(&l5_data, 0, sizeof(l5_data));
  3484. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3485. &l5_data);
  3486. } else if (close_complete) {
  3487. ctx->timestamp = jiffies;
  3488. cnic_close_conn(csk);
  3489. cnic_cm_upcall(cp, csk, csk->state);
  3490. }
  3491. }
  3492. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3493. {
  3494. struct cnic_local *cp = dev->cnic_priv;
  3495. if (!cp->ctx_tbl)
  3496. return;
  3497. if (!netif_running(dev->netdev))
  3498. return;
  3499. cnic_bnx2x_delete_wait(dev, 0);
  3500. cancel_delayed_work(&cp->delete_task);
  3501. flush_workqueue(cnic_wq);
  3502. if (atomic_read(&cp->iscsi_conn) != 0)
  3503. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3504. atomic_read(&cp->iscsi_conn));
  3505. }
  3506. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3507. {
  3508. struct bnx2x *bp = netdev_priv(dev->netdev);
  3509. u32 pfid = bp->pfid;
  3510. u32 port = BP_PORT(bp);
  3511. cnic_init_bnx2x_mac(dev);
  3512. cnic_bnx2x_set_tcp_options(dev, 0, 1);
  3513. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3514. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3515. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3516. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3517. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3518. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3519. DEF_MAX_DA_COUNT);
  3520. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3521. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3522. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3523. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3524. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3525. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3526. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3527. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3528. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3529. DEF_MAX_CWND);
  3530. return 0;
  3531. }
  3532. static void cnic_delete_task(struct work_struct *work)
  3533. {
  3534. struct cnic_local *cp;
  3535. struct cnic_dev *dev;
  3536. u32 i;
  3537. int need_resched = 0;
  3538. cp = container_of(work, struct cnic_local, delete_task.work);
  3539. dev = cp->dev;
  3540. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3541. struct drv_ctl_info info;
  3542. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3543. memset(&info, 0, sizeof(struct drv_ctl_info));
  3544. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3545. cp->ethdev->drv_ctl(dev->netdev, &info);
  3546. }
  3547. for (i = 0; i < cp->max_cid_space; i++) {
  3548. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3549. int err;
  3550. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3551. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3552. continue;
  3553. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3554. need_resched = 1;
  3555. continue;
  3556. }
  3557. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3558. continue;
  3559. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3560. cnic_free_bnx2x_conn_resc(dev, i);
  3561. if (!err) {
  3562. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3563. atomic_dec(&cp->iscsi_conn);
  3564. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3565. }
  3566. }
  3567. if (need_resched)
  3568. queue_delayed_work(cnic_wq, &cp->delete_task,
  3569. msecs_to_jiffies(10));
  3570. }
  3571. static int cnic_cm_open(struct cnic_dev *dev)
  3572. {
  3573. struct cnic_local *cp = dev->cnic_priv;
  3574. int err;
  3575. err = cnic_cm_alloc_mem(dev);
  3576. if (err)
  3577. return err;
  3578. err = cp->start_cm(dev);
  3579. if (err)
  3580. goto err_out;
  3581. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3582. dev->cm_create = cnic_cm_create;
  3583. dev->cm_destroy = cnic_cm_destroy;
  3584. dev->cm_connect = cnic_cm_connect;
  3585. dev->cm_abort = cnic_cm_abort;
  3586. dev->cm_close = cnic_cm_close;
  3587. dev->cm_select_dev = cnic_cm_select_dev;
  3588. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3589. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3590. return 0;
  3591. err_out:
  3592. cnic_cm_free_mem(dev);
  3593. return err;
  3594. }
  3595. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3596. {
  3597. struct cnic_local *cp = dev->cnic_priv;
  3598. int i;
  3599. if (!cp->csk_tbl)
  3600. return 0;
  3601. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3602. struct cnic_sock *csk = &cp->csk_tbl[i];
  3603. clear_bit(SK_F_INUSE, &csk->flags);
  3604. cnic_cm_cleanup(csk);
  3605. }
  3606. cnic_cm_free_mem(dev);
  3607. return 0;
  3608. }
  3609. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3610. {
  3611. u32 cid_addr;
  3612. int i;
  3613. cid_addr = GET_CID_ADDR(cid);
  3614. for (i = 0; i < CTX_SIZE; i += 4)
  3615. cnic_ctx_wr(dev, cid_addr, i, 0);
  3616. }
  3617. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3618. {
  3619. struct cnic_local *cp = dev->cnic_priv;
  3620. int ret = 0, i;
  3621. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3622. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3623. return 0;
  3624. for (i = 0; i < cp->ctx_blks; i++) {
  3625. int j;
  3626. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3627. u32 val;
  3628. memset(cp->ctx_arr[i].ctx, 0, CNIC_PAGE_SIZE);
  3629. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3630. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3631. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3632. (u64) cp->ctx_arr[i].mapping >> 32);
  3633. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3634. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3635. for (j = 0; j < 10; j++) {
  3636. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3637. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3638. break;
  3639. udelay(5);
  3640. }
  3641. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3642. ret = -EBUSY;
  3643. break;
  3644. }
  3645. }
  3646. return ret;
  3647. }
  3648. static void cnic_free_irq(struct cnic_dev *dev)
  3649. {
  3650. struct cnic_local *cp = dev->cnic_priv;
  3651. struct cnic_eth_dev *ethdev = cp->ethdev;
  3652. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3653. cp->disable_int_sync(dev);
  3654. tasklet_kill(&cp->cnic_irq_task);
  3655. free_irq(ethdev->irq_arr[0].vector, dev);
  3656. }
  3657. }
  3658. static int cnic_request_irq(struct cnic_dev *dev)
  3659. {
  3660. struct cnic_local *cp = dev->cnic_priv;
  3661. struct cnic_eth_dev *ethdev = cp->ethdev;
  3662. int err;
  3663. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3664. if (err)
  3665. tasklet_disable(&cp->cnic_irq_task);
  3666. return err;
  3667. }
  3668. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3669. {
  3670. struct cnic_local *cp = dev->cnic_priv;
  3671. struct cnic_eth_dev *ethdev = cp->ethdev;
  3672. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3673. int err, i = 0;
  3674. int sblk_num = cp->status_blk_num;
  3675. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3676. BNX2_HC_SB_CONFIG_1;
  3677. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3678. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3679. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3680. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3681. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3682. tasklet_setup(&cp->cnic_irq_task, cnic_service_bnx2_msix);
  3683. err = cnic_request_irq(dev);
  3684. if (err)
  3685. return err;
  3686. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3687. i < 10) {
  3688. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3689. 1 << (11 + sblk_num));
  3690. udelay(10);
  3691. i++;
  3692. barrier();
  3693. }
  3694. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3695. cnic_free_irq(dev);
  3696. goto failed;
  3697. }
  3698. } else {
  3699. struct status_block *sblk = cp->status_blk.gen;
  3700. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3701. int i = 0;
  3702. while (sblk->status_completion_producer_index && i < 10) {
  3703. CNIC_WR(dev, BNX2_HC_COMMAND,
  3704. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3705. udelay(10);
  3706. i++;
  3707. barrier();
  3708. }
  3709. if (sblk->status_completion_producer_index)
  3710. goto failed;
  3711. }
  3712. return 0;
  3713. failed:
  3714. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3715. return -EBUSY;
  3716. }
  3717. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3718. {
  3719. struct cnic_local *cp = dev->cnic_priv;
  3720. struct cnic_eth_dev *ethdev = cp->ethdev;
  3721. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3722. return;
  3723. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3724. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3725. }
  3726. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3727. {
  3728. struct cnic_local *cp = dev->cnic_priv;
  3729. struct cnic_eth_dev *ethdev = cp->ethdev;
  3730. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3731. return;
  3732. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3733. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3734. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3735. synchronize_irq(ethdev->irq_arr[0].vector);
  3736. }
  3737. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3738. {
  3739. struct cnic_local *cp = dev->cnic_priv;
  3740. struct cnic_eth_dev *ethdev = cp->ethdev;
  3741. struct cnic_uio_dev *udev = cp->udev;
  3742. u32 cid_addr, tx_cid, sb_id;
  3743. u32 val, offset0, offset1, offset2, offset3;
  3744. int i;
  3745. struct bnx2_tx_bd *txbd;
  3746. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3747. struct status_block *s_blk = cp->status_blk.gen;
  3748. sb_id = cp->status_blk_num;
  3749. tx_cid = 20;
  3750. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3751. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3752. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3753. tx_cid = TX_TSS_CID + sb_id - 1;
  3754. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3755. (TX_TSS_CID << 7));
  3756. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3757. }
  3758. cp->tx_cons = *cp->tx_cons_ptr;
  3759. cid_addr = GET_CID_ADDR(tx_cid);
  3760. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  3761. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3762. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3763. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3764. offset0 = BNX2_L2CTX_TYPE_XI;
  3765. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3766. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3767. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3768. } else {
  3769. cnic_init_context(dev, tx_cid);
  3770. cnic_init_context(dev, tx_cid + 1);
  3771. offset0 = BNX2_L2CTX_TYPE;
  3772. offset1 = BNX2_L2CTX_CMD_TYPE;
  3773. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3774. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3775. }
  3776. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3777. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3778. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3779. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3780. txbd = udev->l2_ring;
  3781. buf_map = udev->l2_buf_map;
  3782. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i++, txbd++) {
  3783. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3784. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3785. }
  3786. val = (u64) ring_map >> 32;
  3787. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3788. txbd->tx_bd_haddr_hi = val;
  3789. val = (u64) ring_map & 0xffffffff;
  3790. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3791. txbd->tx_bd_haddr_lo = val;
  3792. }
  3793. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3794. {
  3795. struct cnic_local *cp = dev->cnic_priv;
  3796. struct cnic_eth_dev *ethdev = cp->ethdev;
  3797. struct cnic_uio_dev *udev = cp->udev;
  3798. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3799. int i;
  3800. struct bnx2_rx_bd *rxbd;
  3801. struct status_block *s_blk = cp->status_blk.gen;
  3802. dma_addr_t ring_map = udev->l2_ring_map;
  3803. sb_id = cp->status_blk_num;
  3804. cnic_init_context(dev, 2);
  3805. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3806. coal_reg = BNX2_HC_COMMAND;
  3807. coal_val = CNIC_RD(dev, coal_reg);
  3808. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3809. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3810. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3811. coal_reg = BNX2_HC_COALESCE_NOW;
  3812. coal_val = 1 << (11 + sb_id);
  3813. }
  3814. i = 0;
  3815. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3816. CNIC_WR(dev, coal_reg, coal_val);
  3817. udelay(10);
  3818. i++;
  3819. barrier();
  3820. }
  3821. cp->rx_cons = *cp->rx_cons_ptr;
  3822. cid_addr = GET_CID_ADDR(2);
  3823. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3824. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3825. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3826. if (sb_id == 0)
  3827. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3828. else
  3829. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3830. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3831. rxbd = udev->l2_ring + CNIC_PAGE_SIZE;
  3832. for (i = 0; i < BNX2_MAX_RX_DESC_CNT; i++, rxbd++) {
  3833. dma_addr_t buf_map;
  3834. int n = (i % cp->l2_rx_ring_size) + 1;
  3835. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3836. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3837. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3838. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3839. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3840. }
  3841. val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
  3842. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3843. rxbd->rx_bd_haddr_hi = val;
  3844. val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
  3845. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3846. rxbd->rx_bd_haddr_lo = val;
  3847. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3848. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3849. }
  3850. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3851. {
  3852. struct kwqe *wqes[1], l2kwqe;
  3853. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3854. wqes[0] = &l2kwqe;
  3855. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3856. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3857. KWQE_OPCODE_SHIFT) | 2;
  3858. dev->submit_kwqes(dev, wqes, 1);
  3859. }
  3860. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3861. {
  3862. struct cnic_local *cp = dev->cnic_priv;
  3863. u32 val;
  3864. val = cp->func << 2;
  3865. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3866. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3867. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3868. dev->mac_addr[0] = (u8) (val >> 8);
  3869. dev->mac_addr[1] = (u8) val;
  3870. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3871. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3872. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3873. dev->mac_addr[2] = (u8) (val >> 24);
  3874. dev->mac_addr[3] = (u8) (val >> 16);
  3875. dev->mac_addr[4] = (u8) (val >> 8);
  3876. dev->mac_addr[5] = (u8) val;
  3877. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3878. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3879. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3880. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3881. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3882. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3883. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3884. }
  3885. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3886. {
  3887. struct cnic_local *cp = dev->cnic_priv;
  3888. struct cnic_eth_dev *ethdev = cp->ethdev;
  3889. struct status_block *sblk = cp->status_blk.gen;
  3890. u32 val, kcq_cid_addr, kwq_cid_addr;
  3891. int err;
  3892. cnic_set_bnx2_mac(dev);
  3893. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3894. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3895. if (CNIC_PAGE_BITS > 12)
  3896. val |= (12 - 8) << 4;
  3897. else
  3898. val |= (CNIC_PAGE_BITS - 8) << 4;
  3899. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3900. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3901. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3902. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3903. err = cnic_setup_5709_context(dev, 1);
  3904. if (err)
  3905. return err;
  3906. cnic_init_context(dev, KWQ_CID);
  3907. cnic_init_context(dev, KCQ_CID);
  3908. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3909. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3910. cp->max_kwq_idx = MAX_KWQ_IDX;
  3911. cp->kwq_prod_idx = 0;
  3912. cp->kwq_con_idx = 0;
  3913. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3914. if (BNX2_CHIP(cp) == BNX2_CHIP_5706 || BNX2_CHIP(cp) == BNX2_CHIP_5708)
  3915. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3916. else
  3917. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3918. /* Initialize the kernel work queue context. */
  3919. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3920. (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3921. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3922. val = (CNIC_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3923. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3924. val = ((CNIC_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3925. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3926. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3927. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3928. val = (u32) cp->kwq_info.pgtbl_map;
  3929. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3930. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3931. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3932. cp->kcq1.sw_prod_idx = 0;
  3933. cp->kcq1.hw_prod_idx_ptr =
  3934. &sblk->status_completion_producer_index;
  3935. cp->kcq1.status_idx_ptr = &sblk->status_idx;
  3936. /* Initialize the kernel complete queue context. */
  3937. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3938. (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3939. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3940. val = (CNIC_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3941. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3942. val = ((CNIC_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3943. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3944. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3945. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3946. val = (u32) cp->kcq1.dma.pgtbl_map;
  3947. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3948. cp->int_num = 0;
  3949. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3950. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3951. u32 sb_id = cp->status_blk_num;
  3952. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3953. cp->kcq1.hw_prod_idx_ptr =
  3954. &msblk->status_completion_producer_index;
  3955. cp->kcq1.status_idx_ptr = &msblk->status_idx;
  3956. cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
  3957. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3958. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3959. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3960. }
  3961. /* Enable Commnad Scheduler notification when we write to the
  3962. * host producer index of the kernel contexts. */
  3963. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3964. /* Enable Command Scheduler notification when we write to either
  3965. * the Send Queue or Receive Queue producer indexes of the kernel
  3966. * bypass contexts. */
  3967. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3968. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3969. /* Notify COM when the driver post an application buffer. */
  3970. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3971. /* Set the CP and COM doorbells. These two processors polls the
  3972. * doorbell for a non zero value before running. This must be done
  3973. * after setting up the kernel queue contexts. */
  3974. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3975. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3976. cnic_init_bnx2_tx_ring(dev);
  3977. cnic_init_bnx2_rx_ring(dev);
  3978. err = cnic_init_bnx2_irq(dev);
  3979. if (err) {
  3980. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3981. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3982. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3983. return err;
  3984. }
  3985. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  3986. return 0;
  3987. }
  3988. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3989. {
  3990. struct cnic_local *cp = dev->cnic_priv;
  3991. struct cnic_eth_dev *ethdev = cp->ethdev;
  3992. u32 start_offset = ethdev->ctx_tbl_offset;
  3993. int i;
  3994. for (i = 0; i < cp->ctx_blks; i++) {
  3995. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3996. dma_addr_t map = ctx->mapping;
  3997. if (cp->ctx_align) {
  3998. unsigned long mask = cp->ctx_align - 1;
  3999. map = (map + mask) & ~mask;
  4000. }
  4001. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  4002. }
  4003. }
  4004. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  4005. {
  4006. struct cnic_local *cp = dev->cnic_priv;
  4007. struct cnic_eth_dev *ethdev = cp->ethdev;
  4008. int err = 0;
  4009. tasklet_setup(&cp->cnic_irq_task, cnic_service_bnx2x_bh);
  4010. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  4011. err = cnic_request_irq(dev);
  4012. return err;
  4013. }
  4014. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  4015. u16 sb_id, u8 sb_index,
  4016. u8 disable)
  4017. {
  4018. struct bnx2x *bp = netdev_priv(dev->netdev);
  4019. u32 addr = BAR_CSTRORM_INTMEM +
  4020. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4021. offsetof(struct hc_status_block_data_e1x, index_data) +
  4022. sizeof(struct hc_index_data)*sb_index +
  4023. offsetof(struct hc_index_data, flags);
  4024. u16 flags = CNIC_RD16(dev, addr);
  4025. /* clear and set */
  4026. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  4027. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  4028. HC_INDEX_DATA_HC_ENABLED);
  4029. CNIC_WR16(dev, addr, flags);
  4030. }
  4031. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  4032. {
  4033. struct cnic_local *cp = dev->cnic_priv;
  4034. struct bnx2x *bp = netdev_priv(dev->netdev);
  4035. u8 sb_id = cp->status_blk_num;
  4036. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4037. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4038. offsetof(struct hc_status_block_data_e1x, index_data) +
  4039. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  4040. offsetof(struct hc_index_data, timeout), 64 / 4);
  4041. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  4042. }
  4043. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  4044. {
  4045. }
  4046. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  4047. struct client_init_ramrod_data *data)
  4048. {
  4049. struct cnic_local *cp = dev->cnic_priv;
  4050. struct bnx2x *bp = netdev_priv(dev->netdev);
  4051. struct cnic_uio_dev *udev = cp->udev;
  4052. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  4053. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  4054. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4055. int i;
  4056. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4057. u32 val;
  4058. memset(txbd, 0, CNIC_PAGE_SIZE);
  4059. buf_map = udev->l2_buf_map;
  4060. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  4061. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  4062. struct eth_tx_parse_bd_e1x *pbd_e1x =
  4063. &((txbd + 1)->parse_bd_e1x);
  4064. struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
  4065. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  4066. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4067. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4068. reg_bd->addr_hi = start_bd->addr_hi;
  4069. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  4070. start_bd->nbytes = cpu_to_le16(0x10);
  4071. start_bd->nbd = cpu_to_le16(3);
  4072. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  4073. start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
  4074. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  4075. if (BNX2X_CHIP_IS_E2_PLUS(bp))
  4076. pbd_e2->parsing_data = (UNICAST_ADDRESS <<
  4077. ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
  4078. else
  4079. pbd_e1x->global_data = (UNICAST_ADDRESS <<
  4080. ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
  4081. }
  4082. val = (u64) ring_map >> 32;
  4083. txbd->next_bd.addr_hi = cpu_to_le32(val);
  4084. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  4085. val = (u64) ring_map & 0xffffffff;
  4086. txbd->next_bd.addr_lo = cpu_to_le32(val);
  4087. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  4088. /* Other ramrod params */
  4089. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4090. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4091. /* reset xstorm per client statistics */
  4092. if (cli < MAX_STAT_COUNTER_ID) {
  4093. data->general.statistics_zero_flg = 1;
  4094. data->general.statistics_en_flg = 1;
  4095. data->general.statistics_counter_id = cli;
  4096. }
  4097. cp->tx_cons_ptr =
  4098. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4099. }
  4100. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4101. struct client_init_ramrod_data *data)
  4102. {
  4103. struct cnic_local *cp = dev->cnic_priv;
  4104. struct bnx2x *bp = netdev_priv(dev->netdev);
  4105. struct cnic_uio_dev *udev = cp->udev;
  4106. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4107. CNIC_PAGE_SIZE);
  4108. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4109. (udev->l2_ring + (2 * CNIC_PAGE_SIZE));
  4110. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4111. int i;
  4112. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4113. int cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
  4114. u32 val;
  4115. dma_addr_t ring_map = udev->l2_ring_map;
  4116. /* General data */
  4117. data->general.client_id = cli;
  4118. data->general.activate_flg = 1;
  4119. data->general.sp_client_id = cli;
  4120. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4121. data->general.func_id = bp->pfid;
  4122. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4123. dma_addr_t buf_map;
  4124. int n = (i % cp->l2_rx_ring_size) + 1;
  4125. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4126. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4127. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4128. }
  4129. val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
  4130. rxbd->addr_hi = cpu_to_le32(val);
  4131. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4132. val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
  4133. rxbd->addr_lo = cpu_to_le32(val);
  4134. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4135. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4136. val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) >> 32;
  4137. rxcqe->addr_hi = cpu_to_le32(val);
  4138. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4139. val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) & 0xffffffff;
  4140. rxcqe->addr_lo = cpu_to_le32(val);
  4141. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4142. /* Other ramrod params */
  4143. data->rx.client_qzone_id = cl_qzone_id;
  4144. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4145. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4146. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4147. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4148. data->rx.outer_vlan_removal_enable_flg = 1;
  4149. data->rx.silent_vlan_removal_flg = 1;
  4150. data->rx.silent_vlan_value = 0;
  4151. data->rx.silent_vlan_mask = 0xffff;
  4152. cp->rx_cons_ptr =
  4153. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4154. cp->rx_cons = *cp->rx_cons_ptr;
  4155. }
  4156. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4157. {
  4158. struct cnic_local *cp = dev->cnic_priv;
  4159. struct bnx2x *bp = netdev_priv(dev->netdev);
  4160. u32 pfid = bp->pfid;
  4161. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4162. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4163. cp->kcq1.sw_prod_idx = 0;
  4164. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4165. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4166. cp->kcq1.hw_prod_idx_ptr =
  4167. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4168. cp->kcq1.status_idx_ptr =
  4169. &sb->sb.running_index[SM_RX_ID];
  4170. } else {
  4171. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4172. cp->kcq1.hw_prod_idx_ptr =
  4173. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4174. cp->kcq1.status_idx_ptr =
  4175. &sb->sb.running_index[SM_RX_ID];
  4176. }
  4177. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4178. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4179. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4180. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4181. cp->kcq2.sw_prod_idx = 0;
  4182. cp->kcq2.hw_prod_idx_ptr =
  4183. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4184. cp->kcq2.status_idx_ptr =
  4185. &sb->sb.running_index[SM_RX_ID];
  4186. }
  4187. }
  4188. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4189. {
  4190. struct cnic_local *cp = dev->cnic_priv;
  4191. struct bnx2x *bp = netdev_priv(dev->netdev);
  4192. struct cnic_eth_dev *ethdev = cp->ethdev;
  4193. int ret;
  4194. u32 pfid;
  4195. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4196. cp->func = bp->pf_num;
  4197. pfid = bp->pfid;
  4198. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4199. cp->iscsi_start_cid, 0);
  4200. if (ret)
  4201. return -ENOMEM;
  4202. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4203. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4204. cp->fcoe_start_cid, 0);
  4205. if (ret)
  4206. return -ENOMEM;
  4207. }
  4208. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4209. cnic_init_bnx2x_kcq(dev);
  4210. /* Only 1 EQ */
  4211. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4212. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4213. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4214. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4215. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4216. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4217. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4218. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4219. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4220. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4221. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4222. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4223. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4224. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4225. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4226. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4227. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4228. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4229. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4230. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4231. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4232. HC_INDEX_ISCSI_EQ_CONS);
  4233. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4234. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4235. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4236. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4237. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4238. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4239. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4240. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4241. cnic_setup_bnx2x_context(dev);
  4242. ret = cnic_init_bnx2x_irq(dev);
  4243. if (ret)
  4244. return ret;
  4245. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  4246. return 0;
  4247. }
  4248. static void cnic_init_rings(struct cnic_dev *dev)
  4249. {
  4250. struct cnic_local *cp = dev->cnic_priv;
  4251. struct bnx2x *bp = netdev_priv(dev->netdev);
  4252. struct cnic_uio_dev *udev = cp->udev;
  4253. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4254. return;
  4255. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4256. cnic_init_bnx2_tx_ring(dev);
  4257. cnic_init_bnx2_rx_ring(dev);
  4258. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4259. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4260. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4261. u32 cid = cp->ethdev->iscsi_l2_cid;
  4262. u32 cl_qzone_id;
  4263. struct client_init_ramrod_data *data;
  4264. union l5cm_specific_data l5_data;
  4265. struct ustorm_eth_rx_producers rx_prods = {0};
  4266. u32 off, i, *cid_ptr;
  4267. rx_prods.bd_prod = 0;
  4268. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4269. barrier();
  4270. cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
  4271. off = BAR_USTRORM_INTMEM +
  4272. (BNX2X_CHIP_IS_E2_PLUS(bp) ?
  4273. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4274. USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), cli));
  4275. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4276. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4277. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4278. data = udev->l2_buf;
  4279. cid_ptr = udev->l2_buf + 12;
  4280. memset(data, 0, sizeof(*data));
  4281. cnic_init_bnx2x_tx_ring(dev, data);
  4282. cnic_init_bnx2x_rx_ring(dev, data);
  4283. data->general.fp_hsi_ver = ETH_FP_HSI_VERSION;
  4284. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4285. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4286. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4287. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4288. cid, ETH_CONNECTION_TYPE, &l5_data);
  4289. i = 0;
  4290. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4291. ++i < 10)
  4292. msleep(1);
  4293. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4294. netdev_err(dev->netdev,
  4295. "iSCSI CLIENT_SETUP did not complete\n");
  4296. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4297. cnic_ring_ctl(dev, cid, cli, 1);
  4298. *cid_ptr = cid >> 4;
  4299. *(cid_ptr + 1) = cid * bp->db_size;
  4300. *(cid_ptr + 2) = UIO_USE_TX_DOORBELL;
  4301. }
  4302. }
  4303. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4304. {
  4305. struct cnic_local *cp = dev->cnic_priv;
  4306. struct cnic_uio_dev *udev = cp->udev;
  4307. void *rx_ring;
  4308. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4309. return;
  4310. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4311. cnic_shutdown_bnx2_rx_ring(dev);
  4312. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4313. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4314. u32 cid = cp->ethdev->iscsi_l2_cid;
  4315. union l5cm_specific_data l5_data;
  4316. int i;
  4317. cnic_ring_ctl(dev, cid, cli, 0);
  4318. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4319. l5_data.phy_address.lo = cli;
  4320. l5_data.phy_address.hi = 0;
  4321. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4322. cid, ETH_CONNECTION_TYPE, &l5_data);
  4323. i = 0;
  4324. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4325. ++i < 10)
  4326. msleep(1);
  4327. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4328. netdev_err(dev->netdev,
  4329. "iSCSI CLIENT_HALT did not complete\n");
  4330. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4331. memset(&l5_data, 0, sizeof(l5_data));
  4332. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4333. cid, NONE_CONNECTION_TYPE, &l5_data);
  4334. msleep(10);
  4335. }
  4336. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4337. rx_ring = udev->l2_ring + CNIC_PAGE_SIZE;
  4338. memset(rx_ring, 0, CNIC_PAGE_SIZE);
  4339. }
  4340. static int cnic_register_netdev(struct cnic_dev *dev)
  4341. {
  4342. struct cnic_local *cp = dev->cnic_priv;
  4343. struct cnic_eth_dev *ethdev = cp->ethdev;
  4344. int err;
  4345. if (!ethdev)
  4346. return -ENODEV;
  4347. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4348. return 0;
  4349. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4350. if (err)
  4351. netdev_err(dev->netdev, "register_cnic failed\n");
  4352. /* Read iSCSI config again. On some bnx2x device, iSCSI config
  4353. * can change after firmware is downloaded.
  4354. */
  4355. dev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4356. if (ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  4357. dev->max_iscsi_conn = 0;
  4358. return err;
  4359. }
  4360. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4361. {
  4362. struct cnic_local *cp = dev->cnic_priv;
  4363. struct cnic_eth_dev *ethdev = cp->ethdev;
  4364. if (!ethdev)
  4365. return;
  4366. ethdev->drv_unregister_cnic(dev->netdev);
  4367. }
  4368. static int cnic_start_hw(struct cnic_dev *dev)
  4369. {
  4370. struct cnic_local *cp = dev->cnic_priv;
  4371. struct cnic_eth_dev *ethdev = cp->ethdev;
  4372. int err;
  4373. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4374. return -EALREADY;
  4375. dev->regview = ethdev->io_base;
  4376. pci_dev_get(dev->pcidev);
  4377. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4378. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4379. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4380. err = cp->alloc_resc(dev);
  4381. if (err) {
  4382. netdev_err(dev->netdev, "allocate resource failure\n");
  4383. goto err1;
  4384. }
  4385. err = cp->start_hw(dev);
  4386. if (err)
  4387. goto err1;
  4388. err = cnic_cm_open(dev);
  4389. if (err)
  4390. goto err1;
  4391. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4392. cp->enable_int(dev);
  4393. return 0;
  4394. err1:
  4395. if (ethdev->drv_state & CNIC_DRV_STATE_HANDLES_IRQ)
  4396. cp->stop_hw(dev);
  4397. else
  4398. cp->free_resc(dev);
  4399. pci_dev_put(dev->pcidev);
  4400. return err;
  4401. }
  4402. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4403. {
  4404. cnic_disable_bnx2_int_sync(dev);
  4405. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4406. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4407. cnic_init_context(dev, KWQ_CID);
  4408. cnic_init_context(dev, KCQ_CID);
  4409. cnic_setup_5709_context(dev, 0);
  4410. cnic_free_irq(dev);
  4411. cnic_free_resc(dev);
  4412. }
  4413. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4414. {
  4415. struct cnic_local *cp = dev->cnic_priv;
  4416. struct bnx2x *bp = netdev_priv(dev->netdev);
  4417. u32 hc_index = HC_INDEX_ISCSI_EQ_CONS;
  4418. u32 sb_id = cp->status_blk_num;
  4419. u32 idx_off, syn_off;
  4420. cnic_free_irq(dev);
  4421. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4422. idx_off = offsetof(struct hc_status_block_e2, index_values) +
  4423. (hc_index * sizeof(u16));
  4424. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hc_index, sb_id);
  4425. } else {
  4426. idx_off = offsetof(struct hc_status_block_e1x, index_values) +
  4427. (hc_index * sizeof(u16));
  4428. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hc_index, sb_id);
  4429. }
  4430. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + syn_off, 0);
  4431. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(sb_id) +
  4432. idx_off, 0);
  4433. *cp->kcq1.hw_prod_idx_ptr = 0;
  4434. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4435. CSTORM_ISCSI_EQ_CONS_OFFSET(bp->pfid, 0), 0);
  4436. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4437. cnic_free_resc(dev);
  4438. }
  4439. static void cnic_stop_hw(struct cnic_dev *dev)
  4440. {
  4441. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4442. struct cnic_local *cp = dev->cnic_priv;
  4443. int i = 0;
  4444. /* Need to wait for the ring shutdown event to complete
  4445. * before clearing the CNIC_UP flag.
  4446. */
  4447. while (cp->udev && cp->udev->uio_dev != -1 && i < 15) {
  4448. msleep(100);
  4449. i++;
  4450. }
  4451. cnic_shutdown_rings(dev);
  4452. cp->stop_cm(dev);
  4453. cp->ethdev->drv_state &= ~CNIC_DRV_STATE_HANDLES_IRQ;
  4454. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4455. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4456. synchronize_rcu();
  4457. cnic_cm_shutdown(dev);
  4458. cp->stop_hw(dev);
  4459. pci_dev_put(dev->pcidev);
  4460. }
  4461. }
  4462. static void cnic_free_dev(struct cnic_dev *dev)
  4463. {
  4464. int i = 0;
  4465. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4466. msleep(100);
  4467. i++;
  4468. }
  4469. if (atomic_read(&dev->ref_count) != 0)
  4470. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4471. netdev_info(dev->netdev, "Removed CNIC device\n");
  4472. dev_put(dev->netdev);
  4473. kfree(dev);
  4474. }
  4475. static int cnic_get_fc_npiv_tbl(struct cnic_dev *dev,
  4476. struct cnic_fc_npiv_tbl *npiv_tbl)
  4477. {
  4478. struct cnic_local *cp = dev->cnic_priv;
  4479. struct bnx2x *bp = netdev_priv(dev->netdev);
  4480. int ret;
  4481. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4482. return -EAGAIN; /* bnx2x is down */
  4483. if (!BNX2X_CHIP_IS_E2_PLUS(bp))
  4484. return -EINVAL;
  4485. ret = cp->ethdev->drv_get_fc_npiv_tbl(dev->netdev, npiv_tbl);
  4486. return ret;
  4487. }
  4488. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4489. struct pci_dev *pdev)
  4490. {
  4491. struct cnic_dev *cdev;
  4492. struct cnic_local *cp;
  4493. int alloc_size;
  4494. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4495. cdev = kzalloc(alloc_size, GFP_KERNEL);
  4496. if (cdev == NULL)
  4497. return NULL;
  4498. cdev->netdev = dev;
  4499. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4500. cdev->register_device = cnic_register_device;
  4501. cdev->unregister_device = cnic_unregister_device;
  4502. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4503. cdev->get_fc_npiv_tbl = cnic_get_fc_npiv_tbl;
  4504. atomic_set(&cdev->ref_count, 0);
  4505. cp = cdev->cnic_priv;
  4506. cp->dev = cdev;
  4507. cp->l2_single_buf_size = 0x400;
  4508. cp->l2_rx_ring_size = 3;
  4509. spin_lock_init(&cp->cnic_ulp_lock);
  4510. netdev_info(dev, "Added CNIC device\n");
  4511. return cdev;
  4512. }
  4513. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4514. {
  4515. struct pci_dev *pdev;
  4516. struct cnic_dev *cdev;
  4517. struct cnic_local *cp;
  4518. struct bnx2 *bp = netdev_priv(dev);
  4519. struct cnic_eth_dev *ethdev = NULL;
  4520. if (bp->cnic_probe)
  4521. ethdev = (bp->cnic_probe)(dev);
  4522. if (!ethdev)
  4523. return NULL;
  4524. pdev = ethdev->pdev;
  4525. if (!pdev)
  4526. return NULL;
  4527. dev_hold(dev);
  4528. pci_dev_get(pdev);
  4529. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4530. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4531. (pdev->revision < 0x10)) {
  4532. pci_dev_put(pdev);
  4533. goto cnic_err;
  4534. }
  4535. pci_dev_put(pdev);
  4536. cdev = cnic_alloc_dev(dev, pdev);
  4537. if (cdev == NULL)
  4538. goto cnic_err;
  4539. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4540. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4541. cp = cdev->cnic_priv;
  4542. cp->ethdev = ethdev;
  4543. cdev->pcidev = pdev;
  4544. cp->chip_id = ethdev->chip_id;
  4545. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4546. cp->cnic_ops = &cnic_bnx2_ops;
  4547. cp->start_hw = cnic_start_bnx2_hw;
  4548. cp->stop_hw = cnic_stop_bnx2_hw;
  4549. cp->setup_pgtbl = cnic_setup_page_tbl;
  4550. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4551. cp->free_resc = cnic_free_resc;
  4552. cp->start_cm = cnic_cm_init_bnx2_hw;
  4553. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4554. cp->enable_int = cnic_enable_bnx2_int;
  4555. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4556. cp->close_conn = cnic_close_bnx2_conn;
  4557. return cdev;
  4558. cnic_err:
  4559. dev_put(dev);
  4560. return NULL;
  4561. }
  4562. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4563. {
  4564. struct pci_dev *pdev;
  4565. struct cnic_dev *cdev;
  4566. struct cnic_local *cp;
  4567. struct bnx2x *bp = netdev_priv(dev);
  4568. struct cnic_eth_dev *ethdev = NULL;
  4569. if (bp->cnic_probe)
  4570. ethdev = bp->cnic_probe(dev);
  4571. if (!ethdev)
  4572. return NULL;
  4573. pdev = ethdev->pdev;
  4574. if (!pdev)
  4575. return NULL;
  4576. dev_hold(dev);
  4577. cdev = cnic_alloc_dev(dev, pdev);
  4578. if (cdev == NULL) {
  4579. dev_put(dev);
  4580. return NULL;
  4581. }
  4582. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4583. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4584. cp = cdev->cnic_priv;
  4585. cp->ethdev = ethdev;
  4586. cdev->pcidev = pdev;
  4587. cp->chip_id = ethdev->chip_id;
  4588. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4589. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4590. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4591. if (CNIC_SUPPORTS_FCOE(bp)) {
  4592. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4593. cdev->max_fcoe_exchanges = ethdev->max_fcoe_exchanges;
  4594. }
  4595. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4596. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4597. memcpy(cdev->mac_addr, ethdev->iscsi_mac, ETH_ALEN);
  4598. cp->cnic_ops = &cnic_bnx2x_ops;
  4599. cp->start_hw = cnic_start_bnx2x_hw;
  4600. cp->stop_hw = cnic_stop_bnx2x_hw;
  4601. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4602. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4603. cp->free_resc = cnic_free_resc;
  4604. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4605. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4606. cp->enable_int = cnic_enable_bnx2x_int;
  4607. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4608. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4609. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4610. cp->arm_int = cnic_arm_bnx2x_e2_msix;
  4611. } else {
  4612. cp->ack_int = cnic_ack_bnx2x_msix;
  4613. cp->arm_int = cnic_arm_bnx2x_msix;
  4614. }
  4615. cp->close_conn = cnic_close_bnx2x_conn;
  4616. return cdev;
  4617. }
  4618. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4619. {
  4620. struct ethtool_drvinfo drvinfo;
  4621. struct cnic_dev *cdev = NULL;
  4622. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4623. memset(&drvinfo, 0, sizeof(drvinfo));
  4624. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4625. if (!strcmp(drvinfo.driver, "bnx2"))
  4626. cdev = init_bnx2_cnic(dev);
  4627. if (!strcmp(drvinfo.driver, "bnx2x"))
  4628. cdev = init_bnx2x_cnic(dev);
  4629. if (cdev) {
  4630. write_lock(&cnic_dev_lock);
  4631. list_add(&cdev->list, &cnic_dev_list);
  4632. write_unlock(&cnic_dev_lock);
  4633. }
  4634. }
  4635. return cdev;
  4636. }
  4637. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4638. u16 vlan_id)
  4639. {
  4640. int if_type;
  4641. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4642. struct cnic_ulp_ops *ulp_ops;
  4643. void *ctx;
  4644. mutex_lock(&cnic_lock);
  4645. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  4646. lockdep_is_held(&cnic_lock));
  4647. if (!ulp_ops || !ulp_ops->indicate_netevent) {
  4648. mutex_unlock(&cnic_lock);
  4649. continue;
  4650. }
  4651. ctx = cp->ulp_handle[if_type];
  4652. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  4653. mutex_unlock(&cnic_lock);
  4654. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4655. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  4656. }
  4657. }
  4658. /* netdev event handler */
  4659. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4660. void *ptr)
  4661. {
  4662. struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
  4663. struct cnic_dev *dev;
  4664. int new_dev = 0;
  4665. dev = cnic_from_netdev(netdev);
  4666. if (!dev && event == NETDEV_REGISTER) {
  4667. /* Check for the hot-plug device */
  4668. dev = is_cnic_dev(netdev);
  4669. if (dev) {
  4670. new_dev = 1;
  4671. cnic_hold(dev);
  4672. }
  4673. }
  4674. if (dev) {
  4675. struct cnic_local *cp = dev->cnic_priv;
  4676. if (new_dev)
  4677. cnic_ulp_init(dev);
  4678. else if (event == NETDEV_UNREGISTER)
  4679. cnic_ulp_exit(dev);
  4680. if (event == NETDEV_UP) {
  4681. if (cnic_register_netdev(dev) != 0) {
  4682. cnic_put(dev);
  4683. goto done;
  4684. }
  4685. if (!cnic_start_hw(dev))
  4686. cnic_ulp_start(dev);
  4687. }
  4688. cnic_rcv_netevent(cp, event, 0);
  4689. if (event == NETDEV_GOING_DOWN) {
  4690. cnic_ulp_stop(dev);
  4691. cnic_stop_hw(dev);
  4692. cnic_unregister_netdev(dev);
  4693. } else if (event == NETDEV_UNREGISTER) {
  4694. write_lock(&cnic_dev_lock);
  4695. list_del_init(&dev->list);
  4696. write_unlock(&cnic_dev_lock);
  4697. cnic_put(dev);
  4698. cnic_free_dev(dev);
  4699. goto done;
  4700. }
  4701. cnic_put(dev);
  4702. } else {
  4703. struct net_device *realdev;
  4704. u16 vid;
  4705. vid = cnic_get_vlan(netdev, &realdev);
  4706. if (realdev) {
  4707. dev = cnic_from_netdev(realdev);
  4708. if (dev) {
  4709. vid |= VLAN_CFI_MASK; /* make non-zero */
  4710. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4711. cnic_put(dev);
  4712. }
  4713. }
  4714. }
  4715. done:
  4716. return NOTIFY_DONE;
  4717. }
  4718. static struct notifier_block cnic_netdev_notifier = {
  4719. .notifier_call = cnic_netdev_event
  4720. };
  4721. static void cnic_release(void)
  4722. {
  4723. struct cnic_uio_dev *udev;
  4724. while (!list_empty(&cnic_udev_list)) {
  4725. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4726. list);
  4727. cnic_free_uio(udev);
  4728. }
  4729. }
  4730. static int __init cnic_init(void)
  4731. {
  4732. int rc = 0;
  4733. pr_info("%s", version);
  4734. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4735. if (rc) {
  4736. cnic_release();
  4737. return rc;
  4738. }
  4739. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4740. if (!cnic_wq) {
  4741. cnic_release();
  4742. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4743. return -ENOMEM;
  4744. }
  4745. return 0;
  4746. }
  4747. static void __exit cnic_exit(void)
  4748. {
  4749. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4750. cnic_release();
  4751. destroy_workqueue(cnic_wq);
  4752. }
  4753. module_init(cnic_init);
  4754. module_exit(cnic_exit);