emac_main.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
  4. *
  5. * Driver for the ARC EMAC 10100 (hardware revision 5)
  6. *
  7. * Contributors:
  8. * Amit Bhor
  9. * Sameer Dhavale
  10. * Vineet Gupta
  11. */
  12. #include <linux/crc32.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/of_mdio.h>
  20. #include <linux/of_net.h>
  21. #include <linux/of_platform.h>
  22. #include "emac.h"
  23. static void arc_emac_restart(struct net_device *ndev);
  24. /**
  25. * arc_emac_tx_avail - Return the number of available slots in the tx ring.
  26. * @priv: Pointer to ARC EMAC private data structure.
  27. *
  28. * returns: the number of slots available for transmission in tx the ring.
  29. */
  30. static inline int arc_emac_tx_avail(struct arc_emac_priv *priv)
  31. {
  32. return (priv->txbd_dirty + TX_BD_NUM - priv->txbd_curr - 1) % TX_BD_NUM;
  33. }
  34. /**
  35. * arc_emac_adjust_link - Adjust the PHY link duplex.
  36. * @ndev: Pointer to the net_device structure.
  37. *
  38. * This function is called to change the duplex setting after auto negotiation
  39. * is done by the PHY.
  40. */
  41. static void arc_emac_adjust_link(struct net_device *ndev)
  42. {
  43. struct arc_emac_priv *priv = netdev_priv(ndev);
  44. struct phy_device *phy_dev = ndev->phydev;
  45. unsigned int reg, state_changed = 0;
  46. if (priv->link != phy_dev->link) {
  47. priv->link = phy_dev->link;
  48. state_changed = 1;
  49. }
  50. if (priv->speed != phy_dev->speed) {
  51. priv->speed = phy_dev->speed;
  52. state_changed = 1;
  53. if (priv->set_mac_speed)
  54. priv->set_mac_speed(priv, priv->speed);
  55. }
  56. if (priv->duplex != phy_dev->duplex) {
  57. reg = arc_reg_get(priv, R_CTRL);
  58. if (phy_dev->duplex == DUPLEX_FULL)
  59. reg |= ENFL_MASK;
  60. else
  61. reg &= ~ENFL_MASK;
  62. arc_reg_set(priv, R_CTRL, reg);
  63. priv->duplex = phy_dev->duplex;
  64. state_changed = 1;
  65. }
  66. if (state_changed)
  67. phy_print_status(phy_dev);
  68. }
  69. /**
  70. * arc_emac_get_drvinfo - Get EMAC driver information.
  71. * @ndev: Pointer to net_device structure.
  72. * @info: Pointer to ethtool_drvinfo structure.
  73. *
  74. * This implements ethtool command for getting the driver information.
  75. * Issue "ethtool -i ethX" under linux prompt to execute this function.
  76. */
  77. static void arc_emac_get_drvinfo(struct net_device *ndev,
  78. struct ethtool_drvinfo *info)
  79. {
  80. struct arc_emac_priv *priv = netdev_priv(ndev);
  81. strscpy(info->driver, priv->drv_name, sizeof(info->driver));
  82. }
  83. static const struct ethtool_ops arc_emac_ethtool_ops = {
  84. .get_drvinfo = arc_emac_get_drvinfo,
  85. .get_link = ethtool_op_get_link,
  86. .get_link_ksettings = phy_ethtool_get_link_ksettings,
  87. .set_link_ksettings = phy_ethtool_set_link_ksettings,
  88. };
  89. #define FIRST_OR_LAST_MASK (FIRST_MASK | LAST_MASK)
  90. /**
  91. * arc_emac_tx_clean - clears processed by EMAC Tx BDs.
  92. * @ndev: Pointer to the network device.
  93. */
  94. static void arc_emac_tx_clean(struct net_device *ndev)
  95. {
  96. struct arc_emac_priv *priv = netdev_priv(ndev);
  97. struct net_device_stats *stats = &ndev->stats;
  98. unsigned int i;
  99. for (i = 0; i < TX_BD_NUM; i++) {
  100. unsigned int *txbd_dirty = &priv->txbd_dirty;
  101. struct arc_emac_bd *txbd = &priv->txbd[*txbd_dirty];
  102. struct buffer_state *tx_buff = &priv->tx_buff[*txbd_dirty];
  103. struct sk_buff *skb = tx_buff->skb;
  104. unsigned int info = le32_to_cpu(txbd->info);
  105. if ((info & FOR_EMAC) || !txbd->data || !skb)
  106. break;
  107. if (unlikely(info & (DROP | DEFR | LTCL | UFLO))) {
  108. stats->tx_errors++;
  109. stats->tx_dropped++;
  110. if (info & DEFR)
  111. stats->tx_carrier_errors++;
  112. if (info & LTCL)
  113. stats->collisions++;
  114. if (info & UFLO)
  115. stats->tx_fifo_errors++;
  116. } else if (likely(info & FIRST_OR_LAST_MASK)) {
  117. stats->tx_packets++;
  118. stats->tx_bytes += skb->len;
  119. }
  120. dma_unmap_single(&ndev->dev, dma_unmap_addr(tx_buff, addr),
  121. dma_unmap_len(tx_buff, len), DMA_TO_DEVICE);
  122. /* return the sk_buff to system */
  123. dev_consume_skb_irq(skb);
  124. txbd->data = 0;
  125. txbd->info = 0;
  126. tx_buff->skb = NULL;
  127. *txbd_dirty = (*txbd_dirty + 1) % TX_BD_NUM;
  128. }
  129. /* Ensure that txbd_dirty is visible to tx() before checking
  130. * for queue stopped.
  131. */
  132. smp_mb();
  133. if (netif_queue_stopped(ndev) && arc_emac_tx_avail(priv))
  134. netif_wake_queue(ndev);
  135. }
  136. /**
  137. * arc_emac_rx - processing of Rx packets.
  138. * @ndev: Pointer to the network device.
  139. * @budget: How many BDs to process on 1 call.
  140. *
  141. * returns: Number of processed BDs
  142. *
  143. * Iterate through Rx BDs and deliver received packages to upper layer.
  144. */
  145. static int arc_emac_rx(struct net_device *ndev, int budget)
  146. {
  147. struct arc_emac_priv *priv = netdev_priv(ndev);
  148. unsigned int work_done;
  149. for (work_done = 0; work_done < budget; work_done++) {
  150. unsigned int *last_rx_bd = &priv->last_rx_bd;
  151. struct net_device_stats *stats = &ndev->stats;
  152. struct buffer_state *rx_buff = &priv->rx_buff[*last_rx_bd];
  153. struct arc_emac_bd *rxbd = &priv->rxbd[*last_rx_bd];
  154. unsigned int pktlen, info = le32_to_cpu(rxbd->info);
  155. struct sk_buff *skb;
  156. dma_addr_t addr;
  157. if (unlikely((info & OWN_MASK) == FOR_EMAC))
  158. break;
  159. /* Make a note that we saw a packet at this BD.
  160. * So next time, driver starts from this + 1
  161. */
  162. *last_rx_bd = (*last_rx_bd + 1) % RX_BD_NUM;
  163. if (unlikely((info & FIRST_OR_LAST_MASK) !=
  164. FIRST_OR_LAST_MASK)) {
  165. /* We pre-allocate buffers of MTU size so incoming
  166. * packets won't be split/chained.
  167. */
  168. if (net_ratelimit())
  169. netdev_err(ndev, "incomplete packet received\n");
  170. /* Return ownership to EMAC */
  171. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  172. stats->rx_errors++;
  173. stats->rx_length_errors++;
  174. continue;
  175. }
  176. /* Prepare the BD for next cycle. netif_receive_skb()
  177. * only if new skb was allocated and mapped to avoid holes
  178. * in the RX fifo.
  179. */
  180. skb = netdev_alloc_skb_ip_align(ndev, EMAC_BUFFER_SIZE);
  181. if (unlikely(!skb)) {
  182. if (net_ratelimit())
  183. netdev_err(ndev, "cannot allocate skb\n");
  184. /* Return ownership to EMAC */
  185. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  186. stats->rx_errors++;
  187. stats->rx_dropped++;
  188. continue;
  189. }
  190. addr = dma_map_single(&ndev->dev, (void *)skb->data,
  191. EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
  192. if (dma_mapping_error(&ndev->dev, addr)) {
  193. if (net_ratelimit())
  194. netdev_err(ndev, "cannot map dma buffer\n");
  195. dev_kfree_skb(skb);
  196. /* Return ownership to EMAC */
  197. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  198. stats->rx_errors++;
  199. stats->rx_dropped++;
  200. continue;
  201. }
  202. /* unmap previosly mapped skb */
  203. dma_unmap_single(&ndev->dev, dma_unmap_addr(rx_buff, addr),
  204. dma_unmap_len(rx_buff, len), DMA_FROM_DEVICE);
  205. pktlen = info & LEN_MASK;
  206. stats->rx_packets++;
  207. stats->rx_bytes += pktlen;
  208. skb_put(rx_buff->skb, pktlen);
  209. rx_buff->skb->dev = ndev;
  210. rx_buff->skb->protocol = eth_type_trans(rx_buff->skb, ndev);
  211. netif_receive_skb(rx_buff->skb);
  212. rx_buff->skb = skb;
  213. dma_unmap_addr_set(rx_buff, addr, addr);
  214. dma_unmap_len_set(rx_buff, len, EMAC_BUFFER_SIZE);
  215. rxbd->data = cpu_to_le32(addr);
  216. /* Make sure pointer to data buffer is set */
  217. wmb();
  218. /* Return ownership to EMAC */
  219. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  220. }
  221. return work_done;
  222. }
  223. /**
  224. * arc_emac_rx_miss_handle - handle R_MISS register
  225. * @ndev: Pointer to the net_device structure.
  226. */
  227. static void arc_emac_rx_miss_handle(struct net_device *ndev)
  228. {
  229. struct arc_emac_priv *priv = netdev_priv(ndev);
  230. struct net_device_stats *stats = &ndev->stats;
  231. unsigned int miss;
  232. miss = arc_reg_get(priv, R_MISS);
  233. if (miss) {
  234. stats->rx_errors += miss;
  235. stats->rx_missed_errors += miss;
  236. priv->rx_missed_errors += miss;
  237. }
  238. }
  239. /**
  240. * arc_emac_rx_stall_check - check RX stall
  241. * @ndev: Pointer to the net_device structure.
  242. * @budget: How many BDs requested to process on 1 call.
  243. * @work_done: How many BDs processed
  244. *
  245. * Under certain conditions EMAC stop reception of incoming packets and
  246. * continuously increment R_MISS register instead of saving data into
  247. * provided buffer. This function detect that condition and restart
  248. * EMAC.
  249. */
  250. static void arc_emac_rx_stall_check(struct net_device *ndev,
  251. int budget, unsigned int work_done)
  252. {
  253. struct arc_emac_priv *priv = netdev_priv(ndev);
  254. struct arc_emac_bd *rxbd;
  255. if (work_done)
  256. priv->rx_missed_errors = 0;
  257. if (priv->rx_missed_errors && budget) {
  258. rxbd = &priv->rxbd[priv->last_rx_bd];
  259. if (le32_to_cpu(rxbd->info) & FOR_EMAC) {
  260. arc_emac_restart(ndev);
  261. priv->rx_missed_errors = 0;
  262. }
  263. }
  264. }
  265. /**
  266. * arc_emac_poll - NAPI poll handler.
  267. * @napi: Pointer to napi_struct structure.
  268. * @budget: How many BDs to process on 1 call.
  269. *
  270. * returns: Number of processed BDs
  271. */
  272. static int arc_emac_poll(struct napi_struct *napi, int budget)
  273. {
  274. struct net_device *ndev = napi->dev;
  275. struct arc_emac_priv *priv = netdev_priv(ndev);
  276. unsigned int work_done;
  277. arc_emac_tx_clean(ndev);
  278. arc_emac_rx_miss_handle(ndev);
  279. work_done = arc_emac_rx(ndev, budget);
  280. if (work_done < budget) {
  281. napi_complete_done(napi, work_done);
  282. arc_reg_or(priv, R_ENABLE, RXINT_MASK | TXINT_MASK);
  283. }
  284. arc_emac_rx_stall_check(ndev, budget, work_done);
  285. return work_done;
  286. }
  287. /**
  288. * arc_emac_intr - Global interrupt handler for EMAC.
  289. * @irq: irq number.
  290. * @dev_instance: device instance.
  291. *
  292. * returns: IRQ_HANDLED for all cases.
  293. *
  294. * ARC EMAC has only 1 interrupt line, and depending on bits raised in
  295. * STATUS register we may tell what is a reason for interrupt to fire.
  296. */
  297. static irqreturn_t arc_emac_intr(int irq, void *dev_instance)
  298. {
  299. struct net_device *ndev = dev_instance;
  300. struct arc_emac_priv *priv = netdev_priv(ndev);
  301. struct net_device_stats *stats = &ndev->stats;
  302. unsigned int status;
  303. status = arc_reg_get(priv, R_STATUS);
  304. status &= ~MDIO_MASK;
  305. /* Reset all flags except "MDIO complete" */
  306. arc_reg_set(priv, R_STATUS, status);
  307. if (status & (RXINT_MASK | TXINT_MASK)) {
  308. if (likely(napi_schedule_prep(&priv->napi))) {
  309. arc_reg_clr(priv, R_ENABLE, RXINT_MASK | TXINT_MASK);
  310. __napi_schedule(&priv->napi);
  311. }
  312. }
  313. if (status & ERR_MASK) {
  314. /* MSER/RXCR/RXFR/RXFL interrupt fires on corresponding
  315. * 8-bit error counter overrun.
  316. */
  317. if (status & MSER_MASK) {
  318. stats->rx_missed_errors += 0x100;
  319. stats->rx_errors += 0x100;
  320. priv->rx_missed_errors += 0x100;
  321. napi_schedule(&priv->napi);
  322. }
  323. if (status & RXCR_MASK) {
  324. stats->rx_crc_errors += 0x100;
  325. stats->rx_errors += 0x100;
  326. }
  327. if (status & RXFR_MASK) {
  328. stats->rx_frame_errors += 0x100;
  329. stats->rx_errors += 0x100;
  330. }
  331. if (status & RXFL_MASK) {
  332. stats->rx_over_errors += 0x100;
  333. stats->rx_errors += 0x100;
  334. }
  335. }
  336. return IRQ_HANDLED;
  337. }
  338. #ifdef CONFIG_NET_POLL_CONTROLLER
  339. static void arc_emac_poll_controller(struct net_device *dev)
  340. {
  341. disable_irq(dev->irq);
  342. arc_emac_intr(dev->irq, dev);
  343. enable_irq(dev->irq);
  344. }
  345. #endif
  346. /**
  347. * arc_emac_open - Open the network device.
  348. * @ndev: Pointer to the network device.
  349. *
  350. * returns: 0, on success or non-zero error value on failure.
  351. *
  352. * This function sets the MAC address, requests and enables an IRQ
  353. * for the EMAC device and starts the Tx queue.
  354. * It also connects to the phy device.
  355. */
  356. static int arc_emac_open(struct net_device *ndev)
  357. {
  358. struct arc_emac_priv *priv = netdev_priv(ndev);
  359. struct phy_device *phy_dev = ndev->phydev;
  360. int i;
  361. phy_dev->autoneg = AUTONEG_ENABLE;
  362. phy_dev->speed = 0;
  363. phy_dev->duplex = 0;
  364. linkmode_and(phy_dev->advertising, phy_dev->advertising,
  365. phy_dev->supported);
  366. priv->last_rx_bd = 0;
  367. /* Allocate and set buffers for Rx BD's */
  368. for (i = 0; i < RX_BD_NUM; i++) {
  369. dma_addr_t addr;
  370. unsigned int *last_rx_bd = &priv->last_rx_bd;
  371. struct arc_emac_bd *rxbd = &priv->rxbd[*last_rx_bd];
  372. struct buffer_state *rx_buff = &priv->rx_buff[*last_rx_bd];
  373. rx_buff->skb = netdev_alloc_skb_ip_align(ndev,
  374. EMAC_BUFFER_SIZE);
  375. if (unlikely(!rx_buff->skb))
  376. return -ENOMEM;
  377. addr = dma_map_single(&ndev->dev, (void *)rx_buff->skb->data,
  378. EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
  379. if (dma_mapping_error(&ndev->dev, addr)) {
  380. netdev_err(ndev, "cannot dma map\n");
  381. dev_kfree_skb(rx_buff->skb);
  382. return -ENOMEM;
  383. }
  384. dma_unmap_addr_set(rx_buff, addr, addr);
  385. dma_unmap_len_set(rx_buff, len, EMAC_BUFFER_SIZE);
  386. rxbd->data = cpu_to_le32(addr);
  387. /* Make sure pointer to data buffer is set */
  388. wmb();
  389. /* Return ownership to EMAC */
  390. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  391. *last_rx_bd = (*last_rx_bd + 1) % RX_BD_NUM;
  392. }
  393. priv->txbd_curr = 0;
  394. priv->txbd_dirty = 0;
  395. /* Clean Tx BD's */
  396. memset(priv->txbd, 0, TX_RING_SZ);
  397. /* Initialize logical address filter */
  398. arc_reg_set(priv, R_LAFL, 0);
  399. arc_reg_set(priv, R_LAFH, 0);
  400. /* Set BD ring pointers for device side */
  401. arc_reg_set(priv, R_RX_RING, (unsigned int)priv->rxbd_dma);
  402. arc_reg_set(priv, R_TX_RING, (unsigned int)priv->txbd_dma);
  403. /* Enable interrupts */
  404. arc_reg_set(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
  405. /* Set CONTROL */
  406. arc_reg_set(priv, R_CTRL,
  407. (RX_BD_NUM << 24) | /* RX BD table length */
  408. (TX_BD_NUM << 16) | /* TX BD table length */
  409. TXRN_MASK | RXRN_MASK);
  410. napi_enable(&priv->napi);
  411. /* Enable EMAC */
  412. arc_reg_or(priv, R_CTRL, EN_MASK);
  413. phy_start(ndev->phydev);
  414. netif_start_queue(ndev);
  415. return 0;
  416. }
  417. /**
  418. * arc_emac_set_rx_mode - Change the receive filtering mode.
  419. * @ndev: Pointer to the network device.
  420. *
  421. * This function enables/disables promiscuous or all-multicast mode
  422. * and updates the multicast filtering list of the network device.
  423. */
  424. static void arc_emac_set_rx_mode(struct net_device *ndev)
  425. {
  426. struct arc_emac_priv *priv = netdev_priv(ndev);
  427. if (ndev->flags & IFF_PROMISC) {
  428. arc_reg_or(priv, R_CTRL, PROM_MASK);
  429. } else {
  430. arc_reg_clr(priv, R_CTRL, PROM_MASK);
  431. if (ndev->flags & IFF_ALLMULTI) {
  432. arc_reg_set(priv, R_LAFL, ~0);
  433. arc_reg_set(priv, R_LAFH, ~0);
  434. } else if (ndev->flags & IFF_MULTICAST) {
  435. struct netdev_hw_addr *ha;
  436. unsigned int filter[2] = { 0, 0 };
  437. int bit;
  438. netdev_for_each_mc_addr(ha, ndev) {
  439. bit = ether_crc_le(ETH_ALEN, ha->addr) >> 26;
  440. filter[bit >> 5] |= 1 << (bit & 31);
  441. }
  442. arc_reg_set(priv, R_LAFL, filter[0]);
  443. arc_reg_set(priv, R_LAFH, filter[1]);
  444. } else {
  445. arc_reg_set(priv, R_LAFL, 0);
  446. arc_reg_set(priv, R_LAFH, 0);
  447. }
  448. }
  449. }
  450. /**
  451. * arc_free_tx_queue - free skb from tx queue
  452. * @ndev: Pointer to the network device.
  453. *
  454. * This function must be called while EMAC disable
  455. */
  456. static void arc_free_tx_queue(struct net_device *ndev)
  457. {
  458. struct arc_emac_priv *priv = netdev_priv(ndev);
  459. unsigned int i;
  460. for (i = 0; i < TX_BD_NUM; i++) {
  461. struct arc_emac_bd *txbd = &priv->txbd[i];
  462. struct buffer_state *tx_buff = &priv->tx_buff[i];
  463. if (tx_buff->skb) {
  464. dma_unmap_single(&ndev->dev,
  465. dma_unmap_addr(tx_buff, addr),
  466. dma_unmap_len(tx_buff, len),
  467. DMA_TO_DEVICE);
  468. /* return the sk_buff to system */
  469. dev_kfree_skb_irq(tx_buff->skb);
  470. }
  471. txbd->info = 0;
  472. txbd->data = 0;
  473. tx_buff->skb = NULL;
  474. }
  475. }
  476. /**
  477. * arc_free_rx_queue - free skb from rx queue
  478. * @ndev: Pointer to the network device.
  479. *
  480. * This function must be called while EMAC disable
  481. */
  482. static void arc_free_rx_queue(struct net_device *ndev)
  483. {
  484. struct arc_emac_priv *priv = netdev_priv(ndev);
  485. unsigned int i;
  486. for (i = 0; i < RX_BD_NUM; i++) {
  487. struct arc_emac_bd *rxbd = &priv->rxbd[i];
  488. struct buffer_state *rx_buff = &priv->rx_buff[i];
  489. if (rx_buff->skb) {
  490. dma_unmap_single(&ndev->dev,
  491. dma_unmap_addr(rx_buff, addr),
  492. dma_unmap_len(rx_buff, len),
  493. DMA_FROM_DEVICE);
  494. /* return the sk_buff to system */
  495. dev_kfree_skb_irq(rx_buff->skb);
  496. }
  497. rxbd->info = 0;
  498. rxbd->data = 0;
  499. rx_buff->skb = NULL;
  500. }
  501. }
  502. /**
  503. * arc_emac_stop - Close the network device.
  504. * @ndev: Pointer to the network device.
  505. *
  506. * This function stops the Tx queue, disables interrupts and frees the IRQ for
  507. * the EMAC device.
  508. * It also disconnects the PHY device associated with the EMAC device.
  509. */
  510. static int arc_emac_stop(struct net_device *ndev)
  511. {
  512. struct arc_emac_priv *priv = netdev_priv(ndev);
  513. napi_disable(&priv->napi);
  514. netif_stop_queue(ndev);
  515. phy_stop(ndev->phydev);
  516. /* Disable interrupts */
  517. arc_reg_clr(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
  518. /* Disable EMAC */
  519. arc_reg_clr(priv, R_CTRL, EN_MASK);
  520. /* Return the sk_buff to system */
  521. arc_free_tx_queue(ndev);
  522. arc_free_rx_queue(ndev);
  523. return 0;
  524. }
  525. /**
  526. * arc_emac_stats - Get system network statistics.
  527. * @ndev: Pointer to net_device structure.
  528. *
  529. * Returns the address of the device statistics structure.
  530. * Statistics are updated in interrupt handler.
  531. */
  532. static struct net_device_stats *arc_emac_stats(struct net_device *ndev)
  533. {
  534. struct arc_emac_priv *priv = netdev_priv(ndev);
  535. struct net_device_stats *stats = &ndev->stats;
  536. unsigned long miss, rxerr;
  537. u8 rxcrc, rxfram, rxoflow;
  538. rxerr = arc_reg_get(priv, R_RXERR);
  539. miss = arc_reg_get(priv, R_MISS);
  540. rxcrc = rxerr;
  541. rxfram = rxerr >> 8;
  542. rxoflow = rxerr >> 16;
  543. stats->rx_errors += miss;
  544. stats->rx_errors += rxcrc + rxfram + rxoflow;
  545. stats->rx_over_errors += rxoflow;
  546. stats->rx_frame_errors += rxfram;
  547. stats->rx_crc_errors += rxcrc;
  548. stats->rx_missed_errors += miss;
  549. return stats;
  550. }
  551. /**
  552. * arc_emac_tx - Starts the data transmission.
  553. * @skb: sk_buff pointer that contains data to be Transmitted.
  554. * @ndev: Pointer to net_device structure.
  555. *
  556. * returns: NETDEV_TX_OK, on success
  557. * NETDEV_TX_BUSY, if any of the descriptors are not free.
  558. *
  559. * This function is invoked from upper layers to initiate transmission.
  560. */
  561. static netdev_tx_t arc_emac_tx(struct sk_buff *skb, struct net_device *ndev)
  562. {
  563. struct arc_emac_priv *priv = netdev_priv(ndev);
  564. unsigned int len, *txbd_curr = &priv->txbd_curr;
  565. struct net_device_stats *stats = &ndev->stats;
  566. __le32 *info = &priv->txbd[*txbd_curr].info;
  567. dma_addr_t addr;
  568. if (skb_padto(skb, ETH_ZLEN))
  569. return NETDEV_TX_OK;
  570. len = max_t(unsigned int, ETH_ZLEN, skb->len);
  571. if (unlikely(!arc_emac_tx_avail(priv))) {
  572. netif_stop_queue(ndev);
  573. netdev_err(ndev, "BUG! Tx Ring full when queue awake!\n");
  574. return NETDEV_TX_BUSY;
  575. }
  576. addr = dma_map_single(&ndev->dev, (void *)skb->data, len,
  577. DMA_TO_DEVICE);
  578. if (unlikely(dma_mapping_error(&ndev->dev, addr))) {
  579. stats->tx_dropped++;
  580. stats->tx_errors++;
  581. dev_kfree_skb_any(skb);
  582. return NETDEV_TX_OK;
  583. }
  584. dma_unmap_addr_set(&priv->tx_buff[*txbd_curr], addr, addr);
  585. dma_unmap_len_set(&priv->tx_buff[*txbd_curr], len, len);
  586. priv->txbd[*txbd_curr].data = cpu_to_le32(addr);
  587. /* Make sure pointer to data buffer is set */
  588. wmb();
  589. skb_tx_timestamp(skb);
  590. *info = cpu_to_le32(FOR_EMAC | FIRST_OR_LAST_MASK | len);
  591. /* Make sure info word is set */
  592. wmb();
  593. priv->tx_buff[*txbd_curr].skb = skb;
  594. /* Increment index to point to the next BD */
  595. *txbd_curr = (*txbd_curr + 1) % TX_BD_NUM;
  596. /* Ensure that tx_clean() sees the new txbd_curr before
  597. * checking the queue status. This prevents an unneeded wake
  598. * of the queue in tx_clean().
  599. */
  600. smp_mb();
  601. if (!arc_emac_tx_avail(priv)) {
  602. netif_stop_queue(ndev);
  603. /* Refresh tx_dirty */
  604. smp_mb();
  605. if (arc_emac_tx_avail(priv))
  606. netif_start_queue(ndev);
  607. }
  608. arc_reg_set(priv, R_STATUS, TXPL_MASK);
  609. return NETDEV_TX_OK;
  610. }
  611. static void arc_emac_set_address_internal(struct net_device *ndev)
  612. {
  613. struct arc_emac_priv *priv = netdev_priv(ndev);
  614. unsigned int addr_low, addr_hi;
  615. addr_low = le32_to_cpu(*(__le32 *)&ndev->dev_addr[0]);
  616. addr_hi = le16_to_cpu(*(__le16 *)&ndev->dev_addr[4]);
  617. arc_reg_set(priv, R_ADDRL, addr_low);
  618. arc_reg_set(priv, R_ADDRH, addr_hi);
  619. }
  620. /**
  621. * arc_emac_set_address - Set the MAC address for this device.
  622. * @ndev: Pointer to net_device structure.
  623. * @p: 6 byte Address to be written as MAC address.
  624. *
  625. * This function copies the HW address from the sockaddr structure to the
  626. * net_device structure and updates the address in HW.
  627. *
  628. * returns: -EBUSY if the net device is busy or 0 if the address is set
  629. * successfully.
  630. */
  631. static int arc_emac_set_address(struct net_device *ndev, void *p)
  632. {
  633. struct sockaddr *addr = p;
  634. if (netif_running(ndev))
  635. return -EBUSY;
  636. if (!is_valid_ether_addr(addr->sa_data))
  637. return -EADDRNOTAVAIL;
  638. eth_hw_addr_set(ndev, addr->sa_data);
  639. arc_emac_set_address_internal(ndev);
  640. return 0;
  641. }
  642. /**
  643. * arc_emac_restart - Restart EMAC
  644. * @ndev: Pointer to net_device structure.
  645. *
  646. * This function do hardware reset of EMAC in order to restore
  647. * network packets reception.
  648. */
  649. static void arc_emac_restart(struct net_device *ndev)
  650. {
  651. struct arc_emac_priv *priv = netdev_priv(ndev);
  652. struct net_device_stats *stats = &ndev->stats;
  653. int i;
  654. if (net_ratelimit())
  655. netdev_warn(ndev, "restarting stalled EMAC\n");
  656. netif_stop_queue(ndev);
  657. /* Disable interrupts */
  658. arc_reg_clr(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
  659. /* Disable EMAC */
  660. arc_reg_clr(priv, R_CTRL, EN_MASK);
  661. /* Return the sk_buff to system */
  662. arc_free_tx_queue(ndev);
  663. /* Clean Tx BD's */
  664. priv->txbd_curr = 0;
  665. priv->txbd_dirty = 0;
  666. memset(priv->txbd, 0, TX_RING_SZ);
  667. for (i = 0; i < RX_BD_NUM; i++) {
  668. struct arc_emac_bd *rxbd = &priv->rxbd[i];
  669. unsigned int info = le32_to_cpu(rxbd->info);
  670. if (!(info & FOR_EMAC)) {
  671. stats->rx_errors++;
  672. stats->rx_dropped++;
  673. }
  674. /* Return ownership to EMAC */
  675. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  676. }
  677. priv->last_rx_bd = 0;
  678. /* Make sure info is visible to EMAC before enable */
  679. wmb();
  680. /* Enable interrupts */
  681. arc_reg_set(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
  682. /* Enable EMAC */
  683. arc_reg_or(priv, R_CTRL, EN_MASK);
  684. netif_start_queue(ndev);
  685. }
  686. static const struct net_device_ops arc_emac_netdev_ops = {
  687. .ndo_open = arc_emac_open,
  688. .ndo_stop = arc_emac_stop,
  689. .ndo_start_xmit = arc_emac_tx,
  690. .ndo_set_mac_address = arc_emac_set_address,
  691. .ndo_get_stats = arc_emac_stats,
  692. .ndo_set_rx_mode = arc_emac_set_rx_mode,
  693. .ndo_eth_ioctl = phy_do_ioctl_running,
  694. #ifdef CONFIG_NET_POLL_CONTROLLER
  695. .ndo_poll_controller = arc_emac_poll_controller,
  696. #endif
  697. };
  698. int arc_emac_probe(struct net_device *ndev, int interface)
  699. {
  700. struct device *dev = ndev->dev.parent;
  701. struct resource res_regs;
  702. struct device_node *phy_node;
  703. struct phy_device *phydev = NULL;
  704. struct arc_emac_priv *priv;
  705. unsigned int id, clock_frequency, irq;
  706. int err;
  707. /* Get PHY from device tree */
  708. phy_node = of_parse_phandle(dev->of_node, "phy", 0);
  709. if (!phy_node) {
  710. dev_err(dev, "failed to retrieve phy description from device tree\n");
  711. return -ENODEV;
  712. }
  713. /* Get EMAC registers base address from device tree */
  714. err = of_address_to_resource(dev->of_node, 0, &res_regs);
  715. if (err) {
  716. dev_err(dev, "failed to retrieve registers base from device tree\n");
  717. err = -ENODEV;
  718. goto out_put_node;
  719. }
  720. /* Get IRQ from device tree */
  721. irq = irq_of_parse_and_map(dev->of_node, 0);
  722. if (!irq) {
  723. dev_err(dev, "failed to retrieve <irq> value from device tree\n");
  724. err = -ENODEV;
  725. goto out_put_node;
  726. }
  727. ndev->netdev_ops = &arc_emac_netdev_ops;
  728. ndev->ethtool_ops = &arc_emac_ethtool_ops;
  729. ndev->watchdog_timeo = TX_TIMEOUT;
  730. priv = netdev_priv(ndev);
  731. priv->dev = dev;
  732. priv->regs = devm_ioremap_resource(dev, &res_regs);
  733. if (IS_ERR(priv->regs)) {
  734. err = PTR_ERR(priv->regs);
  735. goto out_put_node;
  736. }
  737. dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs);
  738. if (priv->clk) {
  739. err = clk_prepare_enable(priv->clk);
  740. if (err) {
  741. dev_err(dev, "failed to enable clock\n");
  742. goto out_put_node;
  743. }
  744. clock_frequency = clk_get_rate(priv->clk);
  745. } else {
  746. /* Get CPU clock frequency from device tree */
  747. if (of_property_read_u32(dev->of_node, "clock-frequency",
  748. &clock_frequency)) {
  749. dev_err(dev, "failed to retrieve <clock-frequency> from device tree\n");
  750. err = -EINVAL;
  751. goto out_put_node;
  752. }
  753. }
  754. id = arc_reg_get(priv, R_ID);
  755. /* Check for EMAC revision 5 or 7, magic number */
  756. if (!(id == 0x0005fd02 || id == 0x0007fd02)) {
  757. dev_err(dev, "ARC EMAC not detected, id=0x%x\n", id);
  758. err = -ENODEV;
  759. goto out_clken;
  760. }
  761. dev_info(dev, "ARC EMAC detected with id: 0x%x\n", id);
  762. /* Set poll rate so that it polls every 1 ms */
  763. arc_reg_set(priv, R_POLLRATE, clock_frequency / 1000000);
  764. ndev->irq = irq;
  765. dev_info(dev, "IRQ is %d\n", ndev->irq);
  766. /* Register interrupt handler for device */
  767. err = devm_request_irq(dev, ndev->irq, arc_emac_intr, 0,
  768. ndev->name, ndev);
  769. if (err) {
  770. dev_err(dev, "could not allocate IRQ\n");
  771. goto out_clken;
  772. }
  773. /* Get MAC address from device tree */
  774. err = of_get_ethdev_address(dev->of_node, ndev);
  775. if (err)
  776. eth_hw_addr_random(ndev);
  777. arc_emac_set_address_internal(ndev);
  778. dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
  779. /* Do 1 allocation instead of 2 separate ones for Rx and Tx BD rings */
  780. priv->rxbd = dmam_alloc_coherent(dev, RX_RING_SZ + TX_RING_SZ,
  781. &priv->rxbd_dma, GFP_KERNEL);
  782. if (!priv->rxbd) {
  783. dev_err(dev, "failed to allocate data buffers\n");
  784. err = -ENOMEM;
  785. goto out_clken;
  786. }
  787. priv->txbd = priv->rxbd + RX_BD_NUM;
  788. priv->txbd_dma = priv->rxbd_dma + RX_RING_SZ;
  789. dev_dbg(dev, "EMAC Device addr: Rx Ring [0x%x], Tx Ring[%x]\n",
  790. (unsigned int)priv->rxbd_dma, (unsigned int)priv->txbd_dma);
  791. err = arc_mdio_probe(priv);
  792. if (err) {
  793. dev_err(dev, "failed to probe MII bus\n");
  794. goto out_clken;
  795. }
  796. phydev = of_phy_connect(ndev, phy_node, arc_emac_adjust_link, 0,
  797. interface);
  798. if (!phydev) {
  799. dev_err(dev, "of_phy_connect() failed\n");
  800. err = -ENODEV;
  801. goto out_mdio;
  802. }
  803. dev_info(dev, "connected to %s phy with id 0x%x\n",
  804. phydev->drv->name, phydev->phy_id);
  805. netif_napi_add_weight(ndev, &priv->napi, arc_emac_poll,
  806. ARC_EMAC_NAPI_WEIGHT);
  807. err = register_netdev(ndev);
  808. if (err) {
  809. dev_err(dev, "failed to register network device\n");
  810. goto out_netif_api;
  811. }
  812. of_node_put(phy_node);
  813. return 0;
  814. out_netif_api:
  815. netif_napi_del(&priv->napi);
  816. phy_disconnect(phydev);
  817. out_mdio:
  818. arc_mdio_remove(priv);
  819. out_clken:
  820. if (priv->clk)
  821. clk_disable_unprepare(priv->clk);
  822. out_put_node:
  823. of_node_put(phy_node);
  824. return err;
  825. }
  826. EXPORT_SYMBOL_GPL(arc_emac_probe);
  827. int arc_emac_remove(struct net_device *ndev)
  828. {
  829. struct arc_emac_priv *priv = netdev_priv(ndev);
  830. phy_disconnect(ndev->phydev);
  831. arc_mdio_remove(priv);
  832. unregister_netdev(ndev);
  833. netif_napi_del(&priv->napi);
  834. if (!IS_ERR(priv->clk))
  835. clk_disable_unprepare(priv->clk);
  836. return 0;
  837. }
  838. EXPORT_SYMBOL_GPL(arc_emac_remove);
  839. MODULE_AUTHOR("Alexey Brodkin <[email protected]>");
  840. MODULE_DESCRIPTION("ARC EMAC driver");
  841. MODULE_LICENSE("GPL");