winbond.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2005, Intec Automation Inc.
  4. * Copyright (C) 2014, Freescale Semiconductor, Inc.
  5. */
  6. #include <linux/mtd/spi-nor.h>
  7. #include "core.h"
  8. #define WINBOND_NOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
  9. #define WINBOND_NOR_OP_WREAR 0xc5 /* Write Extended Address Register */
  10. #define WINBOND_NOR_WREAR_OP(buf) \
  11. SPI_MEM_OP(SPI_MEM_OP_CMD(WINBOND_NOR_OP_WREAR, 0), \
  12. SPI_MEM_OP_NO_ADDR, \
  13. SPI_MEM_OP_NO_DUMMY, \
  14. SPI_MEM_OP_DATA_OUT(1, buf, 0))
  15. static int
  16. w25q256_post_bfpt_fixups(struct spi_nor *nor,
  17. const struct sfdp_parameter_header *bfpt_header,
  18. const struct sfdp_bfpt *bfpt)
  19. {
  20. /*
  21. * W25Q256JV supports 4B opcodes but W25Q256FV does not.
  22. * Unfortunately, Winbond has re-used the same JEDEC ID for both
  23. * variants which prevents us from defining a new entry in the parts
  24. * table.
  25. * To differentiate between W25Q256JV and W25Q256FV check SFDP header
  26. * version: only JV has JESD216A compliant structure (version 5).
  27. */
  28. if (bfpt_header->major == SFDP_JESD216_MAJOR &&
  29. bfpt_header->minor == SFDP_JESD216A_MINOR)
  30. nor->flags |= SNOR_F_4B_OPCODES;
  31. return 0;
  32. }
  33. static const struct spi_nor_fixups w25q256_fixups = {
  34. .post_bfpt = w25q256_post_bfpt_fixups,
  35. };
  36. static const struct flash_info winbond_nor_parts[] = {
  37. /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
  38. { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1)
  39. NO_SFDP_FLAGS(SECT_4K) },
  40. { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2)
  41. NO_SFDP_FLAGS(SECT_4K) },
  42. { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4)
  43. NO_SFDP_FLAGS(SECT_4K) },
  44. { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8)
  45. NO_SFDP_FLAGS(SECT_4K) },
  46. { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16)
  47. NO_SFDP_FLAGS(SECT_4K) },
  48. { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32)
  49. NO_SFDP_FLAGS(SECT_4K) },
  50. { "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32)
  51. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  52. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  53. SPI_NOR_QUAD_READ) },
  54. { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64)
  55. NO_SFDP_FLAGS(SECT_4K) },
  56. { "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32)
  57. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  58. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  59. SPI_NOR_QUAD_READ) },
  60. { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4)
  61. NO_SFDP_FLAGS(SECT_4K) },
  62. { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4)
  63. NO_SFDP_FLAGS(SECT_4K) },
  64. { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4)
  65. NO_SFDP_FLAGS(SECT_4K) },
  66. { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64)
  67. NO_SFDP_FLAGS(SECT_4K) },
  68. { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64)
  69. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  70. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
  71. OTP_INFO(256, 3, 0x1000, 0x1000) },
  72. { "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64)
  73. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  74. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  75. SPI_NOR_QUAD_READ) },
  76. { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64)
  77. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  78. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
  79. OTP_INFO(256, 3, 0x1000, 0x1000) },
  80. { "w25q64jwm", INFO(0xef8017, 0, 64 * 1024, 128)
  81. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  82. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  83. SPI_NOR_QUAD_READ) },
  84. { "w25q128jwm", INFO(0xef8018, 0, 64 * 1024, 256)
  85. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  86. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  87. SPI_NOR_QUAD_READ) },
  88. { "w25q256jwm", INFO(0xef8019, 0, 64 * 1024, 512)
  89. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  90. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  91. SPI_NOR_QUAD_READ) },
  92. { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128)
  93. NO_SFDP_FLAGS(SECT_4K) },
  94. { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128)
  95. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  96. SPI_NOR_QUAD_READ) },
  97. { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128)
  98. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  99. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  100. SPI_NOR_QUAD_READ) },
  101. { "w25q64jvm", INFO(0xef7017, 0, 64 * 1024, 128)
  102. NO_SFDP_FLAGS(SECT_4K) },
  103. { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256)
  104. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  105. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  106. SPI_NOR_QUAD_READ) },
  107. { "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256)
  108. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  109. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  110. SPI_NOR_QUAD_READ) },
  111. { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16)
  112. NO_SFDP_FLAGS(SECT_4K) },
  113. { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16)
  114. NO_SFDP_FLAGS(SECT_4K) },
  115. { "w25q128", INFO(0xef4018, 0, 0, 0)
  116. PARSE_SFDP
  117. FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  118. { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512)
  119. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
  120. .fixups = &w25q256_fixups },
  121. { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512)
  122. PARSE_SFDP },
  123. { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512)
  124. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  125. SPI_NOR_QUAD_READ) },
  126. { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024)
  127. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ |
  128. SPI_NOR_DUAL_READ) },
  129. { "w25q512nwm", INFO(0xef8020, 0, 64 * 1024, 1024)
  130. PARSE_SFDP
  131. OTP_INFO(256, 3, 0x1000, 0x1000) },
  132. { "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024)
  133. NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  134. SPI_NOR_QUAD_READ) },
  135. };
  136. /**
  137. * winbond_nor_write_ear() - Write Extended Address Register.
  138. * @nor: pointer to 'struct spi_nor'.
  139. * @ear: value to write to the Extended Address Register.
  140. *
  141. * Return: 0 on success, -errno otherwise.
  142. */
  143. static int winbond_nor_write_ear(struct spi_nor *nor, u8 ear)
  144. {
  145. int ret;
  146. nor->bouncebuf[0] = ear;
  147. if (nor->spimem) {
  148. struct spi_mem_op op = WINBOND_NOR_WREAR_OP(nor->bouncebuf);
  149. spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
  150. ret = spi_mem_exec_op(nor->spimem, &op);
  151. } else {
  152. ret = spi_nor_controller_ops_write_reg(nor,
  153. WINBOND_NOR_OP_WREAR,
  154. nor->bouncebuf, 1);
  155. }
  156. if (ret)
  157. dev_dbg(nor->dev, "error %d writing EAR\n", ret);
  158. return ret;
  159. }
  160. /**
  161. * winbond_nor_set_4byte_addr_mode() - Set 4-byte address mode for Winbond
  162. * flashes.
  163. * @nor: pointer to 'struct spi_nor'.
  164. * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
  165. * address mode.
  166. *
  167. * Return: 0 on success, -errno otherwise.
  168. */
  169. static int winbond_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
  170. {
  171. int ret;
  172. ret = spi_nor_set_4byte_addr_mode(nor, enable);
  173. if (ret || enable)
  174. return ret;
  175. /*
  176. * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
  177. * Register to be set to 1, so all 3-byte-address reads come from the
  178. * second 16M. We must clear the register to enable normal behavior.
  179. */
  180. ret = spi_nor_write_enable(nor);
  181. if (ret)
  182. return ret;
  183. ret = winbond_nor_write_ear(nor, 0);
  184. if (ret)
  185. return ret;
  186. return spi_nor_write_disable(nor);
  187. }
  188. static const struct spi_nor_otp_ops winbond_nor_otp_ops = {
  189. .read = spi_nor_otp_read_secr,
  190. .write = spi_nor_otp_write_secr,
  191. .erase = spi_nor_otp_erase_secr,
  192. .lock = spi_nor_otp_lock_sr2,
  193. .is_locked = spi_nor_otp_is_locked_sr2,
  194. };
  195. static void winbond_nor_default_init(struct spi_nor *nor)
  196. {
  197. nor->params->set_4byte_addr_mode = winbond_nor_set_4byte_addr_mode;
  198. }
  199. static void winbond_nor_late_init(struct spi_nor *nor)
  200. {
  201. if (nor->params->otp.org->n_regions)
  202. nor->params->otp.ops = &winbond_nor_otp_ops;
  203. }
  204. static const struct spi_nor_fixups winbond_nor_fixups = {
  205. .default_init = winbond_nor_default_init,
  206. .late_init = winbond_nor_late_init,
  207. };
  208. const struct spi_nor_manufacturer spi_nor_winbond = {
  209. .name = "winbond",
  210. .parts = winbond_nor_parts,
  211. .nparts = ARRAY_SIZE(winbond_nor_parts),
  212. .fixups = &winbond_nor_fixups,
  213. };