qcom-i2c-pmic.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #define pr_fmt(fmt) "I2C PMIC: %s: " fmt, __func__
  7. #include <linux/bitops.h>
  8. #include <linux/i2c.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/irq.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/module.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/pinctrl/consumer.h>
  15. #include <linux/qti-regmap-debugfs.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #define I2C_INTR_STATUS_BASE 0x0550
  19. #define INT_RT_STS_OFFSET 0x10
  20. #define INT_SET_TYPE_OFFSET 0x11
  21. #define INT_POL_HIGH_OFFSET 0x12
  22. #define INT_POL_LOW_OFFSET 0x13
  23. #define INT_LATCHED_CLR_OFFSET 0x14
  24. #define INT_EN_SET_OFFSET 0x15
  25. #define INT_EN_CLR_OFFSET 0x16
  26. #define INT_LATCHED_STS_OFFSET 0x18
  27. #define INT_PENDING_STS_OFFSET 0x19
  28. #define INT_MID_SEL_OFFSET 0x1A
  29. #define INT_MID_SEL_MASK GENMASK(1, 0)
  30. #define INT_PRIORITY_OFFSET 0x1B
  31. #define INT_PRIORITY_BIT BIT(0)
  32. enum {
  33. IRQ_SET_TYPE = 0,
  34. IRQ_POL_HIGH,
  35. IRQ_POL_LOW,
  36. IRQ_LATCHED_CLR, /* not needed but makes life easy */
  37. IRQ_EN_SET,
  38. IRQ_MAX_REGS,
  39. };
  40. struct i2c_pmic_periph {
  41. void *data;
  42. u16 addr;
  43. u8 cached[IRQ_MAX_REGS];
  44. u8 synced[IRQ_MAX_REGS];
  45. u8 wake;
  46. struct mutex lock;
  47. };
  48. struct i2c_pmic {
  49. struct device *dev;
  50. struct regmap *regmap;
  51. struct irq_domain *domain;
  52. struct i2c_pmic_periph *periph;
  53. struct pinctrl *pinctrl;
  54. struct mutex irq_complete;
  55. const char *pinctrl_name;
  56. int num_periphs;
  57. int summary_irq;
  58. bool resume_completed;
  59. bool irq_waiting;
  60. bool toggle_stat;
  61. };
  62. static void i2c_pmic_irq_bus_lock(struct irq_data *d)
  63. {
  64. struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d);
  65. mutex_lock(&periph->lock);
  66. }
  67. static void i2c_pmic_sync_type_polarity(struct i2c_pmic *chip,
  68. struct i2c_pmic_periph *periph)
  69. {
  70. int rc;
  71. /* did any irq type change? */
  72. if (periph->cached[IRQ_SET_TYPE] ^ periph->synced[IRQ_SET_TYPE]) {
  73. rc = regmap_write(chip->regmap,
  74. periph->addr | INT_SET_TYPE_OFFSET,
  75. periph->cached[IRQ_SET_TYPE]);
  76. if (rc < 0) {
  77. pr_err("Couldn't set periph 0x%04x irqs 0x%02x type rc=%d\n",
  78. periph->addr, periph->cached[IRQ_SET_TYPE], rc);
  79. return;
  80. }
  81. periph->synced[IRQ_SET_TYPE] = periph->cached[IRQ_SET_TYPE];
  82. }
  83. /* did any polarity high change? */
  84. if (periph->cached[IRQ_POL_HIGH] ^ periph->synced[IRQ_POL_HIGH]) {
  85. rc = regmap_write(chip->regmap,
  86. periph->addr | INT_POL_HIGH_OFFSET,
  87. periph->cached[IRQ_POL_HIGH]);
  88. if (rc < 0) {
  89. pr_err("Couldn't set periph 0x%04x irqs 0x%02x polarity high rc=%d\n",
  90. periph->addr, periph->cached[IRQ_POL_HIGH], rc);
  91. return;
  92. }
  93. periph->synced[IRQ_POL_HIGH] = periph->cached[IRQ_POL_HIGH];
  94. }
  95. /* did any polarity low change? */
  96. if (periph->cached[IRQ_POL_LOW] ^ periph->synced[IRQ_POL_LOW]) {
  97. rc = regmap_write(chip->regmap,
  98. periph->addr | INT_POL_LOW_OFFSET,
  99. periph->cached[IRQ_POL_LOW]);
  100. if (rc < 0) {
  101. pr_err("Couldn't set periph 0x%04x irqs 0x%02x polarity low rc=%d\n",
  102. periph->addr, periph->cached[IRQ_POL_LOW], rc);
  103. return;
  104. }
  105. periph->synced[IRQ_POL_LOW] = periph->cached[IRQ_POL_LOW];
  106. }
  107. }
  108. static void i2c_pmic_sync_enable(struct i2c_pmic *chip,
  109. struct i2c_pmic_periph *periph)
  110. {
  111. u8 en_set, en_clr;
  112. int rc;
  113. /* determine which irqs were enabled and which were disabled */
  114. en_clr = periph->synced[IRQ_EN_SET] & ~periph->cached[IRQ_EN_SET];
  115. en_set = ~periph->synced[IRQ_EN_SET] & periph->cached[IRQ_EN_SET];
  116. /* were any irqs disabled? */
  117. if (en_clr) {
  118. rc = regmap_write(chip->regmap,
  119. periph->addr | INT_EN_CLR_OFFSET, en_clr);
  120. if (rc < 0) {
  121. pr_err("Couldn't disable periph 0x%04x irqs 0x%02x rc=%d\n",
  122. periph->addr, en_clr, rc);
  123. return;
  124. }
  125. }
  126. /* were any irqs enabled? */
  127. if (en_set) {
  128. rc = regmap_write(chip->regmap,
  129. periph->addr | INT_EN_SET_OFFSET, en_set);
  130. if (rc < 0) {
  131. pr_err("Couldn't enable periph 0x%04x irqs 0x%02x rc=%d\n",
  132. periph->addr, en_set, rc);
  133. return;
  134. }
  135. }
  136. /* irq enabled status was written to hardware */
  137. periph->synced[IRQ_EN_SET] = periph->cached[IRQ_EN_SET];
  138. }
  139. static void i2c_pmic_irq_bus_sync_unlock(struct irq_data *d)
  140. {
  141. struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d);
  142. struct i2c_pmic *chip = periph->data;
  143. i2c_pmic_sync_type_polarity(chip, periph);
  144. i2c_pmic_sync_enable(chip, periph);
  145. mutex_unlock(&periph->lock);
  146. }
  147. static void i2c_pmic_irq_disable(struct irq_data *d)
  148. {
  149. struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d);
  150. periph->cached[IRQ_EN_SET] &= ~d->hwirq & 0xFF;
  151. }
  152. static void i2c_pmic_irq_enable(struct irq_data *d)
  153. {
  154. struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d);
  155. periph->cached[IRQ_EN_SET] |= d->hwirq & 0xFF;
  156. }
  157. static int i2c_pmic_irq_set_type(struct irq_data *d, unsigned int irq_type)
  158. {
  159. struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d);
  160. switch (irq_type) {
  161. case IRQ_TYPE_EDGE_RISING:
  162. periph->cached[IRQ_SET_TYPE] |= d->hwirq & 0xFF;
  163. periph->cached[IRQ_POL_HIGH] |= d->hwirq & 0xFF;
  164. periph->cached[IRQ_POL_LOW] &= ~d->hwirq & 0xFF;
  165. break;
  166. case IRQ_TYPE_EDGE_FALLING:
  167. periph->cached[IRQ_SET_TYPE] |= d->hwirq & 0xFF;
  168. periph->cached[IRQ_POL_HIGH] &= ~d->hwirq & 0xFF;
  169. periph->cached[IRQ_POL_LOW] |= d->hwirq & 0xFF;
  170. break;
  171. case IRQ_TYPE_EDGE_BOTH:
  172. periph->cached[IRQ_SET_TYPE] |= d->hwirq & 0xFF;
  173. periph->cached[IRQ_POL_HIGH] |= d->hwirq & 0xFF;
  174. periph->cached[IRQ_POL_LOW] |= d->hwirq & 0xFF;
  175. break;
  176. case IRQ_TYPE_LEVEL_HIGH:
  177. periph->cached[IRQ_SET_TYPE] &= ~d->hwirq & 0xFF;
  178. periph->cached[IRQ_POL_HIGH] |= d->hwirq & 0xFF;
  179. periph->cached[IRQ_POL_LOW] &= ~d->hwirq & 0xFF;
  180. break;
  181. case IRQ_TYPE_LEVEL_LOW:
  182. periph->cached[IRQ_SET_TYPE] &= ~d->hwirq & 0xFF;
  183. periph->cached[IRQ_POL_HIGH] &= ~d->hwirq & 0xFF;
  184. periph->cached[IRQ_POL_LOW] |= d->hwirq & 0xFF;
  185. break;
  186. default:
  187. pr_err("irq type 0x%04x is not supported\n", irq_type);
  188. return -EINVAL;
  189. }
  190. return 0;
  191. }
  192. #ifdef CONFIG_PM_SLEEP
  193. static int i2c_pmic_irq_set_wake(struct irq_data *d, unsigned int on)
  194. {
  195. struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d);
  196. if (on)
  197. periph->wake |= d->hwirq & 0xFF;
  198. else
  199. periph->wake &= ~d->hwirq & 0xFF;
  200. return 0;
  201. }
  202. #else
  203. #define i2c_pmic_irq_set_wake NULL
  204. #endif
  205. static struct irq_chip i2c_pmic_irq_chip = {
  206. .name = "i2c_pmic_irq_chip",
  207. .irq_bus_lock = i2c_pmic_irq_bus_lock,
  208. .irq_bus_sync_unlock = i2c_pmic_irq_bus_sync_unlock,
  209. .irq_disable = i2c_pmic_irq_disable,
  210. .irq_enable = i2c_pmic_irq_enable,
  211. .irq_set_type = i2c_pmic_irq_set_type,
  212. .irq_set_wake = i2c_pmic_irq_set_wake,
  213. };
  214. static struct i2c_pmic_periph *i2c_pmic_find_periph(struct i2c_pmic *chip,
  215. irq_hw_number_t hwirq)
  216. {
  217. int i;
  218. for (i = 0; i < chip->num_periphs; i++)
  219. if (chip->periph[i].addr == (hwirq & 0xFF00))
  220. return &chip->periph[i];
  221. pr_err_ratelimited("Couldn't find periph struct for hwirq 0x%04lx\n",
  222. hwirq);
  223. return NULL;
  224. }
  225. static int i2c_pmic_domain_map(struct irq_domain *d, unsigned int virq,
  226. irq_hw_number_t hwirq)
  227. {
  228. struct i2c_pmic *chip = d->host_data;
  229. struct i2c_pmic_periph *periph = i2c_pmic_find_periph(chip, hwirq);
  230. if (!periph)
  231. return -ENODEV;
  232. irq_set_chip_data(virq, periph);
  233. irq_set_chip_and_handler(virq, &i2c_pmic_irq_chip, handle_level_irq);
  234. irq_set_nested_thread(virq, 1);
  235. irq_set_noprobe(virq);
  236. return 0;
  237. }
  238. static int i2c_pmic_domain_xlate(struct irq_domain *d,
  239. struct device_node *ctrlr, const u32 *intspec,
  240. unsigned int intsize, unsigned long *out_hwirq,
  241. unsigned int *out_type)
  242. {
  243. if (intsize != 3)
  244. return -EINVAL;
  245. if (intspec[0] > 0xFF || intspec[1] > 0x7 ||
  246. intspec[2] > IRQ_TYPE_SENSE_MASK)
  247. return -EINVAL;
  248. /*
  249. * Interrupt specifiers are triplets
  250. * <peripheral-address, irq-number, IRQ_TYPE_*>
  251. *
  252. * peripheral-address - The base address of the peripheral
  253. * irq-number - The zero based bit position of the peripheral's
  254. * interrupt registers corresponding to the irq
  255. * where the LSB is 0 and the MSB is 7
  256. * IRQ_TYPE_* - Please refer to linux/irq.h
  257. */
  258. *out_hwirq = intspec[0] << 8 | BIT(intspec[1]);
  259. *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
  260. return 0;
  261. }
  262. static const struct irq_domain_ops i2c_pmic_domain_ops = {
  263. .map = i2c_pmic_domain_map,
  264. .xlate = i2c_pmic_domain_xlate,
  265. };
  266. static void i2c_pmic_irq_ack_now(struct i2c_pmic *chip, u16 hwirq)
  267. {
  268. int rc;
  269. rc = regmap_write(chip->regmap,
  270. (hwirq & 0xFF00) | INT_LATCHED_CLR_OFFSET,
  271. hwirq & 0xFF);
  272. if (rc < 0)
  273. pr_err_ratelimited("Couldn't ack 0x%04x rc=%d\n", hwirq, rc);
  274. }
  275. static void i2c_pmic_irq_disable_now(struct i2c_pmic *chip, u16 hwirq)
  276. {
  277. struct i2c_pmic_periph *periph = i2c_pmic_find_periph(chip, hwirq);
  278. int rc;
  279. if (!periph)
  280. return;
  281. mutex_lock(&periph->lock);
  282. periph->cached[IRQ_EN_SET] &= ~hwirq & 0xFF;
  283. rc = regmap_write(chip->regmap,
  284. (hwirq & 0xFF00) | INT_EN_CLR_OFFSET,
  285. hwirq & 0xFF);
  286. if (rc < 0) {
  287. pr_err_ratelimited("Couldn't disable irq 0x%04x rc=%d\n",
  288. hwirq, rc);
  289. goto unlock;
  290. }
  291. periph->synced[IRQ_EN_SET] = periph->cached[IRQ_EN_SET];
  292. unlock:
  293. mutex_unlock(&periph->lock);
  294. }
  295. static void i2c_pmic_periph_status_handler(struct i2c_pmic *chip,
  296. u16 periph_address, u8 periph_status)
  297. {
  298. unsigned int hwirq, virq;
  299. int i;
  300. while (periph_status) {
  301. i = ffs(periph_status) - 1;
  302. periph_status &= ~BIT(i);
  303. hwirq = periph_address | BIT(i);
  304. virq = irq_find_mapping(chip->domain, hwirq);
  305. if (virq == 0) {
  306. pr_err_ratelimited("Couldn't find mapping; disabling 0x%04x\n",
  307. hwirq);
  308. i2c_pmic_irq_disable_now(chip, hwirq);
  309. continue;
  310. }
  311. handle_nested_irq(virq);
  312. i2c_pmic_irq_ack_now(chip, hwirq);
  313. }
  314. }
  315. static void i2c_pmic_summary_status_handler(struct i2c_pmic *chip,
  316. struct i2c_pmic_periph *periph,
  317. u8 summary_status)
  318. {
  319. unsigned int periph_status;
  320. int rc, i;
  321. while (summary_status) {
  322. i = ffs(summary_status) - 1;
  323. summary_status &= ~BIT(i);
  324. rc = regmap_read(chip->regmap,
  325. periph[i].addr | INT_LATCHED_STS_OFFSET,
  326. &periph_status);
  327. if (rc < 0) {
  328. pr_err_ratelimited("Couldn't read 0x%04x | INT_LATCHED_STS rc=%d\n",
  329. periph[i].addr, rc);
  330. continue;
  331. }
  332. i2c_pmic_periph_status_handler(chip, periph[i].addr,
  333. periph_status);
  334. }
  335. }
  336. static irqreturn_t i2c_pmic_irq_handler(int irq, void *dev_id)
  337. {
  338. struct i2c_pmic *chip = dev_id;
  339. struct i2c_pmic_periph *periph;
  340. unsigned int summary_status;
  341. int rc, i;
  342. mutex_lock(&chip->irq_complete);
  343. chip->irq_waiting = true;
  344. if (!chip->resume_completed) {
  345. pr_debug("IRQ triggered before device-resume\n");
  346. disable_irq_nosync(irq);
  347. mutex_unlock(&chip->irq_complete);
  348. return IRQ_HANDLED;
  349. }
  350. chip->irq_waiting = false;
  351. for (i = 0; i < DIV_ROUND_UP(chip->num_periphs, BITS_PER_BYTE); i++) {
  352. rc = regmap_read(chip->regmap, I2C_INTR_STATUS_BASE + i,
  353. &summary_status);
  354. if (rc < 0) {
  355. pr_err_ratelimited("Couldn't read I2C_INTR_STATUS%d rc=%d\n",
  356. i, rc);
  357. continue;
  358. }
  359. if (summary_status == 0)
  360. continue;
  361. periph = &chip->periph[i * 8];
  362. i2c_pmic_summary_status_handler(chip, periph, summary_status);
  363. }
  364. mutex_unlock(&chip->irq_complete);
  365. return IRQ_HANDLED;
  366. }
  367. static int i2c_pmic_parse_dt(struct i2c_pmic *chip)
  368. {
  369. struct device_node *node = chip->dev->of_node;
  370. int rc, i;
  371. u32 temp;
  372. if (!node) {
  373. pr_err("missing device tree\n");
  374. return -EINVAL;
  375. }
  376. chip->num_periphs = of_property_count_u32_elems(node,
  377. "qcom,periph-map");
  378. if (chip->num_periphs < 0) {
  379. pr_err("missing qcom,periph-map property rc=%d\n",
  380. chip->num_periphs);
  381. return chip->num_periphs;
  382. }
  383. if (chip->num_periphs == 0) {
  384. pr_err("qcom,periph-map must contain at least one address\n");
  385. return -EINVAL;
  386. }
  387. chip->periph = devm_kcalloc(chip->dev, chip->num_periphs,
  388. sizeof(*chip->periph), GFP_KERNEL);
  389. if (!chip->periph)
  390. return -ENOMEM;
  391. for (i = 0; i < chip->num_periphs; i++) {
  392. rc = of_property_read_u32_index(node, "qcom,periph-map",
  393. i, &temp);
  394. if (rc < 0) {
  395. pr_err("Couldn't read qcom,periph-map[%d] rc=%d\n",
  396. i, rc);
  397. return rc;
  398. }
  399. chip->periph[i].addr = (u16)(temp << 8);
  400. chip->periph[i].data = chip;
  401. mutex_init(&chip->periph[i].lock);
  402. }
  403. of_property_read_string(node, "pinctrl-names", &chip->pinctrl_name);
  404. chip->toggle_stat = of_property_read_bool(node,
  405. "qcom,enable-toggle-stat");
  406. return rc;
  407. }
  408. #define MAX_I2C_RETRIES 3
  409. static int i2c_pmic_read(struct regmap *map, unsigned int reg, void *val,
  410. size_t val_count)
  411. {
  412. int rc, retries = 0;
  413. do {
  414. rc = regmap_bulk_read(map, reg, val, val_count);
  415. } while (rc == -ENOTCONN && retries++ < MAX_I2C_RETRIES);
  416. if (retries > 1)
  417. pr_err("i2c_pmic_read failed for %d retries, rc = %d\n",
  418. retries - 1, rc);
  419. return rc;
  420. }
  421. static int i2c_pmic_determine_initial_status(struct i2c_pmic *chip)
  422. {
  423. int rc, i;
  424. for (i = 0; i < chip->num_periphs; i++) {
  425. rc = i2c_pmic_read(chip->regmap,
  426. chip->periph[i].addr | INT_SET_TYPE_OFFSET,
  427. chip->periph[i].cached, IRQ_MAX_REGS);
  428. if (rc < 0) {
  429. pr_err("Couldn't read irq data rc=%d\n", rc);
  430. return rc;
  431. }
  432. memcpy(chip->periph[i].synced, chip->periph[i].cached,
  433. IRQ_MAX_REGS * sizeof(*chip->periph[i].synced));
  434. }
  435. return 0;
  436. }
  437. #define INT_TEST_OFFSET 0xE0
  438. #define INT_TEST_MODE_EN_BIT BIT(7)
  439. #define INT_TEST_VAL_OFFSET 0xE1
  440. #define INT_0_BIT BIT(0)
  441. static int i2c_pmic_toggle_stat(struct i2c_pmic *chip)
  442. {
  443. int rc = 0, i;
  444. if (!chip->toggle_stat || !chip->num_periphs)
  445. return 0;
  446. rc = regmap_write(chip->regmap,
  447. chip->periph[0].addr | INT_EN_SET_OFFSET,
  448. INT_0_BIT);
  449. if (rc < 0) {
  450. pr_err("Couldn't write to int_en_set rc=%d\n", rc);
  451. return rc;
  452. }
  453. rc = regmap_write(chip->regmap, chip->periph[0].addr | INT_TEST_OFFSET,
  454. INT_TEST_MODE_EN_BIT);
  455. if (rc < 0) {
  456. pr_err("Couldn't write to int_test rc=%d\n", rc);
  457. return rc;
  458. }
  459. for (i = 0; i < 5; i++) {
  460. rc = regmap_write(chip->regmap,
  461. chip->periph[0].addr | INT_TEST_VAL_OFFSET,
  462. INT_0_BIT);
  463. if (rc < 0) {
  464. pr_err("Couldn't write to int_test_val rc=%d\n", rc);
  465. goto exit;
  466. }
  467. usleep_range(5000, 5500);
  468. rc = regmap_write(chip->regmap,
  469. chip->periph[0].addr | INT_TEST_VAL_OFFSET,
  470. 0);
  471. if (rc < 0) {
  472. pr_err("Couldn't write to int_test_val rc=%d\n", rc);
  473. goto exit;
  474. }
  475. rc = regmap_write(chip->regmap,
  476. chip->periph[0].addr | INT_LATCHED_CLR_OFFSET,
  477. INT_0_BIT);
  478. if (rc < 0) {
  479. pr_err("Couldn't write to int_latched_clr rc=%d\n", rc);
  480. goto exit;
  481. }
  482. usleep_range(5000, 5500);
  483. }
  484. exit:
  485. regmap_write(chip->regmap, chip->periph[0].addr | INT_TEST_OFFSET, 0);
  486. regmap_write(chip->regmap, chip->periph[0].addr | INT_EN_CLR_OFFSET,
  487. INT_0_BIT);
  488. return rc;
  489. }
  490. static struct regmap_config i2c_pmic_regmap_config = {
  491. .reg_bits = 16,
  492. .val_bits = 8,
  493. .max_register = 0xFFFF,
  494. };
  495. static int i2c_pmic_probe(struct i2c_client *client,
  496. const struct i2c_device_id *id)
  497. {
  498. struct i2c_pmic *chip;
  499. int rc = 0;
  500. chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
  501. if (!chip)
  502. return -ENOMEM;
  503. chip->dev = &client->dev;
  504. chip->regmap = devm_regmap_init_i2c(client, &i2c_pmic_regmap_config);
  505. if (!chip->regmap)
  506. return -ENODEV;
  507. devm_regmap_qti_debugfs_register(chip->dev, chip->regmap);
  508. i2c_set_clientdata(client, chip);
  509. chip->summary_irq = -EINVAL;
  510. if (!of_property_read_bool(chip->dev->of_node, "interrupt-controller"))
  511. goto probe_children;
  512. chip->domain = irq_domain_add_tree(client->dev.of_node,
  513. &i2c_pmic_domain_ops, chip);
  514. if (!chip->domain) {
  515. rc = -ENOMEM;
  516. goto cleanup;
  517. }
  518. rc = i2c_pmic_parse_dt(chip);
  519. if (rc < 0) {
  520. pr_err("Couldn't parse device tree rc=%d\n", rc);
  521. goto cleanup;
  522. }
  523. rc = i2c_pmic_determine_initial_status(chip);
  524. if (rc < 0) {
  525. pr_err("Couldn't determine initial status rc=%d\n", rc);
  526. goto cleanup;
  527. }
  528. if (chip->pinctrl_name) {
  529. chip->pinctrl = devm_pinctrl_get_select(chip->dev,
  530. chip->pinctrl_name);
  531. if (IS_ERR(chip->pinctrl)) {
  532. pr_err("Couldn't select %s pinctrl rc=%ld\n",
  533. chip->pinctrl_name, PTR_ERR(chip->pinctrl));
  534. rc = PTR_ERR(chip->pinctrl);
  535. goto cleanup;
  536. }
  537. }
  538. chip->resume_completed = true;
  539. mutex_init(&chip->irq_complete);
  540. rc = i2c_pmic_toggle_stat(chip);
  541. if (rc < 0) {
  542. pr_err("Couldn't toggle stat rc=%d\n", rc);
  543. goto cleanup;
  544. }
  545. rc = devm_request_threaded_irq(&client->dev, client->irq, NULL,
  546. i2c_pmic_irq_handler,
  547. IRQF_ONESHOT | IRQF_SHARED,
  548. "i2c_pmic_stat_irq", chip);
  549. if (rc < 0) {
  550. pr_err("Couldn't request irq %d rc=%d\n", client->irq, rc);
  551. goto cleanup;
  552. }
  553. chip->summary_irq = client->irq;
  554. enable_irq_wake(client->irq);
  555. probe_children:
  556. of_platform_populate(chip->dev->of_node, NULL, NULL, chip->dev);
  557. pr_info("I2C PMIC probe successful\n");
  558. return rc;
  559. cleanup:
  560. if (chip->domain)
  561. irq_domain_remove(chip->domain);
  562. i2c_set_clientdata(client, NULL);
  563. return rc;
  564. }
  565. static void i2c_pmic_remove(struct i2c_client *client)
  566. {
  567. struct i2c_pmic *chip = i2c_get_clientdata(client);
  568. of_platform_depopulate(chip->dev);
  569. if (chip->domain)
  570. irq_domain_remove(chip->domain);
  571. i2c_set_clientdata(client, NULL);
  572. }
  573. #ifdef CONFIG_PM_SLEEP
  574. static int i2c_pmic_suspend_noirq(struct device *dev)
  575. {
  576. struct i2c_pmic *chip = dev_get_drvdata(dev);
  577. if (chip->irq_waiting) {
  578. pr_err_ratelimited("Aborting suspend, an interrupt was detected while suspending\n");
  579. return -EBUSY;
  580. }
  581. return 0;
  582. }
  583. static int i2c_pmic_suspend(struct device *dev)
  584. {
  585. struct i2c_pmic *chip = dev_get_drvdata(dev);
  586. struct i2c_pmic_periph *periph;
  587. int rc = 0, i;
  588. if (chip->summary_irq < 0)
  589. return 0;
  590. for (i = 0; i < chip->num_periphs; i++) {
  591. periph = &chip->periph[i];
  592. rc = regmap_write(chip->regmap,
  593. periph->addr | INT_EN_CLR_OFFSET, 0xFF);
  594. if (rc < 0) {
  595. pr_err_ratelimited("Couldn't clear 0x%04x irqs rc=%d\n",
  596. periph->addr, rc);
  597. continue;
  598. }
  599. rc = regmap_write(chip->regmap,
  600. periph->addr | INT_EN_SET_OFFSET,
  601. periph->wake);
  602. if (rc < 0)
  603. pr_err_ratelimited("Couldn't enable 0x%04x wake irqs 0x%02x rc=%d\n",
  604. periph->addr, periph->wake, rc);
  605. }
  606. if (!rc) {
  607. mutex_lock(&chip->irq_complete);
  608. chip->resume_completed = false;
  609. mutex_unlock(&chip->irq_complete);
  610. }
  611. return rc;
  612. }
  613. static int i2c_pmic_resume(struct device *dev)
  614. {
  615. struct i2c_pmic *chip = dev_get_drvdata(dev);
  616. struct i2c_pmic_periph *periph;
  617. int rc = 0, i;
  618. if (chip->summary_irq < 0)
  619. return 0;
  620. for (i = 0; i < chip->num_periphs; i++) {
  621. periph = &chip->periph[i];
  622. rc = regmap_write(chip->regmap,
  623. periph->addr | INT_EN_CLR_OFFSET, 0xFF);
  624. if (rc < 0) {
  625. pr_err("Couldn't clear 0x%04x irqs rc=%d\n",
  626. periph->addr, rc);
  627. continue;
  628. }
  629. rc = regmap_write(chip->regmap,
  630. periph->addr | INT_EN_SET_OFFSET,
  631. periph->synced[IRQ_EN_SET]);
  632. if (rc < 0)
  633. pr_err("Couldn't restore 0x%04x synced irqs 0x%02x rc=%d\n",
  634. periph->addr, periph->synced[IRQ_EN_SET], rc);
  635. }
  636. mutex_lock(&chip->irq_complete);
  637. chip->resume_completed = true;
  638. if (chip->irq_waiting) {
  639. mutex_unlock(&chip->irq_complete);
  640. /* irq was pending, call the handler */
  641. i2c_pmic_irq_handler(chip->summary_irq, chip);
  642. enable_irq(chip->summary_irq);
  643. } else {
  644. mutex_unlock(&chip->irq_complete);
  645. }
  646. return rc;
  647. }
  648. #else
  649. static int i2c_pmic_suspend(struct device *dev)
  650. {
  651. return 0;
  652. }
  653. static int i2c_pmic_resume(struct device *dev)
  654. {
  655. return 0;
  656. }
  657. static int i2c_pmic_suspend_noirq(struct device *dev)
  658. {
  659. return 0
  660. }
  661. #endif
  662. static const struct dev_pm_ops i2c_pmic_pm_ops = {
  663. .suspend = i2c_pmic_suspend,
  664. .suspend_noirq = i2c_pmic_suspend_noirq,
  665. .resume = i2c_pmic_resume,
  666. };
  667. static const struct of_device_id i2c_pmic_match_table[] = {
  668. { .compatible = "qcom,i2c-pmic", },
  669. { },
  670. };
  671. static const struct i2c_device_id i2c_pmic_id[] = {
  672. { "i2c-pmic", 0 },
  673. { },
  674. };
  675. MODULE_DEVICE_TABLE(i2c, i2c_pmic_id);
  676. static struct i2c_driver i2c_pmic_driver = {
  677. .driver = {
  678. .name = "i2c_pmic",
  679. .pm = &i2c_pmic_pm_ops,
  680. .of_match_table = i2c_pmic_match_table,
  681. },
  682. .probe = i2c_pmic_probe,
  683. .remove = i2c_pmic_remove,
  684. .id_table = i2c_pmic_id,
  685. };
  686. module_i2c_driver(i2c_pmic_driver);
  687. MODULE_LICENSE("GPL v2");
  688. MODULE_ALIAS("i2c:i2c_pmic");